By Topic

Formal Methods and Models for Co-Design, 2004. MEMOCODE '04. Proceedings. Second ACM and IEEE International Conference on

Date 23-25 June 2004

Filter Results

Displaying Results 1 - 25 of 67
  • Check and simulate: a case for incorporating model checking in network simulation

    Publication Year: 2004, Page(s):27 - 36
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (605 KB) | HTML iconHTML

    Existing network simulators perform reasonably well in evaluating the performance of network protocols, but lack the capability of verifying and validating the correctness of network protocols. In this paper we have extended J-Sim - an open-source, component-based compositional network simulation environment - with the model checking capability to explore the state space created by a network proto... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Bounded model checking of infinite state systems: exploiting the automata hierarchy

    Publication Year: 2004, Page(s):17 - 26
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (578 KB) | HTML iconHTML

    We present a new approach to bounded model checking that extends current methods in two ways: firstly, instead of a reduction to propositional logic, we choose a more powerful, yet decidable target logic, namely Presburger arithmetic. Secondly, instead of unwinding temporal logic formulas, we unwind corresponding ω-automata. To this end, we employ a special technique for translating safety a... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Verification of SpecC using predicate abstraction

    Publication Year: 2004, Page(s):7 - 16
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (558 KB) | HTML iconHTML

    Languages such as SystemC or SpecC offer a new design paradigm that addresses the industry's need for a fast time-to-market. However, formal verification techniques are widely applied in the hardware design industry only for low level designs, such as a netlist or RTL. The higher abstraction levels offered by these new languages are not yet amenable to rigorous, formal verification. This paper des... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Panel: given that hardware verification has been an uphill battle, what is the future of software verification?

    Publication Year: 2004, Page(s):157 - 158
    Request permission for commercial reuse | PDF file iconPDF (117 KB)
    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Checkers for SystemC designs

    Publication Year: 2004, Page(s):171 - 178
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (373 KB) | HTML iconHTML

    Today's complex systems are modeled on a high level of abstraction. In this context, C/C++-based description languages, like SystemC, become very important. The modeling features of SystemC enable adequate levels of abstraction, hardware/software integration and fast executable specifications. Using the SystemC design methodology, a system is partitioned into hardware and software. Then the module... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The ephemeral history register: flexible scheduling for rule-based designs

    Publication Year: 2004, Page(s):189 - 198
    Cited by:  Papers (3)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (533 KB) | HTML iconHTML

    The quality of high-level synthesis results is strongly dependant on the concurrency that can be found in designs. In this paper we introduce the ephemeral history register (EHR), a new primitive state element that enables concurrent scheduling of arbitrary rules in a rule-based design framework. The key properties of the EHR are that it allows multiple operations to write to the same state simult... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A framework for heterogeneous formal modeling and compositional verification of avionics systems

    Publication Year: 2004, Page(s):223 - 232
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (538 KB) | HTML iconHTML

    This paper presents a component oriented framework dedicated to the specification of embedded systems in the aeronautics domain. A component is an entity with three internal layers (hardware, operating functions and applicative functions) together with a collection of models in different domain-oriented views. A composition operation allows the expression of composition scenarios, yielding a compo... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Formal verification of pipelined processors with precise exceptions

    Publication Year: 2004, Page(s):129 - 139
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (569 KB) | HTML iconHTML

    Verification of pipelined processors is a complex and challenging issue. In this paper, we develop a methodology based on translation validation for the verification of pipelined processors that support precise exceptions and out-of-order executions. We have developed a tool integrated with STeP theorem prover for the automatic verification of pipelined architectures. Formal verification of DLX pr... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Efficient code synthesis from synchronous dataflow graphs

    Publication Year: 2004, Page(s):83 - 92
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (482 KB) | HTML iconHTML

    We present a novel approach for efficient code synthesis from synchronous dataflow specifications. The method avoids duplication of code blocks when compiling SDF graphs regardless of whether a single appearance schedule can be found for the graph or not. This also means that we can use schedules that require minimal buffer memory but are not single appearance schedules. The method has been develo... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Formal methods and software reliability

    Publication Year: 2004, Page(s):145 - 146
    Cited by:  Papers (51)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (120 KB) | HTML iconHTML

    In this position statement, the author briefly describes how the software reliability problem has changed over the years, and the primary reasons for the recent creation of the Laboratory for Reliable Software at JPL. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Curing schizophrenia by program rewriting in Esterel

    Publication Year: 2004, Page(s):39 - 48
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (455 KB) | HTML iconHTML

    Synchronous languages such as Esterel can execute a series of statements in a single "instant" of time. If this series spans a loop iteration then it is possible that a computation local to the loop will have several distinct results during that "instant", which is referred to as schizophrenia. This makes the compilation of synchronous languages into more traditional computation models (such as C ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Automated, compositional and iterative deadlock detection

    Publication Year: 2004, Page(s):201 - 210
    Cited by:  Papers (7)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (518 KB) | HTML iconHTML

    We present an algorithm to detect deadlocks in concurrent message-passing programs. Even though deadlock is inherently noncompositional and its absence is not preserved by standard abstractions, our framework employs both abstraction and compositional reasoning to alleviate the state space explosion problem. We iteratively construct increasingly more precise abstractions on the basis of spurious c... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Hierarchical reconfiguration of dataflow models

    Publication Year: 2004, Page(s):179 - 188
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (630 KB) | HTML iconHTML

    This paper presents a unified approach to analyzing patterns of reconfiguration in dataflow graphs. The approach is based on hierarchical decomposition of the structure and execution of a dataflow model. In general, reconfiguration of any part of the system might occur at any point during the execution of a model. However, arbitrary reconfiguration must often be restricted, given the constraints o... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Static priority scheduling of event triggered real time embedded systems

    Publication Year: 2004, Page(s):109 - 118
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (516 KB) | HTML iconHTML

    Real-time embedded systems are often specified as a collection of independent tasks, each generating a sequence of event-triggered code blocks, and the scheduling in this domain tries to find an execution order which satisfies all real-time constraints. Within the context of recurring real-time tasks, all previous work either allowed preemptions, or only considered dynamic scheduling, and generall... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Designing a reorder buffer in Bluespec

    Publication Year: 2004, Page(s):93 - 102
    Cited by:  Papers (3)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (495 KB) | HTML iconHTML

    Production capabilities for complex VLSI chips have outpaced the ability of current generation CAD tools to design and verify such chips effectively. Bluespec is designed to synthesize high-level descriptions in the form of guarded atomic actions into high quality structural RTL. While much work has been done on verifying both the correctness and synthesizability of Bluespec descriptions, the work... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Synchronous extensions to operation centric hardware description languages

    Publication Year: 2004, Page(s):49 - 56
    Cited by:  Papers (5)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (425 KB) | HTML iconHTML

    The abstract transition system (ATS) is a high-level hardware description framework. ATS's operation-centric abstraction permits perspicuous descriptions of complex concurrent hardware behavior as a sequence of atomic state transitions. However non-determinism in the ATS semantics prevents it from capturing the behavior of systems whose correctness depends upon both function and exact synchronous ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • System modeling and verification with UCLID

    Publication Year: 2004, Page(s):3 - 4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (81 KB) | HTML iconHTML

    Formal verification has had a significant impact on the semiconductor industry, particularly for companies that can devote significant resources to creating and deploying internally developed verification tools. Most existing verifiers model system operation at a detailed bit level. We have developed UCLID, a prototype verifier for infinite-state systems. The UCLID modeling language extends that o... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Compositional verification for secure loading of smart card applets

    Publication Year: 2004, Page(s):211 - 222
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (650 KB) | HTML iconHTML

    We present an algorithmic compositional verification method for smart card applets and control flow based safety properties expressed in a modal logic with simultaneous greatest fixed points. Our method builds on a technique proposed by Grumberg and Long who use maximal models to reduce compositional verification of finite-state parallel processes to standard model checking. We adapt this techniqu... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Designers want proofs - but show me the money

    Publication Year: 2004, Page(s):153 - 154
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (102 KB) | HTML iconHTML

    This thesis shows that designers definitely do want proofs. The first author saw ample evidence of that at Motorola, where he managed a verification CAD group, and at Synopsys, where he was involved in verification tools, customers, and in verification projects with our DesignWare component groups. Our talk will discuss some success we had with our DesignWare team. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The BUSpec platform for automated generation of verification aids for standard bus protocols

    Publication Year: 2004, Page(s):119 - 128
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (522 KB) | HTML iconHTML

    A typical verification IP (VIP) of a bus protocol such as ARM AMBA or PCI consists of a set of assertions and associated verification aids like test-benches and coverage metrics. While, several languages have been formalized for specifying assertions (examples include OVA, Sugar, ForSpec, SVA, etc), the tasks of writing test-benches that produce protocol compliant stimuli and coverage monitors tha... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Using invariants to optimize formal specifications before code synthesis

    Publication Year: 2004, Page(s):73 - 82
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (519 KB) | HTML iconHTML

    Formal specifications of required system behavior can be analyzed, verified, and validated, giving high confidence that the specification captures the desired behavior Transferring this confidence to the system implementation depends on a formal link between requirements and implementation. The automatic generation of probably correct code provides just such a link. While optimization is usually p... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • PROBMELA: a modeling language for communicating probabilistic processes

    Publication Year: 2004, Page(s):57 - 66
    Cited by:  Papers (166)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (537 KB) | HTML iconHTML

    Building automated tools to address the analysis of reactive probabilistic systems requires a simple, but expressive input language with a formal semantics based on a probabilistic operational model that can serve as starting point for verification algorithms. We introduce for probabilistic parallel programs with shared variables, message passing via synchronous and (perfect or lossy) fifo channel... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Classes and subclasses in actor-oriented design

    Publication Year: 2004, Page(s):161 - 168
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (525 KB) | HTML iconHTML

    Actor-oriented languages provide a component composition methodology that emphasizes concurrency. The interfaces to actors are parameters and ports (vs. members and methods in object-oriented languages). Actors interact with one another through their ports via a messaging schema that can follow any of several concurrent semantics (vs. procedure calls, with prevail in OO languages). Domain-specific... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Bluespec System Verilog: efficient, correct RTL from high level specifications

    Publication Year: 2004, Page(s):69 - 70
    Cited by:  Papers (31)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (129 KB) | HTML iconHTML

    Bluespec System Verilog is an EDL toolset for ASIC and FPGA design offering significantly higher productivity via a radically different approach to high-level synthesis. Many other attempts at high-level synthesis have tried to move the design language towards a more software-like specification of the behavior of the intended hardware. By means of code samples, demonstrations and measured results,... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Formal Methods and Models for Co-Design

    Publication Year: 2004, Page(s): 0_1
    Request permission for commercial reuse | PDF file iconPDF (130 KB)
    Freely Available from IEEE