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23rd IEEE VLSI Test Symposium (VTS'05)

1-5 May 2005

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  • Proceedings. 23rd IEEE VLSI Test Symposium

    Publication Year: 2005
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  • 23rd IEEE VLSI Test Symposium - Title Page

    Publication Year: 2005, Page(s):i - iii
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  • 23rd IEEE VLSI Test Symposium - Copyright Page

    Publication Year: 2005, Page(s): iv
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  • 23rd IEEE VLSI Test Symposium - Table of contents

    Publication Year: 2005, Page(s):v - x
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  • Foreword

    Publication Year: 2005, Page(s): xi
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  • Organizing Committee

    Publication Year: 2005, Page(s):xii - xiii
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  • Steering Committee

    Publication Year: 2005, Page(s): xiv
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  • Program Committee

    Publication Year: 2005, Page(s): xv
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  • list-reviewer

    Publication Year: 2005, Page(s):xvi - xvii
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  • Acknowledgments

    Publication Year: 2005, Page(s): xviii
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  • Test Technology Technical Council

    Publication Year: 2005, Page(s):xix - xxi
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  • Test technology educational program: Overview of tutorials

    Publication Year: 2005, Page(s):xxii - xxv
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (59 KB)

    The Tutorials & Education Group of the IEEE Computer Society Test Technology Technical Council (TTTC) organizes in 2005 a comprehensive set of Test Technology Tutorials to be held in conjunction with TTTC sponsored technical meetings and included in the annual and expanding Test Technology Educational Program (TTEP). TTEP intends to serve the test and design professionals offering fundamental educ... View full abstract»

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  • VTS 2004 Best Paper Award

    Publication Year: 2005, Page(s): 3
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  • VTS 2004 Best Panel Award

    Publication Year: 2005, Page(s): 4
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  • VTS 2004 Best Innovative Practices Session Award

    Publication Year: 2005, Page(s): 5
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  • A built-in self-test method for write-only content addressable memories

    Publication Year: 2005, Page(s):9 - 14
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (136 KB) | HTML iconHTML

    A novel and pragmatic built-in self test technique provides cost-effective and thorough testing and diagnosis of content addressable memories (CAMS). The method is particularly attractive for write-only CAMS, as neither the presence of a read port nor direct observability of CAM match-lines are required or testing. The underlying test algorithm uniquely exploits little known inherent properties of... View full abstract»

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  • Flash memory built-in self-diagnosis with test mode control

    Publication Year: 2005, Page(s):15 - 20
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (240 KB) | HTML iconHTML

    The objective of this paper is to present a cost-effective fault diagnosis methodology for flash memory. Flash memory is enjoying a rapid market growth. The research for flash memory testing is mainly to reduce the test cost and improve the production yield. In this paper, we propose a fault diagnosis flow for flash memory. We also propose a flexible built-in self-diagnosis (BISD) design with enha... View full abstract»

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  • Highly configurable programmable built-in self test architecture for high-speed memories

    Publication Year: 2005, Page(s):21 - 26
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (144 KB) | HTML iconHTML

    With the rapid growth in the number, the size, and the density of embedded memories in the current generation of microprocessors, developing high coverage memory built-in self-test (MBIST) engines has become increasingly challenging. The MBIST engine should provide high defect coverage and accurate diagnostic capabilities. Furthermore, MBIST engine should be accessible not only at the tester but a... View full abstract»

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  • Transition tests for high performance microprocessors

    Publication Year: 2005, Page(s):29 - 34
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (152 KB) | HTML iconHTML

    The scope and need for scan based transition tests in the context of high volume manufacturing testing of microprocessors is discussed. A classification of transition faults for latch based design is presented. Finally, we discuss a silicon experiment to understand the most fundamental issue of scan based transition testing viz. their robustness. View full abstract»

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  • On silicon-based speed path identification

    Publication Year: 2005, Page(s):35 - 41
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (200 KB) | HTML iconHTML

    Speed path identification is an indispensable step for pushing the design timing wall and for developing the final speed binning strategy in production test. For complex high-performance designs, pre-silicon timing tools have so far not been able to deliver satisfactory results in predicting the actual speed limiting paths on the silicon. The actual speed paths are mostly uncovered through test an... View full abstract»

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  • At-speed transition fault testing with low speed scan enable

    Publication Year: 2005, Page(s):42 - 47
    Cited by:  Papers (29)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (176 KB) | HTML iconHTML

    With today's design size in millions of gates and working frequency in gigahertz range, at-speed test is crucial. The launch-off-shift method has several advantages over the launch-off-capture but imposes strict requirements on transition fault testing due to at-speed scan enable signal. A novel scan-based at-speed test is proposed which generates multiple local fast scan enable signals. The scan ... View full abstract»

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  • 1C: IP Session ?? Multisite Testing

    Publication Year: 2005, Page(s): 49
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  • Minimal March tests for unlinked static faults in random access memories

    Publication Year: 2005, Page(s):53 - 59
    Cited by:  Papers (28)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (144 KB) | HTML iconHTML

    New minimal March test algorithms are proposed for detection of (all) unlinked static faults in random access memories. In particular, a new minimal March MSS test of complexity I8N is introduced detecting all realistic simple static faults, as March SS (22N), (S. Hamdioui, van de Goor, Rodgers, MTDT 2002). View full abstract»

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  • Modeling and testing comparison faults for ternary content addressable memories

    Publication Year: 2005, Page(s):60 - 65
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (168 KB) | HTML iconHTML

    This paper presents the comparison faults of TCAMs based on physical defects, such as shorts between two circuit nodes and transistor stuck-open and stuck-on faults. Accordingly, several comparison fault models are proposed. A March-like test algorithm for comparison faults is also proposed. The test algorithm only requires 4N Write operations, 3N Erase operations, and (4N+2B) Compare operations t... View full abstract»

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  • SRAM retention testing: zero incremental time integration with March algorithms

    Publication Year: 2005, Page(s):66 - 71
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (136 KB) | HTML iconHTML

    Testing data retention faults (DRFs), particularly in integrated systems on chip comprised of very large number of various sizes and types of embedded SRAMs is challenging and typically time-consuming due to the required pause time that needs to be introduced in the test session. This paper proposes a novel technique, referred to as pre-discharge write test mode (PDWTM), that effectively integrate... View full abstract»

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