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VLSI Test Symposium, 2005. Proceedings. 23rd IEEE

Date 1-5 May 2005

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  • Proceedings. 23rd IEEE VLSI Test Symposium

    Publication Year: 2005
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  • 23rd IEEE VLSI Test Symposium - Title Page

    Publication Year: 2005 , Page(s): i - iii
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  • 23rd IEEE VLSI Test Symposium - Copyright Page

    Publication Year: 2005 , Page(s): iv
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  • 23rd IEEE VLSI Test Symposium - Table of contents

    Publication Year: 2005 , Page(s): v - x
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  • Foreword

    Publication Year: 2005 , Page(s): xi
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  • Organizing Committee

    Publication Year: 2005 , Page(s): xii - xiii
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  • Steering Committee

    Publication Year: 2005 , Page(s): xiv
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  • Program Committee

    Publication Year: 2005 , Page(s): xv
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  • list-reviewer

    Publication Year: 2005 , Page(s): xvi - xvii
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  • Acknowledgments

    Publication Year: 2005 , Page(s): xviii
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  • Test Technology Technical Council

    Publication Year: 2005 , Page(s): xix - xxi
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  • Test technology educational program: Overview of tutorials

    Publication Year: 2005 , Page(s): xxii - xxv
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (59 KB)  

    The Tutorials & Education Group of the IEEE Computer Society Test Technology Technical Council (TTTC) organizes in 2005 a comprehensive set of Test Technology Tutorials to be held in conjunction with TTTC sponsored technical meetings and included in the annual and expanding Test Technology Educational Program (TTEP). TTEP intends to serve the test and design professionals offering fundamental education and expert knowledge in state-ofthe- art test technology topics. Participation in TTEP-organized tutorials is credited by TTTC. Each full day tutorial corresponds to four TTEP units. Upon completion of each sixteen TTEP units official accreditation in the form of an "IEEE TTTC Test Technology Certificate" will be presented to the participants. In addition to the tutorials, certified university courses and industrial seminars related to test technology can also be included in TTEP and the participation in these credited similar to TTEP tutorials. For information on TTEP 2005 please visit the TTEP web site http://tab.computer.org/tttc/teg/ttep. The test technology tutorials of the VTS 2005 technical program are part of TTEP 2005. View full abstract»

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  • VTS 2004 Best Paper Award

    Publication Year: 2005 , Page(s): 3
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  • VTS 2004 Best Panel Award

    Publication Year: 2005 , Page(s): 4
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  • VTS 2004 Best Innovative Practices Session Award

    Publication Year: 2005 , Page(s): 5
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  • A built-in self-test method for write-only content addressable memories

    Publication Year: 2005 , Page(s): 9 - 14
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (136 KB) |  | HTML iconHTML  

    A novel and pragmatic built-in self test technique provides cost-effective and thorough testing and diagnosis of content addressable memories (CAMS). The method is particularly attractive for write-only CAMS, as neither the presence of a read port nor direct observability of CAM match-lines are required or testing. The underlying test algorithm uniquely exploits little known inherent properties of pseudorandom patterns generated by linear feedback shift registers in a test-time and hardware-efficient BIST implementation. View full abstract»

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  • Flash memory built-in self-diagnosis with test mode control

    Publication Year: 2005 , Page(s): 15 - 20
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (240 KB) |  | HTML iconHTML  

    The objective of this paper is to present a cost-effective fault diagnosis methodology for flash memory. Flash memory is enjoying a rapid market growth. The research for flash memory testing is mainly to reduce the test cost and improve the production yield. In this paper, we propose a fault diagnosis flow for flash memory. We also propose a flexible built-in self-diagnosis (BISD) design with enhanced test mode control, which reduces the test time and diagnostic data shift-out cycles by using parallel programming and erasure and employing a parallel shift-out mechanism. The area overhead of our BISD circuit is only about 0.5% for a 256Mb commodity flash memory chip. Experimental results from industrial chips show that the proposed diagnosis methodology has high accuracy in distinguishing the fault type. View full abstract»

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  • Highly configurable programmable built-in self test architecture for high-speed memories

    Publication Year: 2005 , Page(s): 21 - 26
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (144 KB) |  | HTML iconHTML  

    With the rapid growth in the number, the size, and the density of embedded memories in the current generation of microprocessors, developing high coverage memory built-in self-test (MBIST) engines has become increasingly challenging. The MBIST engine should provide high defect coverage and accurate diagnostic capabilities. Furthermore, MBIST engine should be accessible not only at the tester but also at the system. We present our work to develop a MBIST architecture that fulfils all such requirements and supports various flavors of embedded SRAMs. Extensive utilization of the proposed architecture in our products will result in increased productivity by reducing the development time and the verification and productization effort. View full abstract»

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  • Transition tests for high performance microprocessors

    Publication Year: 2005 , Page(s): 29 - 34
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (152 KB) |  | HTML iconHTML  

    The scope and need for scan based transition tests in the context of high volume manufacturing testing of microprocessors is discussed. A classification of transition faults for latch based design is presented. Finally, we discuss a silicon experiment to understand the most fundamental issue of scan based transition testing viz. their robustness. View full abstract»

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  • On silicon-based speed path identification

    Publication Year: 2005 , Page(s): 35 - 41
    Cited by:  Papers (14)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (200 KB) |  | HTML iconHTML  

    Speed path identification is an indispensable step for pushing the design timing wall and for developing the final speed binning strategy in production test. For complex high-performance designs, pre-silicon timing tools have so far not been able to deliver satisfactory results in predicting the actual speed limiting paths on the silicon. The actual speed paths are mostly uncovered through test and silicon debug, where tremendous manual effort is involved. This paper presents a novel approach as the first step for automating the speed path identification process. Our approach is silicon-based, meaning that timing information is extracted through testing of silicon sample chips. We call this step silicon learning. Based on silicon learning, we present an iterative flow for speed path identification. Experimental results are presented to explain the new methodologies and to demonstrate the effectiveness of our techniques. View full abstract»

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  • At-speed transition fault testing with low speed scan enable

    Publication Year: 2005 , Page(s): 42 - 47
    Cited by:  Papers (21)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (176 KB) |  | HTML iconHTML  

    With today's design size in millions of gates and working frequency in gigahertz range, at-speed test is crucial. The launch-off-shift method has several advantages over the launch-off-capture but imposes strict requirements on transition fault testing due to at-speed scan enable signal. A novel scan-based at-speed test is proposed which generates multiple local fast scan enable signals. The scan enable control information is encapsulated in the test data and transferred during the scan operation. A new scan cell, referred to as last transition generator (LTG), is inserted in the scan chains to generate the fast local scan enable signal. The proposed technique is robust, practice-oriented and suitable for use in an industrial flow. View full abstract»

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  • 1C: IP Session ?? Multisite Testing

    Publication Year: 2005 , Page(s): 49
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  • Minimal March tests for unlinked static faults in random access memories

    Publication Year: 2005 , Page(s): 53 - 59
    Cited by:  Papers (21)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (144 KB) |  | HTML iconHTML  

    New minimal March test algorithms are proposed for detection of (all) unlinked static faults in random access memories. In particular, a new minimal March MSS test of complexity I8N is introduced detecting all realistic simple static faults, as March SS (22N), (S. Hamdioui, van de Goor, Rodgers, MTDT 2002). View full abstract»

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  • Modeling and testing comparison faults for ternary content addressable memories

    Publication Year: 2005 , Page(s): 60 - 65
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (168 KB) |  | HTML iconHTML  

    This paper presents the comparison faults of TCAMs based on physical defects, such as shorts between two circuit nodes and transistor stuck-open and stuck-on faults. Accordingly, several comparison fault models are proposed. A March-like test algorithm for comparison faults is also proposed. The test algorithm only requires 4N Write operations, 3N Erase operations, and (4N+2B) Compare operations to cover 100% comparison faults for an N × B-bit TCAM. Compared with the previous work, the proposed test algorithm has lower time complexity for TCAMs with wide words and the time complexity is independent of the number of stuck-on faults. Also, the algorithm can cover all defects that cause a failed Compare operation. Moreover, it can be realized by built-in self-test circuitry with lower area cost. View full abstract»

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  • SRAM retention testing: zero incremental time integration with March algorithms

    Publication Year: 2005 , Page(s): 66 - 71
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (136 KB) |  | HTML iconHTML  

    Testing data retention faults (DRFs), particularly in integrated systems on chip comprised of very large number of various sizes and types of embedded SRAMs is challenging and typically time-consuming due to the required pause time that needs to be introduced in the test session. This paper proposes a novel technique, referred to as pre-discharge write test mode (PDWTM), that effectively integrates the testing of DRF within "regular" March algorithms such that the rate (speed) of the latter remains unaltered. That is, the PDWTM enables DRF testing without incurring the additional cycles or pauses in the March test execution thereby enabling additional coverage at no expense in terms of overall test time. We show that DRFs can be easily detected by pre-discharging bit lines before a write operation. Here, the PDWTM is evaluated using both high-speed and low power memory cells, representing two extreme cases based on the typical memory design methodologies. View full abstract»

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