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Advanced Thermal Processing of Semiconductors, 2004. RTP 2004. 12th IEEE International Conference on

Date 28-30 Sept. 2004

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  • 12th IEEE International Conference on Advanced Thermal Processing of Semiconductors

    Publication Year: 2004, Page(s): 149
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  • 12th IEEE International Conference on Advanced Thermal Processing of Semiconductors

    Publication Year: 2004, Page(s): 1
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  • 12th IEEE International Conference on Advanced Thermal Processing of Semiconductors

    Publication Year: 2004, Page(s): 173
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  • 12th IEEE International Conference on Advanced Thermal Processing of Semiconductors (IEEE Cat. No.03EX847)

    Publication Year: 2004
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    Publication Year: 2004, Page(s): 0_2
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  • 12th IEEE International Conference on Advanced Thermal Processing of Semiconductors

    Publication Year: 2004, Page(s): 0_3
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  • Copyright

    Publication Year: 2004, Page(s): 0_4
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  • Table of contents

    Publication Year: 2004, Page(s):0_5 - 0_8
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  • [Blank page]

    Publication Year: 2004, Page(s): 0_9
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  • IEEE RPT Conference Committee

    Publication Year: 2004, Page(s): 0_10
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  • Call for papers

    Publication Year: 2004, Page(s): 0_11
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  • RTP Conference Achievement Awards

    Publication Year: 2004, Page(s):0_12 - 0_13
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  • Brunce W. Peuse - award

    Publication Year: 2004, Page(s):0_16 - 0_17
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  • [Blank page]

    Publication Year: 2004, Page(s): 0_18
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  • [Blank page]

    Publication Year: 2004, Page(s): 2
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  • RTP application and technology options for the sub-45 nm nodes

    Publication Year: 2004, Page(s):3 - 36
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3146 KB) | HTML iconHTML

    As device dimensions have reduced to nanometer length scales, rapid thermal processing (RTP) has emerged as the key approach for providing the low thermal budget and ultra-pure process conditions that are essential in advanced fabrication schemes. As further progress in electronic technology becomes increasingly dependent on success in rapid development cycles that include both materials innovatio... View full abstract»

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  • Infusion processing solutions for USJ and localized strained-Si using gas cluster ion beams

    Publication Year: 2004, Page(s):37 - 45
    Cited by:  Papers (1)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2286 KB) | HTML iconHTML

    Infusion processing using gas cluster ion beam (GCIB) technology provides several new capabilities in the areas of ultra shallow junction formation and localized or blanket SiGe formation resulting in strained-Si. This room temperature process requires only solid phase epitaxy (SPE) anneals (<700degC) for diffusionless activation and high quality SiGe or Ge formation. Initial tests indicate all... View full abstract»

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  • [Blank page]

    Publication Year: 2004, Page(s): 46
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  • Dynamic surface anneal: activation without diffusion

    Publication Year: 2004, Page(s):47 - 51
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1898 KB) | HTML iconHTML

    The continued scaling of devices in accordance with Moore's law requires activation of some implants such as the source-drain extensions, SDEs, with as little diffusion as possible. New options in thermal processing are described and compared. Thermal flux annealing is the regime where power density is high enough to cause local heating but not so high as to eliminate heat transfer entirely. If en... View full abstract»

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    Publication Year: 2004, Page(s): 52
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  • Athermal annealing of silicon implanted layer: beyond the light

    Publication Year: 2004, Page(s):53 - 60
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1993 KB) | HTML iconHTML

    The mechanism of annealing silicon implanted layers has been a subject of debate for more than three decades. The great majority of the research work is restricted to only phenomenological results and elaborating changes in the resistivity of annealed layers. Less obvious parameters such as mobility or carrier lifetime are investigated only occasionally. Restrictions on the duration of thermal exp... View full abstract»

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  • Leveraging a low pressure thermal module to meet the challenges of advanced device manufacturing

    Publication Year: 2004, Page(s):61 - 72
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2246 KB) | HTML iconHTML

    Fulfilling the needs of advanced semiconductor device manufacturing presents continued challenges to the developers and manufacturers of capital equipment. More than twenty years of RTP equipment evolution and development has resulted in the availability of a select few technologies that are capable of delivering the demanding performance required to manufacturer today's advanced semiconductor dev... View full abstract»

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  • Integration of a long pulse laser thermal process for ultra shallow junction formation of CMOS devices

    Publication Year: 2004, Page(s):73 - 78
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2049 KB) | HTML iconHTML

    We present results on ultra-shallow junction formation for the sub 65 nm CMOS node by means of a long pulse laser thermal process (LP-LTP). This method achieve to form abrupt and ultra-shallow junctions with low resistivities, but the different irradiated structures like transistor gates need to be preserved. To assess the integration of the laser process in the fabrication of a CMOS device, we st... View full abstract»

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  • Optimal design of pulse forming networks and flashlamps for thermal flash processes

    Publication Year: 2004, Page(s):79 - 88
    Cited by:  Papers (1)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2080 KB) | HTML iconHTML

    The design of electrical pulse forming networks (PFN), using multiple coils and energy storage capacitors, has a profound effect on the intensity and temporal shape of the radiant flash emitted from a flashlamp. In addition, the geometrical dimensions of a flashlamp control its electrical impedance (i.e. its interaction with the PFN), and also its explosion energy (i.e. its lifetime expectancy). W... View full abstract»

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  • Design of a hot wall-based low temperature annealing system and its process applications

    Publication Year: 2004, Page(s):89 - 93
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1881 KB) | HTML iconHTML

    A hot wall-based low temperature annealing system using resistively heated, stacked hot plates was designed and tested for low temperature (100~500degC) annealing applications for 200 mm and 300 mm wafers. The system is designed to process five wafers simultaneously for productivity enhancement purposes. Thermal properties of the system and wafer temperature profiles during low temperature anneali... View full abstract»

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