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Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.

6-8 Dec. 2004

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Displaying Results 1 - 25 of 238
  • On test vector reordering for combinational circuits

    Publication Year: 2004, Page(s):772 - 775
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (201 KB) | HTML iconHTML

    The cost of testing is a major factor in the cost of digital system design. In order to reduce the test application time, it is required to order the test vectors in such a way that it reduces the time a defective chip spends on a tester until the defect is detected. In this paper, we propose an efficient test vector reordering technique that significantly reduces both the time and memory complexi... View full abstract»

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  • Architecture of a data compression-based low-power scan-path

    Publication Year: 2004, Page(s):768 - 771
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (220 KB) | HTML iconHTML

    This paper shows a novel scan-cell architecture that reduces both power consumption and the total consumed energy using a data compression technique. Based on the data compression methodology, the vector set is partitioned into two repeated and unrepeated segments. The repeated part, which is common among some of the vectors, is not changed during the new scan-path where new test vector is filled.... View full abstract»

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  • STBus transaction level models using SystemC 2.0

    Publication Year: 2004, Page(s):347 - 350
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (186 KB) | HTML iconHTML

    SystemC 2.0 facilitates the development of transaction level models (TLM) that are models of the hardware system components at a high level of abstraction. System architects can quickly develop these models and be ready with an executable specification of the hardware blocks as soon as the initial functional specifications of the system are decided. In this paper, we present a SystemC 2.0 TLM of t... View full abstract»

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  • Integrated wide-band FSK demodulator based on ISPD PLL

    Publication Year: 2004, Page(s):514 - 517
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (171 KB) | HTML iconHTML

    Classic designs of FSK demodulator generally employ conventional phase locked loop second order (PLL). In this paper, we explore the design of a new architecture (without using any filters) of high-performance integrated FSK demodulator using ISPD PLL (inverse sine phase detector PLL). This architecture has clearly shown superior frequency performances, such as large bandwidth, large keep range, l... View full abstract»

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  • Platform and architecture adequacy in SoC environment: a case study

    Publication Year: 2004, Page(s):762 - 767
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (305 KB) | HTML iconHTML

    This work aims to compare several tools and SoC platforms according to the following key parameters: FPGA architecture, coprocessor and accelerator integration, RTOS and HW-SW refinement tools. These key parameters are required to select a flexible and efficient SoC platform (and the associated tools) in order to implement an efficient PACM (processor-accelerator-coprocessor-memory) architecture m... View full abstract»

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  • IP integration methodology for SoC design

    Publication Year: 2004, Page(s):343 - 346
    Cited by:  Papers (5)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (267 KB) | HTML iconHTML

    Integrating intellectual property (IP) components into system-on-chip (SoC) designs requires the use of a generic parameterizable hardware/software interface to increase reuse efficiently, quality and productivity of SoC design. In this paper, we propose a design approach for wrapping the cycle accurate bit accurate (CABA) interface of hardware IPs. This interface integrates many communication and... View full abstract»

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  • Injection locked oscillators for quadrature generation at radio frequency

    Publication Year: 2004, Page(s):124 - 127
    Cited by:  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (273 KB) | HTML iconHTML

    The design of quadrature signal generators is one of the most challenging issues in modern RF transceivers. After a brief review of conventional techniques, this paper presents injection locked oscillators as a viable alternative to achieve high performance and low power consumption. Two different architectures, realized in a 0.18 μm CMOS technology, are presented and compared. The first shows ... View full abstract»

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  • Fast Montgomery modular multiplication by pipelined CSA architecture

    Publication Year: 2004, Page(s):144 - 147
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (197 KB) | HTML iconHTML

    Montgomery modular multiplication algorithm is commonly used in implementations of the RSA cryptosystem or other cryptosystems based on modular arithmetic. There are several architectures for speed up its calculations. In this paper, we use carry save adder (CSA) architecture and pipeline it to increase its performance. We show that this architecture has greater performance for FPGA design than ot... View full abstract»

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  • An ultra low-voltage CMOS OTA Miller with rail-to-rail operation

    Publication Year: 2004, Page(s):223 - 226
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (220 KB) | HTML iconHTML

    This work describes a simple topology for implementing a low voltage rail-to-rail CMOS Miller OTA with differential pair using bulk driven and DC shifters. Since the transistors work on weak inversion, the topology requires a 600 mV power supply and consumes only 420 nW on the 0.35 μm TSMC CMOS process. The voltage swing and the frequency response are almost independent of the power supply volt... View full abstract»

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  • Novel technique for mechanical stresses determination in thin films

    Publication Year: 2004, Page(s):692 - 695
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (258 KB) | HTML iconHTML

    A novel technique for mechanical stresses determination in thin films has been proposed and tested for thin metal films on refractory metals basis. The new method provides the possibility of mechanical stresses distribution determination along of the films thickness. Experimental results concern films of Mo and alloys of Mo-Re deposited with a magnetron sputtering. Films material and sputtering co... View full abstract»

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  • HW-SW design methodologies used for a MPEG video compressor synthesis

    Publication Year: 2004, Page(s):758 - 761
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (241 KB) | HTML iconHTML

    In the last years many new concepts appeared for the system design, with the so-called HW/SW co-design based on system (SoC) and virtual components. Those concepts rely to methodologies that try to integrate HW and SW design techniques in just one consistent system-level methodology allowing to work in a way that is more secure (specifications and developments are verifiable), more efficient (cost... View full abstract»

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  • Mixing linguistic and formal techniques for high-level requirements engineering

    Publication Year: 2004, Page(s):339 - 342
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (226 KB) | HTML iconHTML

    We propose a methodology and a tool for the modeling and validation of requirements as well as elicitation of missing requirements. Modeling relies on a formally structured linguistic approach. Validation is performed using characteristic error patterns. Elicitation of missing requirements is based on Boolean logic concepts. This methodology provides effective modeling and early detection of error... View full abstract»

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  • Multi-dimensional approach to high resolution and high speed binary-to-thermometer decoding

    Publication Year: 2004, Page(s):509 - 512
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (205 KB) | HTML iconHTML

    A binary-to-thermometer decoding logic that allows high speed decoding at high resolution is presented. DNL performance of both binary-weighted and thermometer-coded decoding schemes in digital-to-analog conversion is discussed. Other works on binary-to-thermometer decoder are explored. In multi-dimensional decoding, a small decoding circuit is attached to each current cell in a current-steering D... View full abstract»

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  • 10-transistor 1-bit adders for n-bit parallel adders

    Publication Year: 2004, Page(s):174 - 177
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (177 KB) | HTML iconHTML

    Two designs of 10-transistor 1-bit adder are described in this paper. The output voltages levels of these 1-bit adders have a maximum of one threshold voltage (VT) loss. This is an important property since previously described 10-transistor designs suffer from two-threshold voltage loss. This also allows the successful use of these designs in a 4-bit ripple carry adder (RCA) and a 12-bi... View full abstract»

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  • Methodology to compare on-state breakdown loci of GaAs FET's

    Publication Year: 2004, Page(s):258 - 261
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (196 KB) | HTML iconHTML

    On-state breakdown loci of three technologies (power PHEMT, PHEMT and MESFET) have been measured using gate-current extraction techniques. We present a precise understanding of the correlation between the on-state breakdown voltage (BV on-state) locus and the reverse Igs-Vgs characteristics. From the comparison of Igs-Vgs characteristics, this study has allowed establishing a methodology to compar... View full abstract»

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  • High resolution self-calibrated ADCs for software defined radios

    Publication Year: 2004, Page(s):120 - 123
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (215 KB) | HTML iconHTML

    Next generation transceiver operating with different standards necessitates the existence of a wide bandwidth and highly linear ADC to enable software defined radios (SDR). Several techniques dealing with the design and implementation of several ADC architectures to provide the stringent requirements of the wide-bandwidth transceivers are discussed. Works concerning the design of high-resolution p... View full abstract»

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  • A high performance reconfigurable implementation of DES-like algorithms

    Publication Year: 2004, Page(s):140 - 143
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (182 KB) | HTML iconHTML

    Reconfigurable computing has grown to become an important and large field of research. It offers advantages over traditional hardware and software implementation of computational algorithms. It is based on using field programmable gate arrays (FPGAs), which can be configured after fabrication to take advantage of a hardware design but still maintain the flexibility of software. Particular applicat... View full abstract»

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  • Power estimation of crossbar interconnects using fully analytical approach

    Publication Year: 2004, Page(s):219 - 222
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (195 KB) | HTML iconHTML

    In this paper, a new simple yet accurate model for determining power consumption of mux-based crossbar interconnects is introduced. The analytical model makes use of the modified n-th power law MOSFET model that is appropriate for short channel devices. The proposed model is compact and scalable which makes it suitable for power estimation CAD tools. The results of proposed model for a current and... View full abstract»

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  • Design of 0.35 μm SiGe LNAs for UWB communications systems

    Publication Year: 2004, Page(s):37 - 40
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (188 KB) | HTML iconHTML

    Simple low-noise, low-power, and gain-controlled 0.35 μm SiGe UWB amplifiers for 3.1-10.6 GHz radios are presented. Simulation results of common-base BiCMOS LNAs give a gain controlled from 3.8 up to 15.5 dB over a bandwidth range from 10.6 down to 3.1 GHz, respectively. These LNAs achieved a noise figure that is less than 5.5 dB and power dissipation less than 6.6 mW under a power supply of &p... View full abstract»

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  • Digital compensation of branches imbalance effects in LINC transmitters

    Publication Year: 2004, Page(s):688 - 691
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (195 KB) | HTML iconHTML

    A study of the branch complex gain imbalance effects, as a distortion source, in term of adjacent channel power ratio and signal dynamic range is carried out in this paper. Although a linearity improvement is achieved using a digital predistortion when considering the imbalanced LINC transmitter as a memoryless nonlinear system, this method suffers from a limited dynamic range restitution at the o... View full abstract»

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  • A prototyping platform based on a PCI micronetwork and Leon multiprocessor system

    Publication Year: 2004, Page(s):754 - 757
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (236 KB) | HTML iconHTML

    System-on-chip (SoC) designs provide integrated solutions to challenging design problems in the telecommunication, multimedia, and consumer electronics domains. Much of the progress in these fields hinges on the designers ability to conceive complex electronic engines under strong time to market pressure. Success relies on using appropriate design and process technologies, on the ability to interc... View full abstract»

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  • Asynchronous packet-switch for SoC

    Publication Year: 2004, Page(s):335 - 338
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (255 KB) | HTML iconHTML

    System-on-chip (SoC) design is facing increasing difficulties in its integration, global wiring delay and power dissipation. Interconnection network technology has the advantage over the conventional bus technology in its scalability; on the other hand, asynchronous circuit design technology may offer power saving and tackle the clock-skew problem. The combination of these two technologies therefo... View full abstract»

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  • VLSI implementation of a floating-point divider

    Publication Year: 2004, Page(s):505 - 508
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (194 KB) | HTML iconHTML

    In this paper, we present the VLSI implementation of a low power floating-point divider in CMOS 0.18 μm technology using radix-2 over redundant number system. This divider implementation is well suited for IEEE 754 floating point standard and can be widely used in DSP applications. In the proposed divider designs, different PPM adders, based on 24, 22 and new 16-transistor circuits are used to ... View full abstract»

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  • Design of asynchronous circuit primitives using MOS current-mode logic (MCML)

    Publication Year: 2004, Page(s):170 - 173
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (215 KB) | HTML iconHTML

    This paper introduces and compares two topologies for the C-element in MCML and two topologies for double-edge-triggered flip-flop in MCML. Based on the simulation results, an asynchronous MCML C-element dissipates four times less power than conventional static CMOS C-element at the same throughout of 1.9 GHz. Also, MCML double-edge-triggered flip-flop runs up to three times faster than the conven... View full abstract»

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  • Parallel alias reduction for MP3 decoding

    Publication Year: 2004, Page(s):438 - 441
    Cited by:  Papers (1)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (232 KB) | HTML iconHTML

    Applying parallelism to each hardware circuit and each software program can decrease its response time and increase its performance. Parallel realization of MP3 yields higher performance of the codec block and this issue is important especially when real time encoding and decoding is considered. This paper focuses on the alias reduction component of the MP3 decoder. MP3 is chosen as a case study s... View full abstract»

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