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Microelectronics, 2004. ICM 2004 Proceedings. The 16th International Conference on

Date 6-8 Dec. 2004

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Displaying Results 1 - 25 of 238
  • Digital and analog system testing: fundamentals and new challenges

    Publication Year: 2004 , Page(s): 8 - 10
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (145 KB) |  | HTML iconHTML  

    This paper first introduces the fundamentals of digital testing with a special emphasis on the quality-cost tradeoff which guarantees the viability of the process. Different test solutions are then presented with the corresponding advantages and drawbacks. It is demonstrated that the structural test approach is the most viable solution. Finally, the challenges of system-on-chip testing are specifi... View full abstract»

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  • A new low voltage CMOS current controlled oscillator with minimum phase noise

    Publication Year: 2004 , Page(s): 616 - 619
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (188 KB) |  | HTML iconHTML  

    In this paper, we present a design of a current controlled oscillator in a 0.35 μm CMOS process. Owing to its high degree of controllability, the second generation current conveyor is used as a basic block for our oscillator. Thus, the first step in our design is to develop an improved version of second generation current conveyors operating at ±1.5 V and presenting a current controlled ... View full abstract»

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  • Design of asynchronous circuit primitives using MOS current-mode logic (MCML)

    Publication Year: 2004 , Page(s): 170 - 173
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (215 KB) |  | HTML iconHTML  

    This paper introduces and compares two topologies for the C-element in MCML and two topologies for double-edge-triggered flip-flop in MCML. Based on the simulation results, an asynchronous MCML C-element dissipates four times less power than conventional static CMOS C-element at the same throughout of 1.9 GHz. Also, MCML double-edge-triggered flip-flop runs up to three times faster than the conven... View full abstract»

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  • Voltage and sizing optimization for low power buffered digital designs

    Publication Year: 2004 , Page(s): 20 - 23
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (169 KB)  

    A circuit design style with separate logic and buffer stages is investigated for its energy and delay characteristics. Then a new numerical approach is proposed for determining the optimum transistor sizing and supply voltage according to the minimum energy-delay product as a figure of merit (FOM). The results agree perfectly with the simulation data gathered from the SPICE simulation and are much... View full abstract»

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  • Design of 0.35 μm SiGe LNAs for UWB communications systems

    Publication Year: 2004 , Page(s): 37 - 40
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (188 KB) |  | HTML iconHTML  

    Simple low-noise, low-power, and gain-controlled 0.35 μm SiGe UWB amplifiers for 3.1-10.6 GHz radios are presented. Simulation results of common-base BiCMOS LNAs give a gain controlled from 3.8 up to 15.5 dB over a bandwidth range from 10.6 down to 3.1 GHz, respectively. These LNAs achieved a noise figure that is less than 5.5 dB and power dissipation less than 6.6 mW under a power supply of &p... View full abstract»

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  • Time partitioning framework for fully reconfigurable systems

    Publication Year: 2004 , Page(s): 742 - 745
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (209 KB) |  | HTML iconHTML  

    The SRAM technologies allow the FPGA device to be reconfigured by loading new configuration data. Real time reconfiguration can be performed by loading each configuration data then reinitializing the device. The entire process (loading and reinitializing) requires less than some milliseconds, which can be used to fit a large application onto the FPGA device by partitioning the application over tim... View full abstract»

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  • Detection of bulk and leaky acoustic microwaves in piezoelectric crystal by wavelet technique

    Publication Year: 2004 , Page(s): 582 - 584
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (113 KB) |  | HTML iconHTML  

    In this paper, we propose a new approach for bulk and leaky detection of an acoustic microwave signal. For this reason, we have used a wavelet transform as a numerical analysis method. The originality of this model consists of the local analysis signal singularities where abrupt events appear and hence access to hidden information by using the scale of this transform as up scaling parameters. Thes... View full abstract»

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  • The effect of carrier frequency offset for MC-CDMA systems over Rayleigh multi-path fading channels

    Publication Year: 2004 , Page(s): 625 - 628
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (220 KB) |  | HTML iconHTML  

    In this paper, we consider the MC-CDMA system, which is a combination of the multi-carrier modulation technique and the CDMA, multiple access technique. The performance of the system is investigated over AWGN channels as well as over Rayleigh multi-path fading channels. We show that for a given spreading factor, the performance of the system degrades as the number of the sub-carriers increases. Fu... View full abstract»

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  • A new technique for designing high performance front-end sample and hold circuits

    Publication Year: 2004 , Page(s): 16 - 19
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (249 KB) |  | HTML iconHTML  

    Based on the behavioral modelisation of each element in a sample and hold (S/H) circuit, and using the Verilog-A language, such approach effectively allow us to get the best performances that the circuit can give. Using switched capacitor differential topology, double bootstrapped switches and several native transistors, we optimized with Verilog-A models the amplifier and the switches to end up w... View full abstract»

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  • Parallel alias reduction for MP3 decoding

    Publication Year: 2004 , Page(s): 438 - 441
    Cited by:  Patents (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (232 KB) |  | HTML iconHTML  

    Applying parallelism to each hardware circuit and each software program can decrease its response time and increase its performance. Parallel realization of MP3 yields higher performance of the codec block and this issue is important especially when real time encoding and decoding is considered. This paper focuses on the alias reduction component of the MP3 decoder. MP3 is chosen as a case study s... View full abstract»

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  • 10-transistor 1-bit adders for n-bit parallel adders

    Publication Year: 2004 , Page(s): 174 - 177
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (177 KB) |  | HTML iconHTML  

    Two designs of 10-transistor 1-bit adder are described in this paper. The output voltages levels of these 1-bit adders have a maximum of one threshold voltage (VT) loss. This is an important property since previously described 10-transistor designs suffer from two-threshold voltage loss. This also allows the successful use of these designs in a 4-bit ripple carry adder (RCA) and a 12-bi... View full abstract»

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  • On test vector reordering for combinational circuits

    Publication Year: 2004 , Page(s): 772 - 775
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (201 KB) |  | HTML iconHTML  

    The cost of testing is a major factor in the cost of digital system design. In order to reduce the test application time, it is required to order the test vectors in such a way that it reduces the time a defective chip spends on a tester until the defect is detected. In this paper, we propose an efficient test vector reordering technique that significantly reduces both the time and memory complexi... View full abstract»

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  • Contributions to development of IGBT on SiC technologies

    Publication Year: 2004 , Page(s): 368 - 371
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (248 KB) |  | HTML iconHTML  

    A punch through insulated gate bipolar transistor realized on silicon carbide (4H-SiC) is presented. The IGBT chip consists of a parallel connection of ten thousands elementary cells. The cell equivalent circuit is designed with a MOSFET and a bipolar transistor in a Darlington configuration. The IGBT presented in this paper has one epilayer (cheaper), a buffer layer between substrate and epilayer... View full abstract»

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  • RTDT: a static QoS manager, RT scheduling, HW/SW partitioning CAD tool

    Publication Year: 2004 , Page(s): 50 - 54
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (285 KB) |  | HTML iconHTML  

    The hardware (HW)/software (SW) partitioning relies on two subtasks: the cost function and the real time (RT) analysis. Besides these two subtasks, the proposed generic framework also called RT design trotter (RTDT) processes the problem of the quality of service (QoS) management. The aim of this paper is to add a new dimension to solution selection, namely the guarantee of QoS from both applicati... View full abstract»

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  • Asynchronous packet-switch for SoC

    Publication Year: 2004 , Page(s): 335 - 338
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (255 KB) |  | HTML iconHTML  

    System-on-chip (SoC) design is facing increasing difficulties in its integration, global wiring delay and power dissipation. Interconnection network technology has the advantage over the conventional bus technology in its scalability; on the other hand, asynchronous circuit design technology may offer power saving and tackle the clock-skew problem. The combination of these two technologies therefo... View full abstract»

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  • Numerical study of the dynamic signal in the surface channel charge coupled devices

    Publication Year: 2004 , Page(s): 585 - 588
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (184 KB) |  | HTML iconHTML  

    The devices to transfer of load (C.C.D) are used for the realization of logical or digital function and in imagery. Thus, the fast evolution of the techniques of manufacture of the circuits on big scale integration resulted in reduction of the measurements of arrangements. This reduction makes appear of the phenomena of control of the load transfer. In this work, we were interested in the evolutio... View full abstract»

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  • The 1:6 phased demultiplexer circuit

    Publication Year: 2004 , Page(s): 629 - 632
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (250 KB) |  | HTML iconHTML  

    The behavior of the 1:6 phased demultiplexer (PDMUX6) circuit is analyzed. The circuit demultiplexes the input clock signal into six phased output signals by streaming sets of twelve clock phases. A phase difference equal to the half period of the clock is maintained between consecutive output transitions. The VHDL description of the PDMUX6 cell is given and the simulation and synthesis results ar... View full abstract»

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  • Study of super cut-off CMOS technique in presence of the gate leakage current

    Publication Year: 2004 , Page(s): 24 - 27
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (180 KB) |  | HTML iconHTML  

    Super cut-off method as a well-known technique to reduce leakage power is investigated for its operational characteristics in the sub 100 nm technology nodes. Specially, the effect of the gate leakage in power consumption is considered and a design routine for optimizing the circuit in this regard is proposed. A right design methodology can improve the power and the circuit performance efficiently... View full abstract»

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  • Novel technique for mechanical stresses determination in thin films

    Publication Year: 2004 , Page(s): 692 - 695
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (258 KB) |  | HTML iconHTML  

    A novel technique for mechanical stresses determination in thin films has been proposed and tested for thin metal films on refractory metals basis. The new method provides the possibility of mechanical stresses distribution determination along of the films thickness. Experimental results concern films of Mo and alloys of Mo-Re deposited with a magnetron sputtering. Films material and sputtering co... View full abstract»

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  • High efficiency class-E switched mode power amplifier design and optimization with random search algorithm

    Publication Year: 2004 , Page(s): 283 - 286
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (201 KB) |  | HTML iconHTML  

    The class E switched mode power amplifier consists of a load network and a single transistor that is operated as a switch at the carrier frequency of the output signal. Main three parts of the power amplifier that specify its total efficiency are: the Q factor of output band-pass filter, the transistor on-state resistance, and the driver stage. In this paper, we design and optimize three common st... View full abstract»

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  • The influence of the stacked and double material gate structures on the short channel effects in SOI MOSFETs

    Publication Year: 2004 , Page(s): 68 - 71
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (170 KB) |  | HTML iconHTML  

    An asymmetric dual metal stack gate (DMSG) SOI MOSFET transistor has been investigated for its enhanced electrical characteristics. A 2-D physical model has been proposed and its results have been confirmed by those obtained by simulation. These results predict better short channel effects such as drain induced barrier lowering (DIBL) characteristics and hot carrier effects for this device compare... View full abstract»

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  • An improved heuristic for optimizing SI memory cells application: a fully optimized SI class AB grounded gate cell

    Publication Year: 2004 , Page(s): 180 - 183
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (208 KB) |  | HTML iconHTML  

    Optimally designing switched current (SI) memory cells is a very tedious process. In addition, it is usually limited to the design of ideal cells. Thus, in this paper, we deal with fully optimizing these cells and particularly real cells. Since SI class AB grounded gate memory cells are well known to be improved cells, we applied the proposed heuristic to design these cells. Also, besides maximizi... View full abstract»

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  • High speed implementation of Serpent algorithm

    Publication Year: 2004 , Page(s): 718 - 721
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (199 KB) |  | HTML iconHTML  

    In this paper, we report our implementation of Serpent algorithm on Virtex XCV1000 FPGA using partial evaluation technique. Partial reconfiguration is used in this implementation. The major effect of using partial reconfiguration is higher performance and reduced required area compared with other implementations. The design is pipelined in inner-outer of each round of the cipher and the results sh... View full abstract»

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  • A real time video smoothing implementation inside an FPGA-based system

    Publication Year: 2004 , Page(s): 152 - 156
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (287 KB) |  | HTML iconHTML  

    In this paper, an architecture dedicated to real-time video smoothing using the RC1000P-P Virtex prototyping board is presented. In comparison with smoothing video techniques like deblocking filters in H.264 or smoothing in JPEG2000, the proposed method is implemented in hardware and its computational cost and complexity are reduced where all pixel processing related to uncompressed video is done ... View full abstract»

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  • On-chip testing of embedded silicon transducers

    Publication Year: 2004 , Page(s): 2 - 7
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (438 KB) |  | HTML iconHTML  

    System-on-chip (SoC) technologies are evolving towards the integration of highly heterogeneous devices, including hardware of a different nature, such as digital, analog and mixed-signal, together with software components. Embedding transducers, as predicted by technology roadmaps, is yet another step in this continuous search for higher levels of integration and miniaturisation. Embedded transduc... View full abstract»

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