IEEE International Symposium on Performance Analysis of Systems and Software, 2005. ISPASS 2005.

20-22 March 2005

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  • ISPASS 2005 IEEE International Symposium on Performance Analysis of Systems and Software

    Publication Year: 2005, Page(s): 0_1
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  • Copyright page

    Publication Year: 2005, Page(s): i
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  • General Chairs' message

    Publication Year: 2005, Page(s):ii - iii
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  • Message from the Program Chair

    Publication Year: 2005, Page(s): iv
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  • ISPASS 2005 people

    Publication Year: 2005, Page(s): v
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  • Reviewers

    Publication Year: 2005, Page(s): vi
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  • Table of contents

    Publication Year: 2005, Page(s):vii - ix
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  • Keynote Talk #1- EEMBC and the Purposes of Embedded Processor Benchmarking

    Publication Year: 2005, Page(s): 1
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1629 KB)

    Summary form only given. Embedded processor benchmarking serves many purposes, from providing a framework to guide architectural choices in the development stage to giving original equipment manufacturers an objective means of predicting processor performance in specific application scenarios. Creating embedded processor benchmarks is a comparatively simple task. More difficult is winning acceptan... View full abstract»

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  • BioBench: A Benchmark Suite of Bioinformatics Applications

    Publication Year: 2005, Page(s):2 - 9
    Cited by:  Papers (62)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1729 KB) | HTML iconHTML

    Recent advances in bioinformatics and the significant increase in computational power available to researchers have made it possible to make better use of the vast amounts of genetic data that has been collected over the last two decades. As the uses of genetic data expand to include drug discovery and development of gene-based therapies, bioinformatics is destined to take its place in the forefro... View full abstract»

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  • Measuring Program Similarity: Experiments with SPEC CPU Benchmark Suites

    Publication Year: 2005, Page(s):10 - 20
    Cited by:  Papers (54)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2175 KB) | HTML iconHTML

    It is essential that a subset of benchmark programs used to evaluate an architectural enhancement, is well distributed within the target workload space rather than clustered in specific areas. Past efforts for identifying subsets have primarily relied on using microarchitecture-dependent metrics of program performance, such as cycles per instruction and cache miss-rate. The shortcoming of this tec... View full abstract»

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  • Simulation Differences Between Academia and Industry: A Branch Prediction Case Study

    Publication Year: 2005, Page(s):21 - 31
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1965 KB) | HTML iconHTML

    Computer architecture research in academia and industry is heavily reliant on simulation studies. While microprocessor companies have the resources to develop highly detailed simulation infrastructures that they correlate against their own silicon, academic researchers tend to use free, widely available simulators. The differences in instruction set architectures, operating systems, simulator mode... View full abstract»

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  • PowerFITS: Reduce Dynamic and Static I-Cache Power Using Application Specific Instruction Set Synthesis

    Publication Year: 2005, Page(s):32 - 41
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2131 KB) | HTML iconHTML

    Power consumption, performance, area, and cost are critical concerns in designing microprocessors for embedded systems such as portable handheld computing and personal telecommunication devices. In previous work [A. Cheng et al., (2004)], we introduced the concept of framework-based instruction-set tuning synthesis (FITS), which is a new instruction synthesis paradigm that falls between a general-... View full abstract»

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  • A High Performance, Energy Efficient GALS ProcessorMicroarchitecture with Reduced Implementation Complexity

    Publication Year: 2005, Page(s):42 - 53
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2078 KB) | HTML iconHTML

    As the costs and challenges of global clock distribution grow with each new microprocessor generation, a globally asynchronous, locally synchronous (GALS) approach becomes an attractive alternative. One proposed GALS approach, called a multiple clock domain (MCD) processor, achieves impressive energy savings for a relatively low performance cost. However, the approach requires separating the proce... View full abstract»

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  • Studying Thermal Management for Graphics-Processor Architectures

    Publication Year: 2005, Page(s):54 - 65
    Cited by:  Papers (18)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2195 KB) | HTML iconHTML

    We have previously presented Qsilver, a flexible simulation system for graphics architectures. In this paper we describe our extensions to this system, which we use - instrumented with a power model and HotSpot - to analyze the application of standard CPU static and runtime thermal management techniques on the GPU. We describe experiments implementing clock gating, fetch gating, dynamic voltage sc... View full abstract»

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  • Accelerating Multiprocessor Simulation with a Memory Timestamp Record

    Publication Year: 2005, Page(s):66 - 77
    Cited by:  Papers (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2081 KB) | HTML iconHTML

    We introduce a fast and accurate technique for initializing the directory and cache state of a multiprocessor system based on a novel software structure called the memory timestamp record (MTR). The MTR is a versatile, compressed snapshot of memory reference patterns which can be rapidly updated during fast-forwarded simulation, or stored as part of a checkpoint. We evaluate MTR using a full-syste... View full abstract»

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  • Intrinsic Checkpointing: A Methodology for Decreasing Simulation Time Through Binary Modification

    Publication Year: 2005, Page(s):78 - 88
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2050 KB) | HTML iconHTML

    With the proliferation of benchmarks available today, benchmarking new designs can significantly impact overall development time. In order to fully test and represent a typical workload, a large number of benchmarks must be run, and while current techniques such as SimPoint and SMARTS have had considerable success reducing simulation time, there are still areas of improvement. This paper details a... View full abstract»

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  • Enhancing Multiprocessor Architecture Simulation Speed Using Matched-Pair Comparison

    Publication Year: 2005, Page(s):89 - 99
    Cited by:  Papers (23)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2268 KB) | HTML iconHTML

    While cycle-level, full-system architecture simulation tools are capable of estimating performance at arbitrary accuracy, the time to simulate an entire application is usually prohibitive. Moreover, simulating multi-threaded applications further exacerbates this problem as most simulation tools are single-threaded. Recently, statistical sampling techniques, such as SMARTS, have managed to bring do... View full abstract»

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  • Panel Discussion

    Publication Year: 2005, Page(s): 100
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  • Keynote Talk #2

    Publication Year: 2005, Page(s): 101
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1906 KB)

    Summary form is only given. Hamming said, "The purpose of computing is insight, not numbers," yet this conference, like many today, is awash only in numbers. These numbers are perhaps more strategic than insightful. The numbers are used by designers, who want to prove their invention is better than the status quo. Then there are marketers, who want to prove their product's the one to buy over the ... View full abstract»

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  • Performance Characterization of Java Applications on SMT Processors

    Publication Year: 2005, Page(s):102 - 111
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2630 KB) | HTML iconHTML

    As Java is emerging as one of the major programming languages in software development, studying how Java applications behave on recent SMT processors is of great interest. This paper characterizes the performance of Java applications on an Intel Pentium 4 hyper-threading processor. Using the performance counters provided by Pentium 4, we quantitatively evaluate micro-architecture metrics while run... View full abstract»

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  • Partitioning Multi-Threaded Processors with a Large Number of Threads

    Publication Year: 2005, Page(s):112 - 123
    Cited by:  Papers (12)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2476 KB) | HTML iconHTML

    Today's general-purpose processors are increasingly using multithreading in order to better leverage the additional on-chip real estate available with each technology generation. Simultaneous multi-threading (SMT) was originally proposed as a large dynamic superscalar processor with monolithic hardware structures shared among all threads. Inters hyper-threaded Pentium 4 processor partitions the qu... View full abstract»

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  • Power-Performance Implications of Thread-level Parallelism on Chip Multiprocessors

    Publication Year: 2005, Page(s):124 - 134
    Cited by:  Papers (16)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2135 KB) | HTML iconHTML

    We discuss power-performance implications of running parallel applications on chip multiprocessors (CMPs). First, we develop an analytical model that, for the first time, puts together parallel efficiency, granularity, and voltage/frequency scaling, to quantify the performance and power consumption, delivered by a CMP running a parallel code. Then, we conduct detailed simulations of parallel appli... View full abstract»

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  • Motivation for Variable Length Intervals and Hierarchical Phase Behavior

    Publication Year: 2005, Page(s):135 - 146
    Cited by:  Papers (22)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3514 KB) | HTML iconHTML

    Most programs are repetitive, where similar behavior can be seen at different execution times. Proposed algorithms automatically group similar portions of a program's execution into phases, where the intervals in each phase have homogeneous behavior and similar resource requirements. These prior techniques focus on fixed length intervals (such as a hundred million instructions) to find phase behav... View full abstract»

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  • Fast, Accurate Microarchitecture Simulation Using Statistical Phase Detection

    Publication Year: 2005, Page(s):147 - 156
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2241 KB) | HTML iconHTML

    Simulation-based microarchitecture research is often hindered by the slow speed of simulators. In this work, we propose a novel statistical technique to identify highly representative unique behaviors or phases in a benchmark based on its IPC (instructions committed per cycle) trace. By simulating the timing of only the unique phases, the cycle-accurate simulation time for the SPEC suite is reduce... View full abstract»

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  • A Trace-Driven Simulator For Palm OS Devices

    Publication Year: 2005, Page(s):157 - 166
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3351 KB) | HTML iconHTML

    Due to the high cost of producing hardware prototypes, software simulators are typically used to determine the performance of proposed systems. To accurately represent a system with a simulator, the simulator inputs need to be representative of actual system usage. Trace-driven simulators that use logs of actual usage are generally preferred by researchers and developers to other types of simulato... View full abstract»

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