By Topic

22-25 May 2005

Filter Results

Displaying Results 1 - 25 of 45
  • Proceedings. European Test Symposium. ETS 2005

    Publication Year: 2005
    Request permission for commercial reuse | PDF file iconPDF (329 KB)
    Freely Available from IEEE
  • European Test Symposim 2005 - Title Page

    Publication Year: 2005, Page(s):i - iii
    Request permission for commercial reuse | PDF file iconPDF (32 KB)
    Freely Available from IEEE
  • European Test Symposim 2005 - Copyright Page

    Publication Year: 2005, Page(s): iv
    Request permission for commercial reuse | PDF file iconPDF (46 KB)
    Freely Available from IEEE
  • European Test Symposim 2005 - Table of Contents

    Publication Year: 2005, Page(s):v - vii
    Request permission for commercial reuse | PDF file iconPDF (38 KB)
    Freely Available from IEEE
  • Foreword

    Publication Year: 2005, Page(s): viii
    Request permission for commercial reuse | PDF file iconPDF (16 KB) | HTML iconHTML
    Freely Available from IEEE
  • Organizing Committee

    Publication Year: 2005, Page(s):ix - x
    Request permission for commercial reuse | PDF file iconPDF (1258 KB)
    Freely Available from IEEE
  • Steering Committee

    Publication Year: 2005, Page(s): xi
    Request permission for commercial reuse | PDF file iconPDF (17 KB)
    Freely Available from IEEE
  • Program Committee

    Publication Year: 2005, Page(s): xi
    Request permission for commercial reuse | PDF file iconPDF (17 KB)
    Freely Available from IEEE
  • Test Technology Technical Council

    Publication Year: 2005, Page(s):xiii - xv
    Request permission for commercial reuse | PDF file iconPDF (62 KB)
    Freely Available from IEEE
  • Energy minimization for hybrid BIST in a system-on-chip test environment

    Publication Year: 2005, Page(s):2 - 7
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (239 KB) | HTML iconHTML

    This paper addresses the energy minimization problem for system-on-chip testing. We assume a hybrid BIST test architecture where a combination of deterministic and pseudorandom test sequences is used. The objective of our proposed technique is to find the best ratio of these sequences so that the total energy is minimized and the memory requirements for the deterministic test set are met without s... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Test scheduling for modular SOCs in an abort-on-fail environment

    Publication Year: 2005, Page(s):8 - 13
    Cited by:  Papers (27)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (208 KB) | HTML iconHTML

    Complex SOCs are increasingly tested in a modular fashion, which enables us to record the yield-per-module. In this paper, we consider the yield-per-module as the pass probability of the module's manufacturing test. We use it to exploit the abort-on-fail feature of ATEs, in order to reduce the expected test application time. We present a model for expected test application time, which obtains incr... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A new SoC test architecture with RF/wireless connectivity

    Publication Year: 2005, Page(s):14 - 19
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (184 KB) | HTML iconHTML

    When moving into the billion-transistor era, the direct or bus interconnects in conventional SoC test control models are rather restricted in not only system performance, but also signal integrity and transmission with continued scaling of the feature size. Recent advances in silicon integrated circuit technology are making possible tiny low-cost transceivers to be integrated on chip. In this pape... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A unified fault model and test generation procedure for interconnect opens and bridges

    Publication Year: 2005, Page(s):22 - 27
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (120 KB) | HTML iconHTML

    A unified gate-level fault model for interconnect opens and bridges is proposed. Defects are modeled as constrained multiple line stuck-at faults. A novel feature of the proposed fault model is its flexibility to accommodate increasing levels of accuracy. Additionally the model does not require accurate device level circuit models to achieve desired accuracy. Efficient methods for fault simulation... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Defective behaviours of resistive opens in interconnect lines

    Publication Year: 2005, Page(s):28 - 33
    Cited by:  Papers (23)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (152 KB) | HTML iconHTML

    Defective interconnect lines affected by open defects have been intentionally designed and introduced on a CMOS digital test circuit. A simple bus structure with a scan register followed by a hold register and two buffers is used to investigate the influence of the crosstalk capacitances of the adjacent lines to the open defect. The strength of the open defect has been varied within a realistic ra... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Testing of resistive opens in CMOS latches and flip-flops

    Publication Year: 2005, Page(s):34 - 40
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (256 KB) | HTML iconHTML

    Open defects in CMOS memory elements are investigated. The analysis has been carried-out in a class of symmetrical CMOS flip-flop. Main focus is given to high resistive opens in gates. These defects depend on initial conditions prior to the application of the test vectors. Test conditions influencing the detectability of opens in scan path chains are also analyzed. Some sequences of 1's and 0's ma... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Using dummy bridging faults to define a reduced set of target faults

    Publication Year: 2005, Page(s):42 - 47
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (92 KB) | HTML iconHTML

    The large numbers of bridging faults in a circuit resulted in several approaches to the selection of a subset of faults as targets for test generation. These approaches do not guarantee that all the bridging faults (or even that all the bridging faults that are likely to occur) will be detected. We investigate a different approach to the selection of target bridging faults. The approach is based o... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Acceleration of transition test generation for acyclic sequential circuits utilizing constrained combinational stuck-at test generation

    Publication Year: 2005, Page(s):48 - 53
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (144 KB) | HTML iconHTML

    This paper presents a transition test generation method for acyclic sequential circuits. In this method, to generate test sequences for transition faults in a given acyclic sequential circuit, constrained combinational stuck-at test generation is performed on its double time-expansion model that is composed of two copies of a time-expansion model of the given circuit. This method is complete, i.e.... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Path-oriented transition fault test generation considering operating conditions

    Publication Year: 2005, Page(s):54 - 59
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (112 KB) | HTML iconHTML

    We describe a test generation procedure for path-oriented transition faults that takes into account the fact that operating conditions may change during circuit operation. A path-oriented transition fault is detected through the longest sensitizable path that goes through the fault site. The operating conditions we consider are junction temperature and power supply voltage. Since path delays chang... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Evaluation of signature-based testing of RF/analog circuits

    Publication Year: 2005, Page(s):62 - 67
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (288 KB) | HTML iconHTML

    Due to its low cost, low test time and reduced test complexity, structural testing is preferred to functional whenever possible. The study presented in this paper indicates that the two low-frequency structural test methods considered, power supply current monitoring and the power supply ramping technique, provide a valuable supplement/alternative when one of the functional tests (gain, noise figu... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Accurate measurement of multi-tone power ratio (MTPR) of ADSL devices using low cost testers

    Publication Year: 2005, Page(s):68 - 73
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (200 KB) | HTML iconHTML

    Measurement of multi-tone power ratio (MTPR) on the transmitter output of a central office ADSL analog front-end device (AFE) poses stringent requirements on the linearity of the ATE digitizer. Cost of the ATE digitizer that can perform this test in a specification compliant manner is prohibitively high. In this paper, a test technique to perform TX MTPR test on a central office ADSL device using ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Towards on-line testing of MEMS using electro-thermal excitation

    Publication Year: 2005, Page(s):76 - 81
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (608 KB) | HTML iconHTML

    This paper presents an electro-thermal on-line testing procedure applied to a MEMS magnetometer. The basic idea consists in: (i) using electro-thermal excitation to superimpose thermal variations to the normal operating mode; and (ii) processing the sensor output to extract the thermally-induced signal. In this work, we investigate the possibility of using a modulation of the excitation signal to ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Evaluation of impulse response-based BIST techniques for MEMS in the presence of weak nonlinearities

    Publication Year: 2005, Page(s):82 - 87
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (128 KB) | HTML iconHTML

    Microsystems are usually affected by multiple failure sources. A faulty behavior caused by different types of defects and failure sources can exhibit small functional errors that are difficult to detect using structural testing. From here stems the necessity to apply specification-based functional testing on the basis of a method that carries enough information about the physical behavior of the d... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Bias Superposition - An On-Line Test Strategy for a MEMS Based Conductivity Sensor

    Publication Year: 2005, Page(s):88 - 93
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (177 KB) | HTML iconHTML

    A novel on-line monitoring technique for a range of MEMS and integrated sensor systems is presented based on the injection of a test stimuli into the bias structure of transducer functions. The technique "Bias Superposition" utilises both signal injection and signal extraction techniques to achieve an indication of structural integrity of the transducer and interface. The technique has been succes... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • DOT: new deterministic defect-oriented ATPG tool

    Publication Year: 2005, Page(s):96 - 101
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (272 KB) | HTML iconHTML

    A method is proposed for combinational deterministic test pattern generation using a uniform functional fault model for combinational circuits. This includes an approach, which allows to find the types of faults that may occur in a real circuit and to determine their probabilities. Additionally, a defect-oriented deterministic test generation tool was developed (DOT), and the experimental data obt... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Logic circuit testing for transient faults

    Publication Year: 2005, Page(s):102 - 107
    Cited by:  Papers (10)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (200 KB) | HTML iconHTML

    Transient faults are becoming an increasingly serious concern for logic circuits. They can be caused by thermal neutrons, present at all altitudes, and by other types of ionizing radiation, especially in aerospace applications and nuclear engineering. In this paper we examine issues related to detection of transient errors. The difficulty in testing for transient errors is that they are not always... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.