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Date 22-25 May 2005

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Displaying Results 1 - 25 of 45
  • Proceedings. European Test Symposium. ETS 2005

    Publication Year: 2005
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  • European Test Symposim 2005 - Title Page

    Publication Year: 2005 , Page(s): i - iii
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  • European Test Symposim 2005 - Copyright Page

    Publication Year: 2005 , Page(s): iv
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  • European Test Symposim 2005 - Table of Contents

    Publication Year: 2005 , Page(s): v - vii
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  • Foreword

    Publication Year: 2005 , Page(s): viii
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  • Organizing Committee

    Publication Year: 2005 , Page(s): ix - x
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  • Steering Committee

    Publication Year: 2005 , Page(s): xi
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  • Program Committee

    Publication Year: 2005 , Page(s): xi
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  • Test Technology Technical Council

    Publication Year: 2005 , Page(s): xiii - xv
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  • Energy minimization for hybrid BIST in a system-on-chip test environment

    Publication Year: 2005 , Page(s): 2 - 7
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (248 KB) |  | HTML iconHTML  

    This paper addresses the energy minimization problem for system-on-chip testing. We assume a hybrid BIST test architecture where a combination of deterministic and pseudorandom test sequences is used. The objective of our proposed technique is to find the best ratio of these sequences so that the total energy is minimized and the memory requirements for the deterministic test set are met without sacrificing test quality. We propose two different heuristic algorithms and a fast estimation method that enables considerable reduction of the computation time. Experimental results have shown the efficiency of the approach for finding reduced energy solutions with low computational overhead. View full abstract»

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  • Test scheduling for modular SOCs in an abort-on-fail environment

    Publication Year: 2005 , Page(s): 8 - 13
    Cited by:  Papers (22)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (208 KB) |  | HTML iconHTML  

    Complex SOCs are increasingly tested in a modular fashion, which enables us to record the yield-per-module. In this paper, we consider the yield-per-module as the pass probability of the module's manufacturing test. We use it to exploit the abort-on-fail feature of ATEs, in order to reduce the expected test application time. We present a model for expected test application time, which obtains increasing accuracy due to decreasing granularity of the abortable test unit. For a given SOC, with a modular test architecture consisting of wrappers and disjunct TAMs, and for given pass probabilities per module test, we schedule the tests on each TAM such that the expected test application time is minimized. We describe two heuristic scheduling approaches, one without and one with preemption. Experimental results for the ITC'02 SOC test benchmarks demonstrate the effectiveness of our approach, as we achieve up to 97% reduction of the expected test application time, without any modification of the SOC or ATE. View full abstract»

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  • A new SoC test architecture with RF/wireless connectivity

    Publication Year: 2005 , Page(s): 14 - 19
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (184 KB) |  | HTML iconHTML  

    When moving into the billion-transistor era, the direct or bus interconnects in conventional SoC test control models are rather restricted in not only system performance, but also signal integrity and transmission with continued scaling of the feature size. Recent advances in silicon integrated circuit technology are making possible tiny low-cost transceivers to be integrated on chip. In this paper, we propose a new distributed multihop wireless test control network based on the recent development in "radio-on-chip" technology. Under the multilevel tree structure, the system optimization is performed on control constrained resource partitioning and distribution. Several challenging system design issues, such as RF nodes placement, clustering, and routing are studied, with the integrated resource distribution and system optimization on TAM design and test scheduling. Experimental results show that the proposed algorithm can efficiently minimize the overall testing cost. View full abstract»

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  • A unified fault model and test generation procedure for interconnect opens and bridges

    Publication Year: 2005 , Page(s): 22 - 27
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (120 KB) |  | HTML iconHTML  

    A unified gate-level fault model for interconnect opens and bridges is proposed. Defects are modeled as constrained multiple line stuck-at faults. A novel feature of the proposed fault model is its flexibility to accommodate increasing levels of accuracy. Additionally the model does not require accurate device level circuit models to achieve desired accuracy. Efficient methods for fault simulation and test generation are discussed and experimental results on benchmark circuits and industrial designs are presented. The experimental results presented show that the tests generated using simpler versions of the proposed fault model achieve higher defect coverage than the tests using two currently popular methods to derive high defect coverage tests. View full abstract»

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  • Defective behaviours of resistive opens in interconnect lines

    Publication Year: 2005 , Page(s): 28 - 33
    Cited by:  Papers (17)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (152 KB) |  | HTML iconHTML  

    Defective interconnect lines affected by open defects have been intentionally designed and introduced on a CMOS digital test circuit. A simple bus structure with a scan register followed by a hold register and two buffers is used to investigate the influence of the crosstalk capacitances of the adjacent lines to the open defect. The strength of the open defect has been varied within a realistic range of resistances going from a full (complete) open up to a weak (low-resistive) open. The static and dynamic behavior of the defective lines have been electrically characterized taking into account the location of the defect as well as its resistive value. This characterization allows the extraction of general information useful for the prediction and detection of the faulty behavior caused by the defect. Testability conditions of this defect in interconnect lines are discussed. View full abstract»

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  • Testing of resistive opens in CMOS latches and flip-flops

    Publication Year: 2005 , Page(s): 34 - 40
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (256 KB) |  | HTML iconHTML  

    Open defects in CMOS memory elements are investigated. The analysis has been carried-out in a class of symmetrical CMOS flip-flop. Main focus is given to high resistive opens in gates. These defects depend on initial conditions prior to the application of the test vectors. Test conditions influencing the detectability of opens in scan path chains are also analyzed. Some sequences of 1's and 0's may fail for detecting opens in gates. Conditions for the input sequences for scan path chains are stated. The dependence of the detectability of opens on the duty cycle is also investigated. Experimental results showing the dependence of the behavior of open gates with the initial conditions are shown. View full abstract»

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  • Using dummy bridging faults to define a reduced set of target faults

    Publication Year: 2005 , Page(s): 42 - 47
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (92 KB) |  | HTML iconHTML  

    The large numbers of bridging faults in a circuit resulted in several approaches to the selection of a subset of faults as targets for test generation. These approaches do not guarantee that all the bridging faults (or even that all the bridging faults that are likely to occur) will be detected. We investigate a different approach to the selection of target bridging faults. The approach is based on the introduction of dummy bridging faults, which are not physical faults but whose tests detect large numbers of physical faults. We apply this approach to four-way bridging faults. When no approximations are made, the proposed approach selects a subset of faults such that if they are detected, all the four-way bridging faults are guaranteed to be detected. We also investigate approximations and a test generation approach for the selected faults. View full abstract»

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  • Acceleration of transition test generation for acyclic sequential circuits utilizing constrained combinational stuck-at test generation

    Publication Year: 2005 , Page(s): 48 - 53
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (144 KB) |  | HTML iconHTML  

    This paper presents a transition test generation method for acyclic sequential circuits. In this method, to generate test sequences for transition faults in a given acyclic sequential circuit, constrained combinational stuck-at test generation is performed on its double time-expansion model that is composed of two copies of a time-expansion model of the given circuit. This method is complete, i.e., this method can generate test sequences for all the testable transition faults and can identify all the untestable transition faults in a given acyclic sequential circuit. Experimental results show that our method can achieve higher fault efficiency with drastically shorter test generation time than that achieved by a conventional method. View full abstract»

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  • Path-oriented transition fault test generation considering operating conditions

    Publication Year: 2005 , Page(s): 54 - 59
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (112 KB) |  | HTML iconHTML  

    We describe a test generation procedure for path-oriented transition faults that takes into account the fact that operating conditions may change during circuit operation. A path-oriented transition fault is detected through the longest sensitizable path that goes through the fault site. The operating conditions we consider are junction temperature and power supply voltage. Since path delays change with operating conditions, the longest path through a fault site may be different under different conditions. We show that test generation using nominal delays is not sufficient for covering the complete range of operating conditions, even if N-detection test generation is used. Therefore, operating conditions need to be addressed explicitly during test generation. However, since temperature and voltage are continuous variables and represent an infinite number of values in the range, test generation must concentrate on a small selected set of operating conditions. We discuss the selection of these conditions and demonstrate that N-detection test generation with multiple operating conditions is effective in covering the range of operation conditions almost completely. View full abstract»

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  • Evaluation of signature-based testing of RF/analog circuits

    Publication Year: 2005 , Page(s): 62 - 67
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (288 KB) |  | HTML iconHTML  

    Due to its low cost, low test time and reduced test complexity, structural testing is preferred to functional whenever possible. The study presented in this paper indicates that the two low-frequency structural test methods considered, power supply current monitoring and the power supply ramping technique, provide a valuable supplement/alternative when one of the functional tests (gain, noise figure and total harmonic distortion) in the test set can be complemented or substituted by structural test and add to or maintain no loss of fault coverage. View full abstract»

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  • Accurate measurement of multi-tone power ratio (MTPR) of ADSL devices using low cost testers

    Publication Year: 2005 , Page(s): 68 - 73
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (200 KB) |  | HTML iconHTML  

    Measurement of multi-tone power ratio (MTPR) on the transmitter output of a central office ADSL analog front-end device (AFE) poses stringent requirements on the linearity of the ATE digitizer. Cost of the ATE digitizer that can perform this test in a specification compliant manner is prohibitively high. In this paper, a test technique to perform TX MTPR test on a central office ADSL device using low-cost automatic test equipment (ATE) is proposed. The proposed technique is based on adding optimum dither noise to the output of the DUT, to improve the performance of the low cost ATE digitizer. The dither reduces the distortion caused by the static errors in the ATE digitizer by randomizing these nonlinear errors. Results obtained using the proposed method on ASDL AFE devices show an improvement of ∼7dB in MTPR measurement with very good repeatability. View full abstract»

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  • Towards on-line testing of MEMS using electro-thermal excitation

    Publication Year: 2005 , Page(s): 76 - 81
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (608 KB) |  | HTML iconHTML  

    This paper presents an electro-thermal on-line testing procedure applied to a MEMS magnetometer. The basic idea consists in: (i) using electro-thermal excitation to superimpose thermal variations to the normal operating mode; and (ii) processing the sensor output to extract the thermally-induced signal. In this work, we investigate the possibility of using a modulation of the excitation signal to produce a low-frequency thermally-based signal at the output of the Wheatstone bridge. Investigations using high-level simulations are conducted to determine appropriate test stimulus and suitable system architecture. View full abstract»

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  • Evaluation of impulse response-based BIST techniques for MEMS in the presence of weak nonlinearities

    Publication Year: 2005 , Page(s): 82 - 87
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (128 KB) |  | HTML iconHTML  

    Microsystems are usually affected by multiple failure sources. A faulty behavior caused by different types of defects and failure sources can exhibit small functional errors that are difficult to detect using structural testing. From here stems the necessity to apply specification-based functional testing on the basis of a method that carries enough information about the physical behavior of the device under test (DUT). Such a method can be attained by the impulse response (IR) measurement of the linear DUT. In this paper we explain three existing techniques to measure the IR of linear time-invariant (LTI) devices. Weak nonlinearities that can be caused by system nonidealities and measurement distortions are considered. Only simple techniques that do not require the presence of a digital signal processor (DSP) on-chip are considered. A detailed comparison between these techniques is carried out to demonstrate our choice for a BIST (built-in self-test) approach. View full abstract»

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  • Bias Superposition - An On-Line Test Strategy for a MEMS Based Conductivity Sensor

    Publication Year: 2005 , Page(s): 88 - 93
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (177 KB) |  | HTML iconHTML  

    A novel on-line monitoring technique for a range of MEMS and integrated sensor systems is presented based on the injection of a test stimuli into the bias structure of transducer functions. The technique "Bias Superposition" utilises both signal injection and signal extraction techniques to achieve an indication of structural integrity of the transducer and interface. The technique has been successfully applied to a thick film conductance sensor. View full abstract»

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  • DOT: new deterministic defect-oriented ATPG tool

    Publication Year: 2005 , Page(s): 96 - 101
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (272 KB) |  | HTML iconHTML  

    A method is proposed for combinational deterministic test pattern generation using a uniform functional fault model for combinational circuits. This includes an approach, which allows to find the types of faults that may occur in a real circuit and to determine their probabilities. Additionally, a defect-oriented deterministic test generation tool was developed (DOT), and the experimental data obtained by the tool for ISCAS'85 benchmarks are presented. It was shown that 100% stuck-at fault tests covered only about 80-90% physical defects. The main feature of the new tool is its ability to reach 100% defect efficiency for the given set of defects by proving the redundancy of not detected defects. An interesting conclusion of the experiments is also that up to 25% of the defects cannot be covered by any voltage test approaches. View full abstract»

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  • Logic circuit testing for transient faults

    Publication Year: 2005 , Page(s): 102 - 107
    Cited by:  Papers (7)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (200 KB) |  | HTML iconHTML  

    Transient faults are becoming an increasingly serious concern for logic circuits. They can be caused by thermal neutrons, present at all altitudes, and by other types of ionizing radiation, especially in aerospace applications and nuclear engineering. In this paper we examine issues related to detection of transient errors. The difficulty in testing for transient errors is that they are not always present. Test vectors need to be repeated a number of times in order to detect a fault. We show how to compute a measure for the detectability of transient faults with respect to specific test vectors. This is done using a matrix-based gate-fault model known as the probabilistic transfer matrix model. Using this detectability measure we derive methods to generate multisets of tests to verify probability distributions of faults and detect abnormalities in circuit behavior. Applications of this method include detection of increased atmospheric radiation in terms of its impact on circuits, and testing for process variation that increases the susceptibility of a circuit to transient errors. View full abstract»

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