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Proceedings. DELTA 2004. Second IEEE International Workshop on Electronic Design, Test and Applications

28-30 Jan. 2004

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Displaying Results 1 - 25 of 85
  • Message from the General Chair

    Publication Year: 2004, Page(s): xi
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    Freely Available from IEEE
  • Message from the Program Chairs

    Publication Year: 2004, Page(s): xii
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  • Committees

    Publication Year: 2004, Page(s): xiii
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  • Program Committee

    Publication Year: 2004, Page(s): xiv
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    Freely Available from IEEE
  • list-reviewer

    Publication Year: 2004, Page(s): xv
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  • Hybrid BIST optimization for core-based systems with test pattern broadcasting

    Publication Year: 2004, Page(s):3 - 8
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (143 KB) | HTML iconHTML

    This paper introduces a technique for hybrid BIST time optimization for testing core-based systems that use test pattern broadcasting for both pseudorandom and deterministic patterns. First we formulate the test time minimization problem for such an architecture. Thereafter we present algorithms for finding an efficient combination of pseudorandom and deterministic test sets under given memory con... View full abstract»

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  • Testability issues in superconductor electronics

    Publication Year: 2004, Page(s):9 - 14
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (298 KB) | HTML iconHTML

    An emerging technology for solutions in high-end applications in computing and telecommunication is superconductor electronics. A system-level study has been carried out to verify the feasibility of DfT in superconductor electronics. In this paper, we present how this can be realized to monitor so-called single-flux quantum pulses. As a part of our research, test structures have been developed to ... View full abstract»

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  • Frequency domain testing of general purpose processors at the instruction execution level

    Publication Year: 2004, Page(s):15 - 20
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (253 KB) | HTML iconHTML

    In this paper, we put forth a novel frequency domain BIST approach towards instruction execution level testing. This BIST scheme employs number theoretic transform to obtain the spectrum of the control sequences (generated by the processor control unit, the Finite State Machine) of the instructions during execution to detect stuck-at and transient faults and weak logic signals. The scheme involves... View full abstract»

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  • Spectral warping revisited

    Publication Year: 2004, Page(s):23 - 28
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (458 KB) | HTML iconHTML

    Spectral warping is a time domain to time domain transformation on a signal that effectively warps the frequency content of the original signal. Here we present a matrix formulation of the spectral warping transformation. The transform matrix is decomposed into three steps. The first is a DFT to convert the time signal into the frequency domain. Step two is an interpolation matrix to calculate the... View full abstract»

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  • A new method for eye extraction from facial image

    Publication Year: 2004, Page(s):29 - 34
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB) | HTML iconHTML

    In this paper we present a new approach to the problem of detecting the eyes from a still facial image. Features such as color, edges, intensity and shape are incorporated in different stages of our method. First, the face region is extracted from the image by skin-color filter and window growing. Second, eyes are approximately located by projection of gradient features in different directions. Th... View full abstract»

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  • A new read-out circuit for low power current and voltage mediated integrating CMOS imager

    Publication Year: 2004, Page(s):35 - 40
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (147 KB) | HTML iconHTML

    This paper proposes a new read-out strategy for integrating type of CMOS imagers. The approach uses a single counter and two address decoders for generating both the reset and the selection signals needed for an integrating image sensor array together with the electronic shutter functionality. In contrast to the traditional integrating readout approaches, our reset and read-out phases are carried ... View full abstract»

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  • Phase correlations in human EEG signal: a case study

    Publication Year: 2004, Page(s):41 - 43
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (142 KB) | HTML iconHTML

    This paper is concerned with the study of human electroencephalogram (EEC) signal of an epileptic person. In classical EEG analysis rhythms in different bands have often been assumed to be independent and their occurrence has been interpreted as a sign of different function operations. In this work, quadratic phase coupling has been studied by the use of higher order spectral analysis. The results... View full abstract»

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  • Testing and analysis of computer generated holograms for microphotonic devices

    Publication Year: 2004, Page(s):47 - 52
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (405 KB) | HTML iconHTML

    Opto-VLSI processors offer promising technological platform for implementing reconfigurable Wavelength Division Multiplexing (WDM) networks. By driving an Opto-VLSI processor with a computer generated hologram (CGH), dynamic optical beam steering and/or multicasting can be achieved. In this paper we develop and compare CGH algorithms based on simulated annealing and projection methods, for optimum... View full abstract»

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  • Pixel structure effects on crosstalk in backwall illuminated CMOS compatible photodiode arrays

    Publication Year: 2004, Page(s):53 - 58
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (226 KB) | HTML iconHTML

    CMOS imaging arrays in back-illuminated mode provide a means to realize photodiode arrays for high resolution imaging systems, provided crosstalk effects can be reduced to the level of those observed in front-illuminated arrays. In this study, we have simulated the crosstalk in back-illuminated and front-illuminated arrays as a function of different structural configurations, including the presenc... View full abstract»

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  • Dynamic MicroPhotonic WDM equalizer

    Publication Year: 2004, Page(s):59 - 62
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (307 KB) | HTML iconHTML

    An efficient wavelength division multiplexed (WDM) channel equalizer employing a dynamic MicroPhotonic processor is demonstrated. Using a proof-of-principle 6-channel equalizer setup, optimum phase holograms have been generated, which realise WDM equalisation with more than 25 dB dynamic range and less than 0.2 dB power ripples. View full abstract»

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  • MicroPhotonic reconfigurable RF signal processor

    Publication Year: 2004, Page(s):63 - 67
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (401 KB) | HTML iconHTML

    In this paper, we discuss the use of MicroPhotonic processors to control the optical power distribution in photonic signal processing structures, achieving adaptive photonic RF filtering with arbitrary transfer functions. A new MicroPhotonics-based photonic signal processing architecture is presented, in which fibre collimator arrays, Opto-VLSl processors, and a WDM combiner are integrated within ... View full abstract»

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  • Towards a modular communication system for FPGAs

    Publication Year: 2004, Page(s):71 - 76
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (234 KB) | HTML iconHTML

    This paper describes the prototype development of a flexible communication system. The emphasis is about software concerns, considering that FPGA technologies are the core of the project. It also shows how the components used were specified and chosen, after making an analysis of the available state-of-the-art technologies. The idea of creating a flexible and modular communication system motivated... View full abstract»

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  • Xilinx Virtex II Pro implementation of a reconfigurable UMTS digital channel filter

    Publication Year: 2004, Page(s):77 - 82
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (530 KB) | HTML iconHTML

    A reconfigurable digital root raised cosine (RRC) filter for a UMTS terrestrial radio access (UTRA) mobile terminal receiver is implemented on a Xilinx Vitrex II Pro Field Programmable Gate Array (FPGA). The filter employs a finite impulse response (FIR) and monitors in-band and out-of-band received signal powers and calculates the appropriate filter length that meets the bit-energy to interferenc... View full abstract»

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  • High quality TPG for delay faults in look-up tables of FPGAs

    Publication Year: 2004, Page(s):83 - 88
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (207 KB) | HTML iconHTML

    The objective of this paper is to improve delay fault testing of SRAM-Based FPGAs. We have analyzed the physical behavior of resistive opens in a Look-Up Table (LUT) in previous papers and we have shown that i) these ones can change the propagation delay of the LUT and ii) the delay due to them varies depending on their size and their location. In this paper, we first show that resistive shorts ar... View full abstract»

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  • FPGA implementation of an OFDM-WLAN synchronizer

    Publication Year: 2004, Page(s):89 - 94
    Cited by:  Papers (9)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (188 KB) | HTML iconHTML

    In this paper, we present a timing and frequency synchronization scheme and its FPGA implementation for IEEE 802.11a WLAN systems. In the scheme, an efficient double auto-correlation method based on short training symbols is used for timing synchronization. The performance of the proposed method is comparable or even superior to that of the conventional timing synchronization method under multipat... View full abstract»

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  • Towards analog and mixed-signal SOC design with systemC-AMS

    Publication Year: 2004, Page(s):97 - 102
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (134 KB) | HTML iconHTML

    Systems-on-Chip (SoCs) are heterogeneous by nature as they may integrate digital, analog, RF hardware as well as software components or non electrical parts such as sensors or actuators. The increasing level of complexity for designing SoCs in a reasonable amount of time and resources asks, among other capabilities, for powerful modeling and simulation means. SystemC is emerging as a de facto stan... View full abstract»

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  • CMOS ADC with reconfigurable properties for a cellular handset

    Publication Year: 2004, Page(s):103 - 107
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (290 KB) | HTML iconHTML

    A low power reconfigurable ADC architecture is described for a mobile terminal receiver. The architecture can automatically scale the resolution by monitoring in-band and out-of-band powers. The architecture performance was evaluated in a simulation UTRA-TDD environment. A power consumption analysis of the implemented architecture is also presented. The UTRA-TDD downlink mode was examined statisti... View full abstract»

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  • Time domain analogue to digital conversion in a digital pixel sensor array

    Publication Year: 2004, Page(s):108 - 112
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (538 KB) | HTML iconHTML

    This paper presents a digital pixel sensor array, in which the photodiode sensor, the analogue to digital conversion circuitry, and an 8-bit memory are combined in the 45 /spl mu/m/spl times/45 /spl mu/m pixel, yielding a 12% fill factor. The conversion is performed by measuring the time taken for the photodiode, operating in direct integration mode, to discharge from its reset voltage to a refere... View full abstract»

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  • Static scheduling of monoprocessor real-time systems composed of hard and soft tasks

    Publication Year: 2004, Page(s):115 - 120
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (250 KB) | HTML iconHTML

    In this paper we address the problem of static scheduling of real-time systems that include both hard and soft tasks. We consider that hard as well as soft tasks are periodic and that there exist data dependencies among tasks. In order to capture the relative importance of soft tasks and how the quality of results is affected when missing a soft deadline, we use utility functions associated to sof... View full abstract»

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  • The slack sharing server for embedded microcontrollers

    Publication Year: 2004, Page(s):121 - 125
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (172 KB) | HTML iconHTML

    An embedded real-time microcontroller usually has both hard and soft real-time tasks. The slack sharing server (SSS) allows soft real-time tasks to share the time slack left by hard real-time tasks. This paper evaluated the SSS and found that some tasks may be treated unfairly if the number of consecutive time slacks is not greater than the number of soft real-time tasks. An improved SSS was propo... View full abstract»

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