By Topic

System-on-Chip, 2004. Proceedings. 2004 International Symposium on

Date 16-18 Nov. 2004

Filter Results

Displaying Results 1 - 25 of 79
  • Clock generation and distribution in high-performance processors

    Publication Year: 2004
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (398 KB)

    This paper is an overview of clock generation and distribution techniques, with emphasis on high-performance microprocessor designs. We describe practical techniques to reduce clock skew and jitter, with examples from several industry leaders. As power consumption is a limiting factor for all modern designs, low-power clock distribution techniques and flip-flop implementations are reviewed. Severa... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • 3D graphics circuits for 3G multimedia terminals

    Publication Year: 2004
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (398 KB) | HTML iconHTML

    Summary form only given. The development of system-on-chip technology drives various multimedia and even 3D graphics capabilities into 3G multimedia terminals. The 3D applications are attractive to the mobile market, however, implementing them requires a huge amount of parallel calculations and memory bandwidth within the boundary of limited battery power. In this talk, we discuss 'how to' and 'wh... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design for verification of a PCI bus in SystemC

    Publication Year: 2004, Page(s):201 - 204
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (618 KB) | HTML iconHTML

    In this paper, we present an approach to design and verify SystemC intellectual properties (IPs). We considered as an illustrative case a PCI bus modeled as a monitor module that can be interfaced to existent SystemC IPs. We defined three design steps where we first model the bus in UML; then, design it completely with abstract state machines (ASM); and, finally, translate the ASM code to SystemC.... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Crosstalk immune interconnect driver design

    Publication Year: 2004, Page(s):139 - 142
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (575 KB) | HTML iconHTML

    The effect of crosstalk noise becomes increasingly significant as geometries continue to shrink into the deep sub-micrometer regime and clock-frequency increases into the multi GHz domain. Dynamic delay caused by coupling capacitance between adjacent interconnections is a critical problem, as it cannot accurately be estimated in static timing analysis. This work presents a new driver circuit schem... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Refinement of on-chip communication channels

    Publication Year: 2004, Page(s):197 - 200
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (651 KB) | HTML iconHTML

    We present a formal systematic approach to model and stepwise refine on-chip communication channels. The approach is based on the formal framework of action systems. We show how an abstract channel, modeled as a remote procedure, is first refined into an intermediate form and then further into a concrete implementable model based on boolean communication variables. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Topology design for global link optimization in application specific network-on-chips

    Publication Year: 2004, Page(s):135 - 138
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (585 KB) | HTML iconHTML

    A new algorithm for application-specific network-on-chip design and optimization is presented. The algorithm uses packet-scheduling and traffic modelling concepts to estimate the degree of interaction of several communication channels (congestion) on a given design. It is implemented as part of a network design software package that includes other optimization criteria, like power consumption and ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An in-circuit debug environment for multiprocessor SOCs based on a HDL RISC soft-core

    Publication Year: 2004, Page(s):193 - 196
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (658 KB) | HTML iconHTML

    A fundamental feature common to all SOC projects is the inclusion of one or more embedded microprocessors in the design space. As the complexity of algorithms mapped on embedded processors and their interaction with the surrounding SOC resources increase, the availability of reliable software verification means becomes a serious design issue, especially when more than one processor is included in ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A fully integrated low-IF DVB-T receiver architecture

    Publication Year: 2004, Page(s):189 - 192
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (577 KB) | HTML iconHTML

    We propose a fully integrated DVB-T receiver architecture for low cost CMOS implementation. The receiver uses a dual-IF architecture to cover the receive bands from 170 MHz to 862 MHz and a low-IF of 4.57 MHz. Key performance values meet the DVB-T requirements with competitive performance (sensitivity 72.5 dBm, noise figure 6.6 dB, adjacent channel protection ratio (ACPR)= -43 dB, available SNR=28... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design reuse and design for reuse, a case study on HDSL2

    Publication Year: 2004, Page(s):129 - 133
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (663 KB) | HTML iconHTML

    Design reuse offers time-to-market reduction through exploitation of previously created components and subsystems. Wide adoption of design reuse lays the foundation for the development of system-level design methodologies. The study described here focused on the design for reuse of an HDSL2 transceiver SoC and its components. The problems faced when trying to reuse old macro components are discuss... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A low-power I-cache design with tag-comparison reuse

    Publication Year: 2004, Page(s):61 - 67
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (849 KB) | HTML iconHTML

    This paper reports design and evaluation results of a low-energy I-cache architecture, called history-based tag-comparison (HBTC) cache. The HBTC cache attempts to re-use tag-comparison results to detect and eliminate unnecessary memory-array activations. We have performed cycle accurate simulations, and have designed an SRAM core based on a 0.18 μm CMOS technology. As a result, it has been obs... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Comparative analysis of serial vs parallel links in NoC

    Publication Year: 2004, Page(s):185 - 188
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (596 KB) | HTML iconHTML

    An analytical model is employed to characterize and compare serial and parallel communication techniques in NoC interconnects. Simulations that are based on 130 nm and 70 nm technology parameters reveal up to ×5.5 and ×17 reduction in power and area of serial vs. 32-bit multi-layer parallel links, respectively. Lower power is dissipated by a single-layer parallel link but it occupies a... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A synthesizable RTL design of asynchronous FIFO

    Publication Year: 2004, Page(s):123 - 128
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (655 KB) | HTML iconHTML

    An asynchronous FIFO which avoids data movement in a micropipeline FIFO is presented and it has been implemented as a gate-level netlist. The presented asynchronous FIFO model is constructed by commonly used hardware-description language and synthesized using the conventional EDA tools and methods for synchronous design. The purpose of this work is to construct a reusable asynchronous FIFO design ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A system-level multiprocessor system-on-chip modeling framework

    Publication Year: 2004, Page(s):81 - 84
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (618 KB) | HTML iconHTML

    We present a system-level modeling framework to model system-on-chips (SoC) consisting of heterogeneous multiprocessors and network-on-chip communication structures in order to enable the developers of today's SoC designs to take advantage of the flexibility and scalability of network-on-chip and rapidly explore high-level design alternatives to meet their system requirements. We present a modelin... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A low-noise fast-settling PLL frequency synthesizer for CDMA receivers

    Publication Year: 2004, Page(s):57 - 60
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (600 KB) | HTML iconHTML

    A 1.8-2 GHz fully integrated CMOS phase-locked-loop (PLL) frequency synthesizer for CDMA receivers is presented. The design focuses on the voltage controlled oscillator (VCO) and loop bandwidth adaptation technique, which determine the out-of-band phase noise and the speed of the PLL frequency synthesizer, respectively. A low power low phase noise bond wire VCO is proposed. The inductance compensa... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A thermal-aware power management soft-IP for platform-based SoC designs

    Publication Year: 2004, Page(s):181 - 184
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (631 KB) | HTML iconHTML

    A novel thermal-aware power management (TAPM) software intellectual property (soft-IP) for modem platform-based SoC designs is presented. This research proposes the system-level architecture of thermal-aware power management, which includes a power management bus (PMB), TAPM soft-IP and interface circuitry for the proposed PMB. Each component of the proposed design is encapsulated into a soft-IP. ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Reconfigurable IP blocks: a survey [SoC]

    Publication Year: 2004, Page(s):117 - 122
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (698 KB) | HTML iconHTML

    An extensive survey concentrating totally on reconfigurable IP blocks is given. The most remarkable prevailing implementations are categorized according to the computational granularity, communication topology and source of block, i.e. academic vs. commercial. Also our own research results in this field are included in the classification. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • SoC-Mobinet, R&D and education in system-on-chip design

    Publication Year: 2004, Page(s):77 - 80
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (586 KB) | HTML iconHTML

    With fabrication technologies enabling the integration of a billion transistors and allowing gigahertz frequencies, complex systems (system-on-chip, SoC) can be realized on a single die. The design of such systems provides tremendous challenges to industry and academia. Universities need to invest a huge effort to restructure their related engineering curricula, which is only possible in close co-... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Estimation of a maximum bound of uncertain parameter fluctuations with applications to analogue IP-cores

    Publication Year: 2004, Page(s):161 - 164
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (564 KB) | HTML iconHTML

    In analogue circuits, parameter fluctuations trigger variations in functional behaviour. However, such fluctuations may not result in faulty behaviour and, hence, the circuit may still function satisfactorily. Therefore, it is necessary to estimate a maximum bound of fluctuations that retains satisfactory functional behaviour. A method is presented which integrates design and test and is based on ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Lessons learned from designing the MONTIUM - a coarse-grained reconfigurable processing tile

    Publication Year: 2004, Page(s):29 - 32
    Cited by:  Papers (7)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (623 KB) | HTML iconHTML

    In this paper we describe in retrospective the main results of a four year project, called Chameleon. As part of this project we developed a coarse-grained reconfigurable core for DSP algorithms in wireless devices denoted MONTIUM. After presenting the main achievements within this project we present the lessons learned from this project. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Invited presentations

    Publication Year: 2004, Page(s): xv
    Request permission for commercial reuse | PDF file iconPDF (407 KB) | HTML iconHTML
    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Application specific instruction-set processors (ASIP's) for wireless communications: design, cost, and energy efficiency vs. flexibility

    Publication Year: 2004, Page(s):1 - 2
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (449 KB) | HTML iconHTML

    Summary form only given. The next generation of wireless communication systems will be cognitive to efficiently use the available bandwidth. For a given criterion, these systems will adaptively select the transmission method, protocol and the services which are optimal at any given time. Sophisticated signal processing algorithms of ultra high complexity must be executed to perform this adaptation... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Reusable XGFT interconnect IP for network-on-chip implementations

    Publication Year: 2004, Page(s):95 - 102
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (879 KB) | HTML iconHTML

    Platform-based design flows are coming into use in system-on-chip (SoC) circuit design. These design flows, which integrate different processors, large memory subsystems, reconfigurable logic blocks and reusable intellectual property (IP) blocks for various purposes into the same platform, use also reusable interconnect IP (IIP) blocks as communication infrastructures. This work presents a new lay... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • SoC-Mobinet: broadband transceiver design challenges

    Publication Year: 2004
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (448 KB) | HTML iconHTML

    Summary form only given. Decreasing feature size and increasing system complexity enables to map complex systems onto one die (SoC - system on chip) or into one package (SiP - system in package). This reduces development, production and packaging costs of the integrated circuit, increases integration density of the customer products by consuming less board space and optimizes the bill of material ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A model for imaging system-on-chip manufacturing costs

    Publication Year: 2004, Page(s):53 - 56
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (606 KB) | HTML iconHTML

    This work describes some of the issues faced when integrating a CMOS image sensor into a system-on-chip (SoC). A simple method is proposed for estimating the manufacturing costs of imaging SoCs at several silicon processes using readily available information sources. A low-cost imaging SoC with integral DSP is presented and its manufacturing cost calculated. The results indicated that for the exam... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Assertion based verification of PSL for SystemC designs

    Publication Year: 2004, Page(s):177 - 180
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (643 KB) | HTML iconHTML

    In this paper, we present an assertion based verification approach for SystemC designs, based on embedding the property specification language (PSL) using abstract state machines (ASM). Our approach utilizes an existing embedding of PSL in ASM in order to enable modeling of PSL assertions at the ASM level. Here, we propose to compile PSL assertions into C# code, and integrate them with the SystemC... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.