By Topic

Current and Defect Based Testing, 2004. DBT 2004. Proceedings. 2004 IEEE International Workshop on

Date 25 April 2004

Filter Results

Displaying Results 1 - 25 of 42
  • At-speed test for path delay faults using practical techniques

    Publication Year: 2004, Page(s):61 - 66
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (728 KB) | HTML iconHTML

    To detect the smallest delay faults at a fault site, the longest path(s) through it must be tested at full speed. Most existing test generation tools are either inefficient in automatically identifying the longest testable paths due to the high computational complexity or do not support at-speed test using existing practical design-for-testability structures, such as scan design. In this work a te... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Mixed-signal LSI relationship among measurement accuracy, yield, and test time

    Publication Year: 2004, Page(s):43 - 45
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (523 KB) | HTML iconHTML

    As the degree of LSI integration is becoming rapidly greater and circuit size is becoming bigger, the bigger LSI test cost due to longer test time in LSI production becomes more serious. This paper discusses how much impact mixed LSI measurement accuracy improvement affects test time and LSI yield by analyzing the test results in a production test. It is a practical and effective example for the s... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Test volume reduction via flip-flop compatibility analysis for balanced parallel scan

    Publication Year: 2004, Page(s):105 - 109
    Cited by:  Papers (3)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (605 KB) | HTML iconHTML

    Test generation for scan-based test of sequential circuits is typically performed by generating tests for the embedded combinational logic (ECL) and translating these into scan test vectors. However, the serial nature of scan-based test incurs significant overhead in terms of test application time. To reduce the test data volume, in this paper we propose a new algorithm for compatibility analysis ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Calibrating power supply signal measurements for process and probe card variations

    Publication Year: 2004, Page(s):23 - 30
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (904 KB) | HTML iconHTML

    The power supply transient signal (IDDT) methods that we propose for defect detection and localization analyze regional signal variations introduced by defects at a set of the power supply ports on the chip under test (CUT). A significant detractor to the successful application of such methods is dealing with the signal variations introduced by process and probe card parameter variation... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • On the potential of flush delay for characterization and test optimization

    Publication Year: 2004, Page(s):55 - 60
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (664 KB) | HTML iconHTML

    This paper explores the potential of an IC speed estimate, called flush delay, for characterization and test optimization, using Sematech Project S-121 data as a test case. This exploration leads us to conclude that: 1) characterization based on flush delay is a very efficient way to compare test methods aimed to detect IC not meeting speed specifications due to process variations; 2) (design-veri... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Doing more with less: a recipe for rapid IDDQ development

    Publication Year: 2004, Page(s):33 - 42
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (716 KB) | HTML iconHTML

    This paper describes the method for developing and deploying IDDQ testing on two 0.18 μm chips developed at SMA. By using the self-scaling ratio-based IDDQ technique developed by Peter Maxwell, SMA is able to effectively screen defective devices without incurring unnecessary yield penalties. This paper documents the method of generating IDDQ vectors, qualifying them through temperature analysis... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An improved method for iDDT testing in the presence of leakage and process variation

    Publication Year: 2004, Page(s):11 - 16
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (649 KB) | HTML iconHTML

    We propose in this paper a testing method for CMOS circuits that is insensitive to process variations and leakage levels. This method is based on the transient supply current (iDDT) and on the observation that current levels for different circuits on a chip scale with different runs of the process. In this method, we introduce a very simple test circuit on-chip. Then, we apply a normali... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Delay testing based on transition faults propagated to all reachable outputs

    Publication Year: 2004, Page(s):67 - 75
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (858 KB) | HTML iconHTML

    Data from the test floor has shown that transition faults propagated to all reachable outputs (TARO) is more effective in detecting defective chips compared to conventional transition faults [Tseng et al. 2001]. This paper describes an efficient approach to generate tests pattern based on TARO metric using Boolean satisfiability. The problem of test pattern generation is converted to an instance o... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A memory built-in self-diagnosis design with syndrome compression

    Publication Year: 2004, Page(s):99 - 104
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (748 KB) | HTML iconHTML

    We present a memory built-in self-diagnosis (BISD) design that incorporates a fault syndrome compression scheme. We also have developed efficient faulty-word, faulty-row, and faulty-column identification methods, which have been incorporated in our new BISD design. Our approach reduces the amount of data that need to be transmitted from the chip under test to the automatic test equipment (ATE). It... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Comparison of wafer-level spatial IDDQ estimation methods: NNR versus NCR

    Publication Year: 2004, Page(s):17 - 22
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (664 KB) | HTML iconHTML

    Extending the useful life of IDDQ test to deep submicron technologies has been a topic of interest in recent years. IDDQ test loses its effectiveness as the signal to noise ratio degrades due to rising background current and fault-free IDDQ variance. Defect detection using IDDQ test requires separation of deterministic sources of variation from defective... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • On the effectiveness of detecting small delay defects in the slack interval

    Publication Year: 2004, Page(s):49 - 53
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (639 KB) | HTML iconHTML

    A new delay testing scheme that identifies abnormal delays in the slack interval by comparing switching delays in neighboring dies on a wafer has been recently proposed and validated on small experimental circuits. In this paper we evaluate the effectiveness of this new approach through the simulation of injected delay faults in the ISCAS benchmark circuits. The results indicate that the new delay... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • On correlating structural tests with functional tests for speed binning

    Publication Year: 2004, Page(s):79 - 83
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (579 KB) | HTML iconHTML

    The utilization of functional vectors has been an industry standard for speed binning purpose. This practice can be prohibitively expensive as the ICs become faster and more complex. In comparison, structural patterns can target performance related faults in a more systematic manner. To make structural test an effective alternative to functional test for speed binning, structural patterns need to ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Fault diagnosis of a GHz CMOS LNA using high-speed ADC-based BIST

    Publication Year: 2004, Page(s):85 - 89
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (596 KB) | HTML iconHTML

    This paper presents a fault isolation method using the digital signatures from a LNA BIST solution. The fault localization capabilities of the functional test and data analysis methods are demonstrated by circuit level simulation. Also a discussion of the efficacy of this method is given. Results showed that only 16% of the resistive faults examined here cannot be mapped to its specification locat... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Automatic test pattern generation for resistive bridging faults

    Publication Year: 2004, Page(s):91 - 96
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (753 KB) | HTML iconHTML

    An ATPG for resistive bridging faults is proposed that combines the advantages of section-based generation and interval-based simulation. In contrast to the solutions introduced so far, it can handle arbitrary non-feedback bridges between two nodes, including ones detectable at higher resistance and undetectable at lower resistance, and faults requiring more than one vector for detection. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • 2004 IEEE International Workshop on Defect Based Testing ( DBT) - Cover

    Publication Year: 2004, Page(s): 0_1
    Request permission for commercial reuse | PDF file iconPDF (15 KB)
    Freely Available from IEEE
  • [Blank page]

    Publication Year: 2004, Page(s): 0_2
    Request permission for commercial reuse | PDF file iconPDF (3 KB)
    Freely Available from IEEE
  • Proceedings. 2004 IEEE International Workshop on Current and Defect Based Testing (IEEE Cat. No.04EX1004)

    Publication Year: 2004
    Request permission for commercial reuse | PDF file iconPDF (28 KB)
    Freely Available from IEEE
  • Copyright

    Publication Year: 2004, Page(s): ii
    Request permission for commercial reuse | PDF file iconPDF (22 KB)
    Freely Available from IEEE
  • Table of contents

    Publication Year: 2004, Page(s):iii - iv
    Request permission for commercial reuse | PDF file iconPDF (64 KB)
    Freely Available from IEEE
  • Welcome message

    Publication Year: 2004, Page(s): v
    Request permission for commercial reuse | PDF file iconPDF (99 KB) | HTML iconHTML
    Freely Available from IEEE
  • Organizing Committee

    Publication Year: 2004, Page(s): vi
    Request permission for commercial reuse | PDF file iconPDF (26 KB)
    Freely Available from IEEE
  • Program Committee

    Publication Year: 2004, Page(s): vii
    Request permission for commercial reuse | PDF file iconPDF (29 KB)
    Freely Available from IEEE
  • [Breaker page]

    Publication Year: 2004, Page(s):viii - x
    Request permission for commercial reuse | PDF file iconPDF (32 KB)
    Freely Available from IEEE
  • [Breaker page]

    Publication Year: 2004, Page(s): 1
    Request permission for commercial reuse | PDF file iconPDF (11 KB)
    Freely Available from IEEE
  • [Blank page]

    Publication Year: 2004, Page(s): 2
    Request permission for commercial reuse | PDF file iconPDF (5 KB)
    Freely Available from IEEE