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Signal Propagation on Interconnects, 2004. Proceedings. 8th IEEE Workshop on

Date 9-12 May 2004

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Displaying Results 1 - 25 of 85
  • Characterization of via holes on printed circuit boards

    Page(s): 211 - 214
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (680 KB) |  | HTML iconHTML  

    When high speed digital signals propagate on printed circuit boards (PCBs), all the on board discontinuities are a concern for the electronic designers. Among them, the via holes, allowing the signals to jump from an external PCB layer to an internal one, are of paramount importance. The paper compares the transmission performances of three different kind of single ended and differential vias (through, blind and buried), providing the better solution for propagating high speed digital signals on a multi-layer PCB. View full abstract»

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  • Dampening high frequency noise in high performance microprocessor packaging

    Page(s): 53 - 56
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (560 KB) |  | HTML iconHTML  

    In high performance microprocessors, power supply noise needs to be controlled to ensure reliable high speed bus operation. This is generally done with high quality package capacitors and on die capacitance. These capacitors are generally lower equivalent series inductance (ESL) and lower equivalent series resistor (ESR). Because the ESL is not zero, die capacitance is required to reduce the impact of this ESL on the power supply noise. Alternatively, in this paper, we present a novel approach of using an on-die metal resistor in series with the package capacitance to dampen the high frequency noise. We show by validation on the 90 nm technology that this technique is capable of reducing the noise by nearly 80% without adversely affecting the bus speed. View full abstract»

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  • Electrical high speed chip-package characterization comparison of simulation results with component measurement

    Page(s): 215 - 218
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (592 KB) |  | HTML iconHTML  

    The electrical characteristics of interconnects (signal and power nets) of a given multi-chip package (MCP) had to be determined. MCP-nets are mostly multi drop (multi point) nets (MDNs) with in this case up to 18 terminals. The given clock frequency range is 200MHz to 500MHz. The outer dimensions of the MCP under test (MCP u.t.) are about 11 × 12mm. The goal of the analysis was to find out an appropriate way of modelling for such a complex package including signal as well as power nets. It was also necessary to understand if the MCP multi-port nets can be described as lumped circuits in the given performance range of 200MHz to 500MHz as predicted by the λ/20 - and the ts > 5tf - rules for the about 1cm long partial branches of the MDNs. View full abstract»

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  • Non-uniform grid (NG) algorithm for fast capacitance extraction

    Page(s): 109 - 112
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (600 KB) |  | HTML iconHTML  

    A novel approach for computing the capacitance matrices of arbitrary shaped three-dimensional geometries is presented. The proposed approach combines an iterative solution of the pertinent integral equations with the non-uniform grid (NG) algorithm for fast evaluation of potentials due to given source distributions. The NG approach is based on the observation that locally the potential produced by a finite size source can be interpolated from its samples at a small number of points of a non uniform spherical grid. This observation leads to a multilevel algorithm comprising interpolation and aggregation of potentials. The resulting hierarchical algorithm attains an O(N) asymptotic complexity. View full abstract»

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  • A 0.18μm CMOS fully integrated 6.25Gbps single aggressor multi-rate crosstalk cancellation IC for legacy backplane and interconnect applications

    Page(s): 73 - 76
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (671 KB) |  | HTML iconHTML  

    A multi-rate crosstalk canceller for active cancellation of near end cross talk (NEXT) caused by a single aggressor in a backplane channel environment has been demonstrated in this paper. The proposed IC enhances the performance of existing legacy backplane at higher data rates, thereby avoiding the costs associated with upgrading to higher end backplanes and connectors. The IC has been fabricated in a 0.18μm CMOS process and the prototype test bench demonstrated capability of improving the bit-error rate (BER) performance in excess of 5 orders of magnitude at data rates up to 6.25Gbps. View full abstract»

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  • PEEC methods in 2D signal line modeling for mid-frequency on-chip power supply noise simulations

    Page(s): 49 - 52
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (559 KB) |  | HTML iconHTML  

    In this paper a 2D signal line model is used to simulate the power distribution network (PDN). The proposed method uses an admittance function to model the frequency-dependent resistance and inductance in each direction. This admittance function can be gained directly by model order reduction from a partial element equivalent circuit (PEEC) model. Hence, it is possible to efficiently calculate the model parameters even for irregular PDNs. A fast transient simulation algorithm closely related to the finite-difference time-domain (FDTD) schemes is presented. The alternating-direction-implicit (ADI) method relaxes the time step for the simulation, because it is not limited by a stability criterion. View full abstract»

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  • A frequency domain approach for efficient model reduction of mixed VLSI circuits

    Page(s): 171 - 174
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    It has become well accepted that interconnect delay dominates gate delay in current VLSI circuits. This paper introduces a new method, based on a frequency domain approach, for the simulation of interconnect problems found in high speed digital circuits and SOC-AMS. View full abstract»

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  • Implementation of MOR for time domain simulation on real-life interconnect structures

    Page(s): 127 - 130
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (629 KB) |  | HTML iconHTML  

    Stable equivalent circuit models cannot be guaranteed by currently available EM simulation tooling, resulting in non-convergence in time domain simulations. Theoretically it is proven that available MOR methods preserve stability and passivity in the reduction process. Implementation of MOR methods and the realization of equivalent circuit models for actual use in circuit simulation are not straightforward. This paper describes the successful implementation of a MOR method, allowing the generation of equivalent circuit models suitable for time domain simulation. Two examples of time domain simulations performed on real-life interconnect structures are given. View full abstract»

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  • Illustration of the importance of on-chip self and mutual inductances

    Page(s): 113 - 116
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (594 KB) |  | HTML iconHTML  

    Transmission line properties of on-chip wiring need to be taken into account due to the great lengths and fast rise times encountered. In this paper, we show the influence of on-chip self and mutual inductances on timing performances by considering two configurations of parallel coupled interconnects, one with both drivers on the same side, and on the other with the drivers in opposite directions. The differences observed, when the currents in the lines flow in the same direction as opposed to the cases when the currents are in opposite directions shows clearly the influence of mutual inductance. A second comparison ignoring inductive effects shows a discrepancy rate reaching as high as 50% for the output switching delay. View full abstract»

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  • Screening attenuation of differential cable-connector assemblies

    Page(s): 175 - 178
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    High speed data transmission is now required in many applications. One limiting factor on speed can be radiated emissions. This paper presents simulation and measurement results on electromagnetic leakage of various differential cable connector assemblies. Leakage modelling aspects are also considered. Differential and common mode interferences as well as single and double shielded assemblies where grounding pin number directly connected to the cable screen varies are studied. The research methods are FIT simulations and absorbing clamp measurements. It is shown that the symmetry of the differential shielding is important and to suppress common mode interferences high amount of grounding pins is required when unscreened connectors like typical high-speed digital ones are used. Double shielded assemblies leak much less. View full abstract»

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  • A novel modeling approach for multiple coupled wire bond interconnects

    Page(s): 155 - 158
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (650 KB) |  | HTML iconHTML  

    A novel approach for electrical modeling of multiple coupled wire bonds up to a frequency of 10GHz is presented. This paper describes a very easy way to get complex electrical model for complex structures like multiple coupled wire bonds. Electromagnetic field computation and compact model extraction using optimization algorithm is limited on few elements. A very efficient way is starting with the development of an equivalent circuit model for a single wire bond. The electrical model of single interconnect is used to model coupled interconnects. Full wave electromagnetic field computation was used to calculate the S-parameters. S-parameters are very good suitable to extract compact models for radio frequencies (RF). Moreover, this procedure is still more effectively by using parameterized models for design kits and libraries. View full abstract»

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  • Layout synthesis algorithm of embedded passive components for RF and EMC reliable system design

    Page(s): 201 - 204
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (724 KB) |  | HTML iconHTML  

    The integration of passive components onto a module platform offers great potential for miniaturization of RF and microwave systems. Development of component design with respect to electrical requirements is one of the challenges in RF system design. This paper first introduces a layout synthesis algorithm for embedded passive components like capacitor, resistor and inductor. For required electrical parameter of embedded passives (main values) including RF characteristic (resonant frequency, quality factor, 3dB cutoff frequency) the optimized component layout are generated. For electrical simulation respective s-parameter and equivalent circuit model are derived. This synthesis procedure is a break through for modern RF system design. The synthesis algorithm is universal and can be applied easily for various design types of embedded inductors, capacitors and resistors. The method is demonstrated using HDI organic square loop inductors as a specific example. View full abstract»

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  • Sensitivity analysis of generic on-chip ΔI-noise simulation methodology

    Page(s): 35 - 38
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (674 KB) |  | HTML iconHTML  

    Power integrity, i.e. providing a stable voltage supply under the condition of rapidly changing current transients, gets increasing attention in the design of electronic packaging. Part of this discussion is the on-chip ΔI-noise. Various simulation methodologies, e.g. RAPiD, are known for simulation. Characteristic for these simulations is the very time consuming task of collecting and processing the complex input data, in order to optimise the required effort a sensitivity analysis for high-frequency on-chip ΔI-noise simulation has been carried out. This paper describes the results of this sensitivity analysis. A generic description of the on-chip ΔI-noise simulation methodology is shown. In particular the required input data is described. The sensitivity analysis quantifies the impact of each simulation parameter on the simulation results. The nominal value of each input parameter has been varied in a range from 0.5x to 2.0x compared to a nominal case. The maximum HF ΔI-noise is measured and plotted versus the respective input parameter deviation. The input parameters are categorized in high, medium and low impact parameters. This analysis results in guidelines which design parameters most efficiently reduce HF-noise and/or which input parameter need to be accurate in order to obtain accurate simulation results. View full abstract»

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  • Analysis of power delivery network constructed by irregular-shaped power/ground plane including densely populated via-hole

    Page(s): 31 - 34
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (620 KB) |  | HTML iconHTML  

    Due to the high speed and low power trends, the design of the power distribution network (PDN) in multi-layer printed circuit board (PCB) becomes more important. This paper presents a fast and efficient analysis methodology for power/ground plane pair considering irregular shaped power plane and via effects in the frequency-domain. The proposed method uses parallel-plate transmission line theory and partitioning of the plane considering geometry properties. Using the popularly used circuit simulator SPICE, we have analyzed input-impedance of the power/ground plane pair. Due to the higher accuracy and the faster simulation time, the proposed method is applicable to the early design step of multi-layer PCB. Characteristic of power distribution network implemented by perforated plane is determined based on full-wave analysis using FDTD periodic structure modeling method. View full abstract»

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  • Efficient algorithm for sensitivity analysis of nonuniform transmission lines

    Page(s): 135 - 138
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (621 KB) |  | HTML iconHTML  

    A new orthogonalization algorithm is presented for sensitivity analysis techniques based on the integrated congruence transform. The proposed technique does not require sensitivity moments to be computed explicitly to generate an orthogonal basis that spans their subspace. The proposed algorithm can be used to construct an orthogonal basis for a general set of elements in Hilbert space related through an inhomogeneous differential operator. Simulation results demonstrate improved numerical accuracy by using the new orthogonalization technique. View full abstract»

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  • Effect of inductance on interconnect propagation delay in VLSI circuits

    Page(s): 121 - 124
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (523 KB) |  | HTML iconHTML  

    In the paper the analytical formula for the propagation delay of CMOS gate driving a distributed RLC line was derived. It is shown that obtained formula is more accurate in some cases than used in literature. The main idea of the presented approach is based on the expansion of the voltage unit step response into Taylor series. The coefficients of this expansion are calculated in symbolical manner in frequency domain as the moments determined for infinite frequency. View full abstract»

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  • An enhanced transmission line model for full-wave analysis of interconnects in non-homogeneous dielectrics

    Page(s): 21 - 24
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (632 KB) |  | HTML iconHTML  

    An enhanced transmission line model has been recently proposed by the authors to perform the full-wave analysis of high-frequency interconnects. Such a model, while retaining the same simplicity of a transmission line model, describes accurately the case where the signal characteristic wavelength is comparable to the interconnect transverse dimension. The model has been obtained from an integral formulation of the propagation problem by using electromagnetic potentials with Lorenz gauge, with reference to a pair of cylindrical wires in homogeneous dielectric. Here the model is extended to interconnects with arbitrary cross-sections, embedded in a non-homogeneous dielectric. The main difference is in the reformulation of the problem by adding new unknowns (the polarization charges and displacement currents of the dielectrics), so that the potential may still be expressed through the Green function of the free space. View full abstract»

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  • Investigating the global suppression of the power/ground plane noise

    Page(s): 209 - 210
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (513 KB) |  | HTML iconHTML  

    In this paper, the global suppression of the power/ground noise induced by a transient current on vias within a parallel-plate power distribution system is studied. Two different methods of noise suppression, i.e. differential via routing and application of an electromagnetic bandgap (EBG) structure, are investigated. The latter offers noise suppression in all azimuthal directions, while the noise suppression achieved by differential routing depends on the location of the observation point and improves at farther distances from the source. View full abstract»

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  • On the modelling of interconnection discontinuities

    Page(s): 187 - 188
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (497 KB) |  | HTML iconHTML  

    An efficient and simple method of modelling of printed-circuit board (PCB) discontinuities is presented. Based on time-domain measurements and subsequent microwave analysis the method enables the PCB discontinuity S-parameters to be calculated. Then, as black box, they can be incorporated into a circuit simulator in order to carry out the transient analysis of overall digital module. The modelling results of DIN-connector are compared to experimental data and good agreement is reported. View full abstract»

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  • A new integral-equation-based, full-wave layered interconnect simulator

    Page(s): 25 - 28
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (582 KB) |  | HTML iconHTML  

    Full-wave simulators are required for accurate modeling of high-performance, 3D interconnects. However, current full-wave solvers are too inefficient to handle large interconnect problems. In this paper, a new efficient, integral-equation-based, full-wave layered interconnect simulator (UA-FWLIS) is developed by using analytical methods and incorporating physics-based expansion function. The accuracy of the simulator developed using this strategy is validated by comparing with commercial simulator tools. View full abstract»

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  • Cross-talk noise in repeater networks

    Page(s): 77 - 80
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (622 KB) |  | HTML iconHTML  

    To avoid unjustified optimism in noise prediction in the absence of accurate analysis of switching activity, commercial tools have to make the most conservative assumption about aggressor switching which leads to an overly pessimistic result in situations of strongly correlated signals connected by repeaters. Such pessimism in the noise analysis hides out the effect of interleaved repeaters used to minimize noise in long, coupled interconnects. In the proposed approach we accurately analyze coupled networks with repeaters by considering timing and logical correlations, and multiple signal switching. We demonstrate an 81% reduction in the number of false noise violations in a design where interleaved repeaters are used for crosstalk critical global interconnects. View full abstract»

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  • A 0.18μm-CMOS near-end crosstalk (NEXT) noise canceller for 4-PAM/20Gbps throughput transmission over backplane channels

    Page(s): 179 - 182
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (578 KB) |  | HTML iconHTML  

    This paper demonstrates an active near-end crosstalk (NEXT) noise canceller intended for use in commercial backplanes. Optimum system architecture and specifications are generated using measured channel data. Additionally, CMOS circuit implementation approaches are introduced and their performances are discussed. The NEXT canceller is applied to a 20Gbps 4-PAM signal over a 16-inch backplane channel and shows 75% cancellation. View full abstract»

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  • A fast algorithm for near optimal passive reduction of high-speed interconnect networks

    Page(s): 91 - 94
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (559 KB) |  | HTML iconHTML  

    With the increasing operating frequencies and functionality in modern designs, the resulting size of circuit equations of high-frequency modules are becoming large. Two-level passive model-reduction based algorithms were recently suggested to obtain compact macromodels for fast transient analysis of large scale circuits. This paper describes an efficient algorithm for reducing the computational cost involved in second level passive reduction algorithms. View full abstract»

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  • Modelling the dynamic response of on-chip decoupling capacitors

    Page(s): 39 - 42
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (619 KB) |  | HTML iconHTML  

    High-speed digital circuits require increasing amounts of on-chip decoupling capacitors (decaps) to preserve power integrity. Therefore, proper modelling and analysis of the dynamic response of such decaps in the high frequency range is needed. This paper shows that, in that range, lumped decap models fail and have to be substituted by distributed models. A derivation of such distributed model based on physical grounds is presented and compared with SPICE non-quasi static MOS models. View full abstract»

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  • Effects of mode conversion on parasitic coupling in high-speed VLSI circuits

    Page(s): 193 - 196
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (661 KB) |  | HTML iconHTML  

    The mode conversion means that a modification of the electromagnetic field configuration occurs, generally, after discontinuities. In deep submicron digital ULSI circuits, the mode conversion analysis is indispensable to identify the signal return path, the return current distribution and therefore, for an accurate inductance modelling which remains a challenging problem (Y. I. Ismael and E. G. Friedman, 2000). On the other hand, switching activity of high speed CMOS circuit may produce large current derivatives in wires (crosstalk) and substrate. These current transients can generate large potential surges and coupled noise. In this mind, a reduction of the mode conversion phenomenon decreases noise in high speed ULSI circuits (Y. Quere et al., 2003). We have investigated the mode conversion, in the frequency domain, for multiple-line inter-layer transitions in CMOS devices. The signal integrity analysis in time domain proved the detrimental effects of mode conversion. Finally, we confirmed that our design rule reduces the mode conversion phenomenon in the case of transition with multiple coupled lines. View full abstract»

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