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Multiple-Valued Logic, 1994. Proceedings., Twenty-Fourth International Symposium on

Date 25-27 May 1994

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  • Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)

    Publication Year: 1994
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  • Interband-tunneling III-V semiconductor structures for multiple-valued literal and arithmetic functions

    Publication Year: 1994 , Page(s): 198 - 206
    Cited by:  Papers (2)
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    Earlier MVL circuits used resonant tunneling devices based on intraband tunneling. Recently device concepts were explored in the AlSb/InAs system based on interband tunneling. Here non-resonant tunneling discharge from the 2DEG is effected into p+ doped InAs gates, whereas the 2DEG current is controlled with a Schottky gate as in the conventional HEMT. A wide range of physical and functional device features is possible. Linear properties of the proposed tunneling HEMTs are used for signal summation. The authors explore basic ternary half adders and redundant MVL full adders. The interband tunneling also leads to highly effective literal circuits with applications in MVL synthesis and pattern recognition. Vertically integrated tunnel gates are introduced. Recommendations for experiments and further theoretical work conclude this paper View full abstract»

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  • Searching for complete functions over E(3) with small radii

    Publication Year: 1994 , Page(s): 172 - 176
    Cited by:  Papers (1)
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    Recent advances in laser and fiber optic technology have made it feasible to build optical processors which are based upon value systems larger than E(2)={0,1}. The problem of designing a transistor which can be used as the basis for the circuits of such a processor involves a detailed study of functions which are either complete or complete with constants over E(3) and E(4). The radii of all complete functions over E(3) have been calculated but the sequential methods used cannot be applied over E(4). The authors use the known results for E(3) to develop genetic algorithm techniques to “grow” functions over E(3) with small radii. The paper ends with a discussion of the modifications needed to move the techniques developed for E(3) to a massively parallel environment so that complete functions over E(4) with small radii may be developed View full abstract»

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  • Enumeration of function and bases of three-valued set logic under compositions with Boolean functions

    Publication Year: 1994 , Page(s): 164 - 171
    Cited by:  Papers (4)
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    This paper discusses some classification and enumeration problems in r-valued set logic, which is the logic of functions mapping n-tuples of subsets into subsets over r values. Boolean functions are convenient choice as building blocks in the design of set logic functions. Weak maximal sets are these containing all Boolean functions. The authors give the number of n-ary functions in each weak maximal set and and some properties of intersections of weak maximal sets in r-valued set logic. These properties are used to classify all three-valued set logic functions according to the weak maximal sets they belong to. They prove that there are 29 such classes of functions and give a unary function representative for each of them. Finally, they find the number of n-ary weak Sheffer functions of three-valued set logic, i.e. functions which are complete under compositions with Boolean functions View full abstract»

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  • An algebraic method to decide the deduction problem in many-valued propositional calculus

    Publication Year: 1994 , Page(s): 270 - 273
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    We show that there is a polynomial over the rational number field Q corresponding to a given propositional formula in a given many-valued logic. Then, to decide whether a propositional formula can be deduced from a finite set of such formulas (deduction problem), we only need to decide whether the polynomial vanishes on an algebraic variety which is related to this formula set. By decomposing this algebraic variety, an algorithm to decide this problem is given View full abstract»

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  • Knot automata

    Publication Year: 1994 , Page(s): 328 - 333
    Cited by:  Papers (1)
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    This paper studies a mathematical model for automata as direct abstractions of digital circuitry. We give a rigorous model for distributed delays in terms of a precedence order of operations. The model is applied to automata that arise in the study of topological invariants of knots in three dimensional space and to digital design View full abstract»

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  • On multiple-valued separable unordered codes

    Publication Year: 1994 , Page(s): 350 - 355
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    A new encoding/decoding scheme of multiple-valued separable balanced codes are presented. These codes have 2·m information digits and m·(R-2) check digits in radices R⩾4, and 2·m-1 information digits and m+1 check digits in R=3 where code-length n=R·m. In actual use of code-lengths and radices, it is shown that the presented codes are efficient in comparison with multiple-valued Berger-codes which are known as optimal unordered codes View full abstract»

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  • Parallel processing of fuzzy inferences

    Publication Year: 1994 , Page(s): 134 - 140
    Cited by:  Papers (1)
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    Rule based systems are computationally very demanding, since a large number of rules has to be evaluated every time new input data are observed in order to undertake a corresponding action. The authors study the possible improvements in performance by using parallel processing. Both fine grade algorithms and standard multiprocessor architectures for Mamdani-type fuzzy systems with two inputs and one output are considered. It is shown, that a speed-up close to linear may be achieved. The results may be extended to systems with more than two inputs View full abstract»

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  • Multiple-valued current-mode MOS integrated circuits based on dual-rail source-coupled logic

    Publication Year: 1994 , Page(s): 19 - 26
    Cited by:  Papers (2)  |  Patents (1)
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    This paper presents a design of new multiple-valued current-mode MOS integrated circuits based on dual-rail source-coupled logic. This circuit can be efficiently utilized in implementing high-speed arithmetic VLSI systems. The use of dual-rail source-coupled logic makes it possible to reduce an input voltage swing for a threshold detector, so that the switching delay of the threshold detector can be reduced. This property is suitable for implementing high-speed multiple-valued integrated circuits with low supply voltage. It is demonstrated that the delay of the proposed radix-2 signed-digit (SD) adder based on dual-rail source-coupled logic is reduced to 67 percent in comparison with that of the corresponding binary CMOS implementation View full abstract»

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  • Hereditary clones of multiple valued logic algebra

    Publication Year: 1994 , Page(s): 306 - 313
    Cited by:  Papers (3)
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    We discuss relationships between properties and operations over the set Ω of MVL functions. Closed properties are those invariant under the classical closure operation. A new type of properties, called hereditary, is defined, as well as hereditary closure. We calculate the ratio of hereditary properties, describe the families of maximal hereditary clones, and give a formula for their enumeration. We show that there are exactly eleven such clones in ternary logic. For Boolean algebra the lattice of all hereditary classes is finite, and we describe it completely. Meanwhile, starting from the three valued case there are still a continuum number of clones View full abstract»

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  • Design of wave-parallel computing circuits for densely connected architectures

    Publication Year: 1994 , Page(s): 207 - 214
    Cited by:  Papers (3)
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    Investigates new architecture LSIs based on wave-parallel computing (WPC) to address the interconnection problems in highly parallel VLSI systems. The underlying concept is frequency multiplexing of digital signals, which enables the utilization of the parallelism of electrical (or optical) waves for parallel processing. The key to success with WPC architecture lies in finding efficient implementation of multi-wave selection function. The paper proposes a multi-wave selection circuit based on coherent detection of modulated waves. The proposed method has potential advantage of high degree of multiplexing and real-time-variable selectivity. Also, its application to the densely connected WPC architecture for minimum-latency image processing is discussed with emphasis on the reduction in the number of interconnections View full abstract»

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  • The satisfiability problem in multiple-valued Horn formulae

    Publication Year: 1994 , Page(s): 250 - 256
    Cited by:  Papers (3)
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    Testing the satisfiability of propositional Horn formulae is an important problem within artificial intelligence due to its repercussions in rule-based systems. This problem has been widely studied and its linearity has been proved for the classical case. However, nothing has been published to solve the satisfiability of multiple-valued Horn formulae, although it is closely related to deduction in expert systems frameworks (where a certainty degree is attached to each fact and rule). In this paper, we propose several new results. First, we present a calculus for multiple-valued Horn clauses and claim its soundness and completeness. Second, we offer a detailed description of an almost linear algorithm for testing the satisfiability of multiple-valued Horn formulae. Finally, the minimal model, the minimal inconsistent interpretation and the maximal set of consistent clauses are defined and furnished by another algorithm which is almost linear too. This information is particularly helpful when validating a rule-based system with a knowledge base formed by a set of multiple-valued clauses View full abstract»

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  • Several remarks on algebraic entropy

    Publication Year: 1994 , Page(s): 319 - 322
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    Following our previous results on axiomatization of entropy of finite functions we introduce an axiomatization of the notion of entropy for equivalence relations. Also, we examine entropic properties of several classes of functions View full abstract»

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  • On T-quantifiers and S-quantifiers

    Publication Year: 1994 , Page(s): 264 - 269
    Cited by:  Papers (3)
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    We show how the “classical” theory of T-norms and S-norms of fuzzy logic can be generalized to a theory of T-quantifiers and S-quantifiers, respectively. The key idea leading to this generalization is the fact that the (infinite) iteration of the two-valued conjunction and disjunction gives the two-valued all-quantifier and ex-quantifier, respectively. In the framework of fuzzy logic the same holds for min with respect to Inf and for max with respect to Sup. As a T-norm (S-norm) is commutative and associative, we can construct an all-τ-quantifier (an ex-σ-quantifier) from a given T-norm τ (S-norm σ). These quantifiers are characterized by axioms (T-quantifiers and S-quantifiers). Furthermore we show that the generating procedure is “complete” with respect to arbitrary T-quantifiers (S-quantifiers) and uniquely reversible View full abstract»

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  • Algebraic division for multilevel logic synthesis of multi-valued logic circuits

    Publication Year: 1994 , Page(s): 44 - 51
    Cited by:  Papers (3)
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    Presents the concept of algebraic division for multilevel logic synthesis of multi-valued logic (MVL). At first, an MVL algebraic division procedure is developed based on a basic set of gates. By introducing two MVL Boolean properties: “identical” and “complementary” into the division operation, the procedure is further improved to be a mix-algebraic division procedure, which can obtain more efficient algebraic division to facilitate multilevel logic synthesis of MVL functions. Experimental results show that, in average, the multilevel implementation cost for an MVL function can have 30.1% cost saving over the two-level implementation, and the improved mix-algebraic division procedure can have 19.4% cost saving over the algebraic division procedure View full abstract»

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  • A four-valued logic and switch-level differences

    Publication Year: 1994 , Page(s): 362 - 367
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    In this paper, the application of a four-valued logic to the switch-level test generation is studied. A switch-level operator fault model is proposed. Switch-level U difference and Z difference of a function to a fault are defined. A method to derive switch-level differences is given. Finally, a new switch-level test generation algorithm for CMOS circuits is presented View full abstract»

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  • Soft computing perspectives

    Publication Year: 1994 , Page(s): 276 - 281
    Cited by:  Papers (1)
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    Soft computing stands for methods and techniques in fuzzy logic, probabilistic reasoning, neural networks, genetic algorithms, chaos or other approaches related to cognitive modelling. These overlapping domains can reinforce each other, thus offering suitable tools to represent and solve real world problems. Genetic algorithms and classifier systems are introduced in the framework of soft computing. Their interactions with other fields are discussed, especially in relation to neural networks and fuzzy logic based systems of If-Then rules. It finally presents fuzzy genetic algorithms involving soft (fuzzy) crossover operators View full abstract»

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  • Multiple-valued combinational circuits with feedback

    Publication Year: 1994 , Page(s): 342 - 347
    Cited by:  Papers (1)
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    We consider the use of feedback loops in the realization of multiple-valued combinational circuits. We show that the number of purely combinational configurations in an r-valued system is 1/r of the total number. Thus, as the radix increases, the fraction of combinational configurations decreases. We also show that, for every radix value r, there is a circuit with feedback realizing a combinational logic function that has fewer gates than any feedback-free circuit View full abstract»

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  • Resonant tunneling diodes for multi-valued digital applications

    Publication Year: 1994 , Page(s): 188 - 195
    Cited by:  Papers (24)  |  Patents (1)
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    Resonant tunneling diodes (RTD) have unique folding V-I characteristics, which lend themselves to multi-valued applications, The negative differential resistance of RTDs renders the operating points self-latching and stable. Any positive resistance in series with an RTD can give rise to hysteresis, especially at high frequencies, The hysteresis effect limits the operation of some multi-valued circuits, but can be utilized to produce some useful functions in other applications. In most applications, the input connection and the output connection are sequentially clocked to achieve isolation. An RTD can achieve higher operating frequency operation than conventional devices, and the maximum operating frequency is often limited by the dynamic hysteresis effect View full abstract»

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  • Completeness criteria in many-valued set logic under compositions with Boolean functions

    Publication Year: 1994 , Page(s): 177 - 183
    Cited by:  Papers (5)  |  Patents (1)
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    Discusses the functional completeness problems in r-valued set logic, which is the logic of functions mapping n-tuples of subsets into subsets over r values. Boolean functions are convenient choice as building blocks in the design of set logic functions. A set of functions F is Boolean complete if any set logic function can be composed from F once all Boolean functions are added to F. The paper proves that there are 2r-2 Boolean maximal sets in r-valued set logic and gives their description using equivalence relations. A set F is then Boolean complete if it is not a subset of any of these 2r-2 Boolean maximal sets, which is a completeness criteria in many-valued set logic under compositions with Boolean functions View full abstract»

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  • Quaternary multiplier circuit

    Publication Year: 1994 , Page(s): 15 - 18
    Cited by:  Papers (3)
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    A new quaternary multiplier circuit is presented. This current-mode CMOS circuit multiplies the values of two quaternary-valued input currents and adds a ternary-valued carry input current to generate the two-quaternary-digit output: a most-significant-digit ternary-valued CARRY output current and a quaternary-valued PRODUCT output current. This multiplier circuit uses 49 MOS transistors and generates its outputs in about 10 microseconds, worst case View full abstract»

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  • A field programmable analog array for continuous, fuzzy, and multi-valued logic applications

    Publication Year: 1994 , Page(s): 148 - 155
    Cited by:  Papers (4)  |  Patents (1)
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    We propose a novel approach to the realization of continuous, fuzzy, and multi-valued logic (mvl) circuits. We demonstrate how a general-purpose field programmable analog array (FPAA), with cells realizing simple arithmetic operations on signals, can be used for this purpose. The FPAA, which is being implemented in a bipolar transistor array technology, operates from ±3.3 V or ±5 V power supplies and works in the range of frequencies up to several hundred MHz View full abstract»

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  • Design of fault-tolerant cellular arrays on multiple-valued logic

    Publication Year: 1994 , Page(s): 297 - 304
    Cited by:  Papers (5)
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    This paper discusses the problems of the design and the fault tolerance in multiple-valued cellular arrays by considering the single-level array, the two-level array and the three-level array. These arrays are constructed by some cells that have the unique switch operation. It assumes the stuck-at-0 fault and the stuck-at-(k-1) fault of the switch cells on k-valued cellular arrays. The fault-tolerant arrays for the single fault are constructed by building a duplicate row and a duplicate column iteratively in the arrays. By evaluating three types for the design, the fault tolerance and the testability for multiple faults, it clarifies that the two-level array is the most suitable structure. Finally, the comparison with formerly presented arrays shows advantages for our fault-tolerant two-level array View full abstract»

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  • Multi-peak resonant tunneling diodes based fuzzifiers

    Publication Year: 1994 , Page(s): 156 - 161
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    In contrast to conventional CMOS and bipolar implementations for fuzzifier hardwares, the newly proposed fuzzifier circuits take advantage of the unique folding characteristic of one class of quantum well device, namely, the resonant tunneling diode (RTD). Three different types of RTD based fuzzifiers are proposed depending on the kinds of intrinsic I-V characteristics available. For fuzzy logic purposes, the multi-peaked RTD I-V characteristics can be generally classified as triangular, sawtooth and hysteretic types. The speed of operation, i.e. fuzzy logic inference per second (FLIPS) is expected to be high, and circuit complexity is reduced with respect to previously proposed fuzzifier circuits using conventional devices such as CMOS View full abstract»

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  • On scheduling in multiprocessor systems using fuzzy logic

    Publication Year: 1994 , Page(s): 141 - 147
    Cited by:  Papers (1)
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    Proposes an algorithm for processor partitioning in multiprocessor systems. The algorithm is based on fuzzy logic. It takes crisp inputs that represent the remaining amount of work and the efficiency of an application and produces the output that determines the number of processors that are to be allocated to the application during a given reallocation period. Simulation results are presented that indicate the effectiveness of the proposed scheme View full abstract»

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