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11th IEEE International Symposium on Asynchronous Circuits and Systems

Date 14-16 March 2005

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  • Proceedings. 11th IEEE International Symposium on Asynchronous Circuits and Systems

    Publication Year: 2005
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  • 11th IEEE International Symposium on Asynchronous Circuits and Systems - Title Page

    Publication Year: 2005, Page(s):i - ii
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  • 11th IEEE International Symposium on Asynchronous Circuits and Systems - Copyright Page

    Publication Year: 2005, Page(s): iv
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  • 11th IEEE International Symposium on Asynchronous Circuits and Systems - Table of contents

    Publication Year: 2005, Page(s):v - vi
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  • Message from the Chairs

    Publication Year: 2005, Page(s):vii - viii
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  • Symposium Committee

    Publication Year: 2005, Page(s): ix
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  • Technical Program Committee

    Publication Year: 2005, Page(s): ix
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  • Additional reviewers

    Publication Year: 2005, Page(s): x
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  • Steering Committee

    Publication Year: 2005, Page(s): x
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  • Deep pipelines vs. risk and power walls [microprocessors]

    Publication Year: 2005
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (19 KB)

    Summary form only given. Intel's ×86 processors pushed pipelining and clock rates until physics stopped us. Less obviously, we were also pushing complexity, and therefore risk. We now know where the limits to these trends lie: with the Prescott processor. This talk explores the nature of risk in chip developments, how the ever-deepening pipelines in the Pentium series affected, and were affe... View full abstract»

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  • Energy efficient surfing [latchless pipelining technique]

    Publication Year: 2005, Page(s):2 - 11
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (272 KB) | HTML iconHTML

    Surfing is a latchless pipelining technique where the propagation delays of gates and other logic functions are modulated to produce event attractors. We describe a test chip that demonstrates a surfing pipeline ring and then introduce new circuits that dramatically reduce the energy overhead for surfing. Our test chip implements a twelve-stage, surfing ring that supports two independent waves of ... View full abstract»

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  • GasP control for domino circuits

    Publication Year: 2005, Page(s):12 - 22
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (216 KB) | HTML iconHTML

    We present two novel asynchronous control circuits for domino pipelines. The control circuits are based on GasP circuits, have a minimum cycle time of six gate delays, and compare favorably with previously published control circuits. We present some results from a chip implementation of several 64-bit domino adders in a TSMC CMOS 180 nm process technology. View full abstract»

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  • Design of high-performance power-aware asynchronous pipelined circuits in MOS current-mode logic

    Publication Year: 2005, Page(s):23 - 32
    Cited by:  Papers (3)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (544 KB) | HTML iconHTML

    This paper introduces the implementation of multi-GHz power-aware asynchronous pipelined circuits in MOS current-mode logic (MCML). The C-element and double-edge-triggered flip-flop are implemented in MCML and used in the so-called micropipeline circuits. An input data detector is proposed to put the inactive combinational logic into sleep mode. The effects of different layout techniques on the pe... View full abstract»

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  • Scheduling discipline for latency and bandwidth guarantees in asynchronous network-on-chip

    Publication Year: 2005, Page(s):34 - 43
    Cited by:  Papers (42)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (472 KB) | HTML iconHTML

    Guaranteed services (GS) are important in that they provide predictability in the complex dynamics of shared communication structures. This paper discusses the implementation of GS in an asynchronous network-on-chip. We present a novel scheduling discipline called asynchronous latency guarantee (ALG) scheduling, which provides latency and bandwidth guarantees in accessing a shared media, e.g. a ph... View full abstract»

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  • An asynchronous router for multiple service levels networks on chip

    Publication Year: 2005, Page(s):44 - 53
    Cited by:  Papers (30)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (216 KB) | HTML iconHTML

    Networks on chip that can guarantee quality of service (QNoC) are based on special routers that can support multiple service levels. GALS SoCs call for asynchronous NoC implementations, to eliminate the need for synchronization when crossing clock domains. An asynchronous multi-service level QNoC router is investigated. It comprises multiple interconnected input and output ports, and arbitration m... View full abstract»

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  • An asynchronous NOC architecture providing low latency service and its multi-level design framework

    Publication Year: 2005, Page(s):54 - 63
    Cited by:  Papers (91)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (200 KB) | HTML iconHTML

    The demands of scalable, low latency and power efficient system-on-chip interconnect cannot only be satisfied by point-to-point or shared-bus interconnects. In this paper, we propose a new asynchronous network-on-chip (NOC) architecture which provides low latency transfers. This architecture is implemented as a GALS system, where chip units are built as synchronous islands, connected together usin... View full abstract»

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  • Register-communication between mutually asynchronous domains

    Publication Year: 2005, Page(s):66 - 75
    Cited by:  Papers (6)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (160 KB) | HTML iconHTML

    We present the design of several so-called communication registers, which are modules that support non-blocking communication between two mutually asynchronous domains. For that purpose, a communication register offers two mutually asynchronous access ports: a write and a read port. Communication registers differ from buffers in that read and write accesses are never held up. Consequently, data ma... View full abstract»

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  • Request-driven GALS technique for wireless communication system

    Publication Year: 2005, Page(s):76 - 85
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB) | HTML iconHTML

    A globally asynchronous - locally synchronous (GALS) technique for application in wireless communication systems is proposed and evaluated. The GALS wrappers are based on a request-driven operation with an embedded time-out function. A formally verified GALS wrapper is deployed for the 'GALSiftcation' of a baseband processor for WLAN. Details of the GALS partitioning, implementation and the design... View full abstract»

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  • Self-timed circuitry for global clocking

    Publication Year: 2005, Page(s):86 - 96
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1912 KB) | HTML iconHTML

    We present an apparatus used to distribute a timing reference or clock across the extent of a digital system. Self-timed circuitry both generates and distributes a clock signal, while using less power and less skew compared to a clock tree. HSpice simulations, in a 180 nm CMOS process, comparing the distributed clock generator presented in this paper and an H-tree clock distribution system, each c... View full abstract»

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  • Proximity communication and time [capacitively coupled IC communication]

    Publication Year: 2005
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (20 KB)

    Summary form only given. Two IC chips placed face-to-face can communicate without direct electrical contact. The capacitive coupling between their top-level metal layers can carry data. We have demonstrated such "proximity communication" on 50 μm centers and data rates similar to on-chip wires. Such communication offers attractive speed, density, and energy economy, but requires accurate mechan... View full abstract»

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  • Modeling and verifying circuits using generalized relative timing

    Publication Year: 2005, Page(s):98 - 108
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB) | HTML iconHTML

    We propose a novel technique for modeling and verifying timed circuits based on the notion of generalized relative timing. Generalized relative timing constraints can express not just a relative ordering between events, but also some forms of metric timing constraints. Circuits modeled using generalized relative timing constraints are formally encoded as timed automata. Novel fully symbolic verifi... View full abstract»

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  • Controlling event spacing in self-timed rings

    Publication Year: 2005, Page(s):109 - 115
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (808 KB) | HTML iconHTML

    Prior research in event spacing has identified two effects which contribute to the phenomenon of bursting events in self-timed systems, namely the Charlie and the Drafting effects. In this paper, we attempt to further the understanding of these effects by presenting an analysis of their magnitude for a range of asynchronous handshaking controller implementations. The main contribution of this work... View full abstract»

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  • Delay insensitive encoding and power analysis: a balancing act [cryptographic hardware protection]

    Publication Year: 2005, Page(s):116 - 125
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1024 KB) | HTML iconHTML

    Unprotected cryptographic hardware is vulnerable to a side-channel attack known as differential power analysis (DPA). This attack exploits data-dependent power consumption of a computation to determine the secret key. Dual-rail asynchronous circuits have been regarded as a potential countermeasure to this attack. In this paper, we evaluate the security of asynchronous dual-rail circuits against DP... View full abstract»

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  • A scalable counterflow-pipelined asynchronous radix-4 Booth multiplier

    Publication Year: 2005, Page(s):128 - 137
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (344 KB) | HTML iconHTML

    This paper introduces an asynchronous radix-4 Booth multiplier architecture, which is scalable to arbitrary operand lengths while maintaining a constant cycle time per Booth iteration. It has several novel features, including: (i) a novel counterflow organization, in which the data bits flow in one direction and the Booth commands piggyback on the acknowledgments flowing in the opposite direction;... View full abstract»

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  • Continuous-time digital signal processors

    Publication Year: 2005, Page(s):138 - 143
    Cited by:  Papers (21)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (288 KB) | HTML iconHTML

    In this paper, we discuss how asynchronous design techniques can be used in the implementation of continuous-time signal processors. Such processors are presented by signals developed by continuous-time analog-to-digital converters which involve no sampling, and thus do not exhibit aliasing; in addition, the resulting in-band quantization error is lower than in conventional techniques. Several des... View full abstract»

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