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Electronics Packaging Technology Conference, 2004. EPTC 2004. Proceedings of 6th

Date 8-10 Dec. 2004

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Displaying Results 1 - 25 of 160
  • Modelling and application of silicon microphone systems

    Publication Year: 2004 , Page(s): 183 - 188
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (769 KB) |  | HTML iconHTML  

    The modelling procedure described in this publication which is based on a partitioning of the total structure, allows a synthesis of the overall transfer function from simple, physics-motivated equations representing the behaviour of the substructures. Casting this into a Matlab description admits relatively easy combination with a GUI in order to obtain a modelling environment convenient for parameter studies during the development process. In parallel, some package solution for single-chip and array microphones are developed. During the model development it is not possible to consider all kinds of applications taking into account, so that some effects occur first at the finished product. Especially in a car application (handsfree set) for mobile phones occurred parasitic EMC effects. Based on this example, the EMC problems are described and solutions for circuit- as well as for package-level are presented. View full abstract»

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  • Effect of stress on interfacial intermetallic compound development of Sn-Ag-Cu lead-free solder joint on Au/Ni/Cu substrate

    Publication Year: 2004 , Page(s): 414 - 419
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (872 KB) |  | HTML iconHTML  

    The formation of thin intermetallic compounds (IMC) due to reaction between the solder and substrate during device fabrication is essential to achieve a good metallurgical bond. Nevertheless, excessive IMC growth significantly decreases the reliability of the solder joint. The thickness of IMC is influenced by numerous factors during the component fabrication process and in service. Stress is known to be an important factor, but no existing method can be used to study the effect of stress state on IMC growth. This work presents a novel method to study the effect of stress on interface IMC layer growth of Sn-Ag-Cu lead-free solder on the Cu substrate coated with electroless Ni and immersion Au (ENIG). In this technique, C-ring is used and in-plane bending induced tensile and compressive stresses can be applied by tightening the C-ring. Isothermal annealing experiments at 125 °C and at different levels of induced bending stresses on the C-ring were investigated The effect of in-plane tensile and in-plane compressive stresses on IMC growth are quantified. View full abstract»

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  • Design analysis of touch chip for enhanced package and board level reliability

    Publication Year: 2004 , Page(s): 743 - 747
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (662 KB) |  | HTML iconHTML  

    Touch chip, a unique bio-sensor to recognize fingerprint of users, is ideally suited for portable consumer applications such as mobile phones, remote controls, tablet PCs, PDAs, and ultra-thin laptop computers as security system. Modeling is a useful and efficient tool for design analysis. In this paper, both package and board level modeling are performed for touch strip, a new generation of touch chip design. The fatigue life, failure location and crack interface of the critical solder ball during thermal cycling test are predicted. It covers 14 design parameters for solder joint reliability analysis, i.e. die size and thickness, substrate thickness, board thickness, mold compound thickness, solder ball geometry, die attach and mold compound material properties, inclusion of polyimide layer, and temperature cycling range. Package level stress analysis is investigated for polyimide thickness and modulus. The findings help to design a more reliable touch chip at both package and board levels. View full abstract»

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  • Considerations for a robust moisture performance of a flip chip in package for lead-free soldering

    Publication Year: 2004 , Page(s): 218 - 223
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    This work provides a comprehensive study on several approaches to obtain a robust lead-free flip chip package. The influence of materials, chip passivation, package configuration and cleaning processes were investigated to provide insights on the effectiveness of each approach to improve the moisture sensitivity level (MSL) performance. Results showed that the underfill/flux compatibility to the chip passivation has a strong influence on the MSL performance. Furthermore, it was observed that the unmolded version generally has a better MSL performance than the molded flip chip in package (FCIP) for a given material combination. However, there is no strong correlation between MSL performance and material properties. The plasma cleaning and defluxing processes were introduced to assess any potential improvement in MSL performance. Based on the results, plasma cleaning was found to be effective in improving the MSL performance. Defluxing evaluation showed potential for MSL performance improvement provided the defluxing process is well controlled. It is also worth noting that with the right underfill/flux/passivation combination, plasma cleaning may not be necessary to achieve the same MSL performance. In summary, this paper has emphasized the importance of mold compound/underfill/flux/passivation compatibility and the effectiveness of an optimized plasma cleaning or defluxing process to improve MSL performance. This study has also sucessfully demonstrated that MSL 1 performance can be achieved with the right choice of materials combination without additional cleaning processes. View full abstract»

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  • Thermo- and hydro-mechanical modeling of an adhesive flip chip joint

    Publication Year: 2004 , Page(s): 92 - 97
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (709 KB) |  | HTML iconHTML  

    This work presents the results of experimental work combined with numerical analysis, to explore the characteristics of anisotropic conductive adhesive (ACA) interconnects. The experimental program involved the assembly of 5×5mm die with 80 electro-plated Au bumps at 200μm pitch, attached by anisotropic conductive paste (ACP) onto a glass substrate with indium tin oxide (ITO) as conductor lines. Subsequent temperature cycling (TC -40°C/125°C) and temperature-humidity test (TH 85°C/85%RH) were carried out to assess the stability of the joint contact resistance. A bump-force vs joint-resistance (F-R) model based on Power Law was established experimentally. Numerical study using finite element analysis (FEA) was developed to determine the Au bump contact force after assembly, TC and TH simulations. After which, employing the F-R model, the joint resistances were predicted and validated with the experimental test results. The comparison between process modeling and the experimental results gave good agreement, while the TH modeling results showed better correlation compared to TC modeling results. View full abstract»

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  • Resistance characterization of Au bump and anisotropic conductive adhesives under temperature and moisture conditions

    Publication Year: 2004 , Page(s): 420 - 425
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (683 KB) |  | HTML iconHTML  

    In this work, the effect of temperature and moisture on joint resistance of Au bump and ACA is reported. A flip chip on glass (FCOG) test vehicle was used to study the joint resistance of Au bump and ACA after temperature cycling (-40°C/125°C), temperature humidity testing (85°C/85%RH) and moisture preconditioning (MSL 1/3/5). In general, the results showed that Au bump and ACP has a better performance than Au bump and ACF during temperature cycling, temperature humidity testing and moisture preconditioning. The size of the Au bump and conductive fillers is found to an important factor in achieving a joint with low and stable resistance. For improved temperature and moisture performance, the use of a larger Au bump size with a larger conductive filler size is recommended for ACAs. View full abstract»

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  • Direct wafer bonding for photonic MEMS and packaging applications

    Publication Year: 2004 , Page(s): 193 - 196
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (615 KB) |  | HTML iconHTML  

    A low temperature direct wafer bonding of semiconductor substrates has been envisaged. The method developed overcomes the previous techniques where high temperature is required for direct bonding. A combination of specific chemical cleaning and plasma treatment enables the wafers to be adhered together at room temperature. Heat treatment at around 220° C with pressure enables the wafers to be atomically bonded. TEM micrograph reveals that the bonded interface is uniform and smooth. In addition micro-Raman (MR) and SEM with EDAX were also used to investigate the bonded interface. Electrical measurements reveal that the interface does not obstruct the passage of current. This technique would be useful to fabricate photonic devices and also extended for packaging applications. View full abstract»

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  • ECPR (electrochemical pattern replication): metal printing for advanced packaging applications

    Publication Year: 2004 , Page(s): 294 - 297
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (785 KB) |  | HTML iconHTML  

    ECPR (electrochemical pattern replication) is a new fabrication process for the production of microstructures in conducting materials. Using ECPR, the cost of metallization for advanced packaging solutions can be significantly reduced compared to using lithography based processes. The technology utilizes a reusable master electrode for electrochemical pattern replication, which enables direct metallization with short cycle times, high throughput and comparably low equipment investments. ECPR provides metallization on most substrates such as silicon wafers, ceramic substrates and flexible or rigid organic substrates. The technique currently enables pattern transfer of copper structures down to 5/5 μm line/space with uniform material distribution and high resolution patterns with small line width variations. Results from replication studies on both ultrathin polyimide substrates and silicon wafers are presented. View full abstract»

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  • Pressure and depth dependence of sidewall roughness of polymer optical waveguides during reactive ion etching

    Publication Year: 2004 , Page(s): 381 - 384
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (621 KB) |  | HTML iconHTML  

    Sidewall roughness (SWR) of fluorinated polyether waveguides fabricated using reactive ion etching in pure oxygen gas was directly measured using atomic force microscope (AFM). We confirmed that SWR is not the replicate of line edge roughness (LER) of the waveguides. We also confirmed the pressure dependence of SWR for shallow structures and discovered an additional etch depth dependence for deeper structures which counteracts the pressure dependence. Lower O2 pressure etching produces SWR which increases with depth while higher O2 pressure etching produces declining SWR with depth. The depth dependence at lower pressure is explained by the change in the arrival dynamics of etchant ions in a mechanism involving both shadowing and first order reemission effects. View full abstract»

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  • High precision passive alignment flip chip assembly using self-alignment and micromechanical stops

    Publication Year: 2004 , Page(s): 385 - 389
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (715 KB) |  | HTML iconHTML  

    The implementation of passive alignment in optoelectronics packaging is still a challenge. Flip chip assembly of single mode laser diodes requires a post bond alignment accuracy of less than 1 μm. A low cost approach to achieve such high precision alignment is using the self-alignment mechanism in combination with micromechanical stops. In order to prove that this approach is feasible test vehicles were designed and fabricated. This work presents the concept of passive alignment pursued, the experimental setup and results thereof. The design of the test vehicles is described including the bump design as well as bumping and flip chip assembly. View full abstract»

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  • A numerical study of the effects of temperature, moisture and vapour pressure on delamination in a PQFP during solder reflow

    Publication Year: 2004 , Page(s): 98 - 104
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (670 KB) |  | HTML iconHTML  

    Delamination during solder reflow is a critical reliability problem for the plastic IC packages. The main objective of this paper is to investigate the effects of temperature, moisture diffusion and vapour pressure on the likelihood of delamination of the interface between the leadframe pad and the encapsulant. In this paper the entire thermal and moisture history of a plastic IC package is simulated from the start of level 1 moisture preconditioning (85°C/85%RH for 168 hours) to subsequent exposure to a solder reflow process lasting about 5 minutes. The transient development of the strain energy release rate due to thermal stress only Gt, hygrostress only Gh, vapour pressure Gp and combined Gtot are computed and studied by using a new modified crack surface displacement extrapolation method (MCSDEM). Finite element models were constructed for a 160-leaded PQFP. The initial crack length was varied from 0.1mm to 3.5mm in order to study its effect. The results show that for small cracks, the effects of temperature and moisture are dominant while that of vapour pressure is insignificant. For moderate crack lengths, the effect of temperature is greatest. For large crack lengths, the effect of vapour pressure is dominant. View full abstract»

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  • Numerical modeling of annular flow in microchannel

    Publication Year: 2004 , Page(s): 575 - 580
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (626 KB) |  | HTML iconHTML  

    Recent experimental studies on flow boiling in micro-channels reveal that annular flow is the dominant two-phase flow pattern. This study is an initial effort towards the simulation of annular flow in micro-channels. In this article, two-phase axisymmetric flows with phase change are studied. The level-set method is used to track the interface between the phases. To overcome the mass conservation problem of the level-set method, a local mass correction (LMC) scheme is proposed. With the proposed LMC, mass is shown to conserve well even phase change occurs. View full abstract»

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  • Low temperature Si-to-Si wafer bonding with sol-gel coating as intermediate layer

    Publication Year: 2004 , Page(s): 189 - 192
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (609 KB) |  | HTML iconHTML  

    In this study, Si-to-Si bonding process between two 4-inch, p-type silicon wafers has been successfully achieved with the assistance of tetraethylorthosilicate (TEOS) sol-gel coating. Atomic force microscopy (AFM) is used to measure the roughness of the sol-gel coating, and the contact angle of water on the sol-gel coated wafer is measured using an optical contact angle system. Fourier transform infrared spectroscopy (FTIR) is performed to determine the chemical bonds and bonding groups in the coatings. The bond strength is measured using an Instron tensile testing machine. The bond strength of up to 35 MPa has been achieved. The bonding mechanism for the low temperature sol-gel intermediate layer wafer bonding is found to be related to the surface smoothness, porous intermediate layer and high density of OH groups with small amount of absorbed water on the sol-gel coating. View full abstract»

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  • Chip-package co-design of power distribution network for system-in-package applications

    Publication Year: 2004 , Page(s): 499 - 501
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (568 KB) |  | HTML iconHTML  

    A new figure of merit for chip-package co-design of a power distribution network (PDN) is needed, not merely a voltage difference between power and ground at each hierarchy. In order to measure power supply noise as it is actually seen by the circuits in various locations on a chip, we need to chase the power/ground voltage with reference to a system ground. A PDN has two current paths; a series path and a shunt path. While the shunt path determines the voltage difference, the series path controls the power/ground voltage itself. Therefore, a balanced approach is strongly required rather than an excessive attention to the shunt path. View full abstract»

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  • In-situ electromigration studies on Sn-Ag-Cu solder joint by digital image speckle analysis (DISA)

    Publication Year: 2004 , Page(s): 410 - 413
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (677 KB) |  | HTML iconHTML  

    The phenomenon of electromigration in Pb-free Sn-Ag-Cu solder joint specimen subject to high current density was characterized. Electromigration measurements in the direction of the electron flux, via Cu metal lines, ENIG metallization, and Sn-Ag-Cu solder joint is documented. The consequence of this migration phenomenon causes void formation and the significant accumulation of voiding is a serious reliability concern. Digital image speckle analysis (DISA) was used to measure the in-situ micro-deformation of a cross sectioned solder joints, which is subject to electromigration with a current density of 5*103A/cm2 under a constant temperature of 150°C. The deformation and strain field of the solder joint were analyzed by a digital image correlation software. After 120hrs thermal-current test, higher strain near large voids was detected. The IMC growth behavior with/without current are compared. It was noted that IMC layer growth on anode interface is faster than cathode interface, and both are faster than isothermal aging. View full abstract»

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  • Fully cure-dependent polymer modeling and application to QFN-packages warpage

    Publication Year: 2004 , Page(s): 87 - 91
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (632 KB) |  | HTML iconHTML  

    Process-induced warpage is an important issue for package reliability. In order to model the warpage generated during the molding process of QFN packages, a full experimental material characterization of model molding compounds is discussed in This work. Through a method of intermittent cure experiment, the master curve and both a "temperature shift factor" and a "conversion shift factor" are obtained. A series of molding experiments for QFN matrix strips with the model-molding compounds were performed. In the molding process, different combinations of molding temperature/time and post-cure/time were used. The warpage after molding and after post-cure was measured, respectively. The results show that both the filler percentage and the die thickness have significant effects on the warpage level. View full abstract»

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  • Coaxial probe dielectric measurements in the presence of airgaps

    Publication Year: 2004 , Page(s): 496 - 498
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (528 KB) |  | HTML iconHTML  

    Interpolation formulas for retrieval of the dielectric constant of the substrate from the measured probe impedance within a specified frequency range are introduced. The proposed formulas were tested for retrieval of dielectric constant from impedance measurements for the substrates with known properties. It was found that the accuracy of the proposed interpolation formulas is better than 5% within the frequency range of 0.5-20 GHz. View full abstract»

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  • Integrated waveguides for optical interconnects

    Publication Year: 2004 , Page(s): 748 - 752
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (704 KB) |  | HTML iconHTML  

    Optical waveguides offer potential as interconnects for high speed communication. On silicon, the SOI wafer structure allows rib waveguides to be easily fabricated. Large area single mode waveguides have been wet etched and their losses measured. The large turning radius for these waveguides is an economic disadvantage. Compact turning mirrors using the wet etch crystal planes have been fabricated and losses measured. These enable reduced dimensions for devices such as Mach Zehnder interferometers which are a requirement for high speed modulators. Polymers are also a prime candidate for optical waveguides. Preliminary loss results have been obtained for multimode waveguides fabricated from photodefinable SU8. View full abstract»

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  • An optimized face-down bonding process for laser diode packages

    Publication Year: 2004 , Page(s): 390 - 395
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (774 KB) |  | HTML iconHTML  

    We present an optimized face-down die attachment for single-mode ridge-waveguide laser diodes (LDs) using Au80Sn20 solder. Based on this improved technique, a bonding process window has been determined through microstructure and mechanical investigation of the solder joint, and electro-optical characterization of LDs. Metallographical investigation shows that the solder joint comprises of a layer of δ phase near the LD/solder and solder/heatsink interfaces, ζ phase at the center of the solder joint, and a layer of (Au, Ni)Sn intermetallic compound (IMC) at the solder/heatsink interface. The δ phase shifted to the interfaces, while ζ phase Au/Sn compound is remaining at the center of the joint, is postulated by the lower surface tension in δ phase. Mechanical shear testing demonstrates good bonding integrity, which meets the requirements specified by MIL-STD-883C. Fracture surface characterization shows brittle fracture occurring within the LD, at the GaAs/SiN interface. This optimized bonding process can achieve optical improvement of 2.5-3× compared to unbonded LDs due to good thermal management. View full abstract»

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  • A novel decoupling capacitance platform for substrates, sockets, and interposers

    Publication Year: 2004 , Page(s): 231 - 234
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (641 KB) |  | HTML iconHTML  

    Due to increasing demands on the power delivery networks within current and next-generation computer systems, power integrity has become a leading focus, in addition to signal integrity, in system design. We will present a technology deployed within substrates, interposers, or sockets to enhance core power delivery. Our technology is comprised of a novel integration of decoupling capacitance between the core power nets and ground. This decoupling replaces the numerous decoupling capacitors suboptimally placed on traditional printed circuit boards (PCBs). The net result it lowered power supply noise and increased core power stability, permitting greater semiconductor switching frequency while reducing overall system cost. Studying actual system applications, we compare this technology to a wide range of expensive and largely ineffective decoupling strategies that have been proposed and even deployed, and demonstrate its superiority in both cost and performance. View full abstract»

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  • Characterisation of intermetallic growth in copper and gold ball bonds on aluminium metallization

    Publication Year: 2004 , Page(s): 348 - 353
    Cited by:  Papers (28)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (883 KB) |  | HTML iconHTML  

    While the characterisation of intermetallic coverage and intermetallic phase (IP) growth in gold ball bonding on aluminium is quite well understood, there is relatively little literature concerning the morphology and growth of IP's between Cu balls bonded on aluminium pad metallisation. The difference between Cu-Al IP growth compared with the well known Au-Al IP's has been studied mainly of larger wire diameter (35-50μm) in the early 1980's. Cu wire ball bonding has been established for many years mainly for high power devices at wire diameters ≥ 38μm and fine wire for discrete device applications. However, there is now interest in fine pitch Cu wire ball bonding at smaller wire diameters of 25μm and smaller for high pin count applications, driven mainly by cost reduction. Development and optimisation of robust copper wire bonding processes for such applications requires an assessment of intermetallic coverage and Cu-Al intermetallic growth after isothermal aging. This work describes the problems associated with coverage determination, some characteristics of Cu-Al and Au-Al intermetallic compounds and characterises the difference in the IP growth between Au-Al and Cu-Al. The relative merits of gold and copper ballbonding are also briefly discussed. View full abstract»

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  • Link simulation of four channel CWDM transceiver modules

    Publication Year: 2004 , Page(s): 767 - 771
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    Optical communication systems are extremely complex and difficult to analyze. It is often hard to predict the effect of various characteristics of the devices used on the signal fidelity in a fiber optic link. This work involves simulation of 2.5 Gigabits per second (Gbps) coarse wavelength division multiplexing (CWDM) transceiver for end-to-end link performance. Simulation software is available commercially which can realistically model an optical link. Such simulation helps in analyzing the module under development and predicts the performance for a given link distance and the simulation output helps eliminating any likely performance degradation before realizing the actual hardware. The objective of the fiber optic link is to transport data or communication signals reliably over a longer distance. The desired Q factor is approximately 7 and the desired bit error rate (BER) is approximately 10-12. The simulation objective is to ensure that the received pulses are of appropriate shape and of sufficient intensity, with minimized loss due to noise or attenuation, and to remove distortion present in the signal. The Q factor and BER obtained from either the eye diagram analyzer or the BER analyzer are used to analyze the degradation of the signal at the receiver components. View full abstract»

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  • Assembly and characterization of micromachined combustor

    Publication Year: 2004 , Page(s): 172 - 176
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    As part of an effort to develop MEMS-based power generation system, we present the assembly solution and the combustion test results of a recent-developed micro combustion device micromachined from single crystal silicon. Comprising the non-rotating components of a micro turbine engine, each micro combustor is constructed by 7 stacking dies, which are diced from 7 pieces of bulk-micromachined silicon wafer. Each die has identical size (21.50 mm × 21.50 mm) and various thickness, ranging from 400 μm to 800 μm. Deep reactive ion etching (DRIE) process is employed to structure the silicon wafers from both sides. The combustion chamber measures about 94 mm3. The micro combustor is assembled through seamless mechanical clamping by a customized jig, which fixed the dies and provides gas transportation in and out of the micro combustor. Some combustion experiments have been conducted after igniting the fuel/air mixture in the micro chamber. Stable hydrogen-air combustion has been observed to sustain inside the combustion chamber with exit temperature over 1200 °C. During the combustion experiments, the silicon dies keep good mechanical integrity under assembly and no gas leakage is observed. These results show the feasibility of using this micro combustor as a part of micro power generation system. View full abstract»

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  • On the modelling of electrons in thermo-electronic modelling of Si MOSFETs

    Publication Year: 2004 , Page(s): 259 - 263
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    Importance of the modeling of electrons in coupled electro-thermal analysis of Si MOSFETs is discussed. The simple, lumped-electron temperature model predicts drastic increase of the electron temperature above the electric field of the order of 106V/m. Also, the calculation of electron thermal conductivity predicts that the thermal conductivity reaches on the order of 10-1 W/m-K. Numerical calculation of coupled electrical and thermal analysis predicts 103 K order of temperature gradient in the channel region. These results clearly exhibit the importance of the modeling of electrons in the coupled analysis. View full abstract»

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  • Through wafer interconnection technologies for advanced electronic devices

    Publication Year: 2004 , Page(s): 1 - 6
    Cited by:  Papers (2)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (826 KB) |  | HTML iconHTML  

    There is a need for miniaturizing electronic components such as ICs and modules that are used in portable devices like cellular phones and PDAs. Miniaturization not only results in a reduced foot print of the components on the printed board but it can also have a positive effect on the device performance. The ultimate miniaturization is reached when packaging the component into a chip size package (CSP). To enable this, the bonding pads of ICs can be rerouted into, e.g., a ball grid array (BGA) configuration. For devices such as vertical discrete components and stacked dies planar rerouting is not sufficient. Introducing so-called through wafer interconnect enables addressing the back side and so these devices can be converted into CSPs. Although through wafer interconnect requires rather complicated technologies, wafer level processing (resulting in simultaneous fabrication of large number of packages) limits the additional packaging cost. View full abstract»

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