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Test Conference, 2004. Proceedings. ITC 2004. International

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Test Conference, 2004. Proceedings. ITC 2004. International

Date 26-28 Oct. 2004

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Title History

Security vs. test quality: are they mutually exclusive?

At-speed interconnect test and diagnosis of external memories on a system

A design for test technique for parametric analysis of SRAM: on-die low yield analysis

Programmable at-speed array and functional BIST for embedded DRAM LSI

BER estimation for serial links based on jitter spectrum and clock recovery characteristics

Production test effectiveness of combined automated inspection and ICT test strategies

Detecting faults in the peripheral circuits and an evaluation of SRAM tests

Evaluating the effects of transient faults on vehicle dynamic performance in automotive systems

Built-in self-test for system-on-chip: a case study

An SRAM weak cell fault model and a DFT technique with a programmable detection threshold

Use of embedded sensors for built-in-test RF circuits

Open architecture test system: system architecture and design

Hierarchical DFT methodology - a case study

A little DFT goes a long way when testing multi-Gb/s I/O signals

K longest paths per gate (KLPG) test generation for scan-based sequential circuits

Post-packaging auto repair techniques for fast row cycle embedded DRAM

Data compression for multiple scan chains using dictionaries with corrections

Integrating core selection in the SOC test solution design-flow

To test or to inspect, what is the coverage?

Active tester interface unit design for data collection

Formal verification of a system-on-chip using computation slicing

Removing JTAG bottlenecks in system interconnect test

Panel synopsis - diagnosis meets physical failure analysis: how long can we succeed?

Formal description of test specification and ATE architecture for mixed-signal test

How to bridge the gap between simulation and test

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