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High-Performance Computer Architecture, 2005. HPCA-11. 11th International Symposium on

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High-Performance Computer Architecture, 2005. HPCA-11. 11th International Symposium on

Date 12-16 Feb. 2005

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Title History

Proceedings. 11th International Symposium on High-Performance Computer Architecture

[Title page]

Table of contents

Message from the General Chair

Message from the Program Chair

list-reviewer

Organizing Committee

Trends in High-Performance Processors

Multithreaded value prediction

Checkpointed early load retirement

Microarchitectural wire management for performance and power in partitioned architectures

A small, fast and low-power register file by bit-partitioning

Accurate energy dissipation and thermal modeling for nanometer-scale buses

Distributing the frontend for temperature reduction

Performance, energy, and thermal considerations for SMT and CMP architectures

Tapping ZettaRAM™ for low-power memory systems

An efficient programmable 10 gigabit Ethernet network interface card

A new scalable and cost-effective congestion management strategy for lossless multistage interconnection networks

Exploring the design space of power-aware opto-electronic networked systems

Scatter-add in data parallel architectures

Software directed issue queue power reduction

On the limits of leakage power reduction in caches

Heat stroke: power-density-based denial of service in SMT

Voltage and frequency control with adaptive reaction time in multiple-clock-domain processors

Using virtual load/store queues (VLSQs) to reduce the negative effects of reordered memory instructions

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