By Topic

15-17 Nov. 2004

Filter Results

Displaying Results 1 - 25 of 89
  • 13th Asian Test Symposium - Cover

    Publication Year: 2004, Page(s): c1
    Request permission for commercial reuse | PDF file iconPDF (336 KB)
    Freely Available from IEEE
  • Proceedings. 13th Asian Test Symposium

    Publication Year: 2004
    Request permission for commercial reuse | PDF file iconPDF (38 KB)
    Freely Available from IEEE
  • 13th Asian Test Symposium - Copyright Page

    Publication Year: 2004, Page(s): iv
    Request permission for commercial reuse | PDF file iconPDF (41 KB)
    Freely Available from IEEE
  • 13th Asian Test Symposium - Table of contents

    Publication Year: 2004, Page(s):v - x
    Request permission for commercial reuse | PDF file iconPDF (55 KB)
    Freely Available from IEEE
  • Foreword

    Publication Year: 2004, Page(s): xi
    Request permission for commercial reuse | PDF file iconPDF (24 KB) | HTML iconHTML
    Freely Available from IEEE
  • Organizing Committee

    Publication Year: 2004, Page(s):xii - xiii
    Request permission for commercial reuse | PDF file iconPDF (1456 KB)
    Freely Available from IEEE
  • Program Committee

    Publication Year: 2004, Page(s): xiv
    Request permission for commercial reuse | PDF file iconPDF (345 KB)
    Freely Available from IEEE
  • list-reviewer

    Publication Year: 2004, Page(s): xv
    Request permission for commercial reuse | PDF file iconPDF (236 KB)
    Freely Available from IEEE
  • Tutorials

    Publication Year: 2004, Page(s):xvi - xviii
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (30 KB)

    Provides an abstract for each of the tutorial presentations and a brief professional biography of each presenter. The complete presentations were not made available for publication as part of the conference proceedings. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Keynote speech

    Publication Year: 2004, Page(s):xix - xx
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (32 KB)

    Provides an abstract of the keynote presentation and a brief professional biography of the presenter. The complete presentation was not made available for publication as part of the conference proceedings. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Invited Talk

    Publication Year: 2004, Page(s): xxi
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (29 KB)

    Because of trends in scaling, in the near future every high performance dice will contain a massive number of defects and process aggravated noise and performance problems. In an attempt to obtain useful yields, designers and test engineers will need to adopt a qualitatively different approach to their work. They will need to learn, enhance and deploy techniques such as fault- and defect-tolerance... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • TTTC Introduction

    Publication Year: 2004, Page(s):xxii - xxiv
    Request permission for commercial reuse | PDF file iconPDF (189 KB)
    Freely Available from IEEE
  • Call for Papers of ATS’05

    Publication Year: 2004, Page(s): xxv
    Request permission for commercial reuse | PDF file iconPDF (86 KB)
    Freely Available from IEEE
  • TTEP Introduction

    Publication Year: 2004, Page(s): xxvi
    Request permission for commercial reuse | PDF file iconPDF (135 KB)
    Freely Available from IEEE
  • Multi-frequency test access mechanism design for modular SOC testing

    Publication Year: 2004, Page(s):2 - 7
    Cited by:  Papers (16)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (160 KB) | HTML iconHTML

    This paper investigates the applicability of multi-frequency test access mechanism (TAM) design for reducing the system-on-a-chip (SOC) test application time. Based on the bandwidth matching concept the proposed algorithms explore a larger solution space, which, as shown by experimental data, can lead to improved test application time. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Rapid and energy-efficient testing for embedded cores

    Publication Year: 2004, Page(s):8 - 13
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (152 KB) | HTML iconHTML

    Conventional serial connection of internal scan chains brings the power and time penalty. A parallel core wrapper design (pCWD) approach is presented in this paper for reducing test power and test application time. The pCWD utilizes overlapping scan slices to reduce the number of scan slices loading. Experimental results on d695 of ITC2002 benchmark demonstrated that, about 2× shift time and... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Constructing transparency paths for IP cores using greedy searching strategy

    Publication Year: 2004, Page(s):14 - 19
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (200 KB) | HTML iconHTML

    In this paper, a transparency paths constructing approach based on the gate-level netlist of cores is proposed. It searches the potential transparency paths using greedy searching strategy with FB-numbers as its heuristic information, and solves constraints and inconsistency by inserting basic cells, multiplexers and controlling gates. With these transparency paths, IP cores can transfer one test ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Adding testability to an asynchronous interconnect for GALS SoC

    Publication Year: 2004, Page(s):20 - 23
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (93 KB) | HTML iconHTML

    Asynchronous circuits offer great potential for solving the interconnect problems faced by system-on-chip designers, but their adoption has been held back by a lack of methodology and support for fabrication testing of such circuits. This paper addresses this problem using a partial scan approach which achieves a test coverage of 99.5% on the CHAIN network-on-chip interconnect fabric which is used... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Test power reduction with multiple capture orders

    Publication Year: 2004, Page(s):26 - 31
    Cited by:  Papers (29)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (160 KB) | HTML iconHTML

    This paper proposes a method to reduce the excess power dissipation during scan testing. The proposed method divides a scan chain into a number of sub-chains, and enables only one sub-chain at a time for both the scan and capture operations. To efficiently deal with the data dependence problem during the capture cycles, we develop a multiple-capture-orders method to guarantee the full scan fault c... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Power-constrained DFT algorithms for non-scan BIST-able RTL data paths

    Publication Year: 2004, Page(s):32 - 39
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (144 KB) | HTML iconHTML

    This paper proposes two power-constrained test synthesis schemes and scheduling algorithms, under non-scan BIST, for RTL data paths. The first scheme uses boundary non-scan BIST, and can achieve a low hardware overhead. The second scheme uses generic non-scan BIST, and can offer some tradeoffs between hardware overhead, test application time and power dissipation. A designer can easily select an a... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Low power BIST with smoother and scan-chain reorder

    Publication Year: 2004, Page(s):40 - 45
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (168 KB) | HTML iconHTML

    In this paper, we propose a low-power testing methodology for the scan-based BIST. A smoother is included in the test pattern generator (TPG) to reduce average power consumption during scan testing, while a group-based greedy algorithm is employed for the scan-chain reorder in order to improve the fault coverage. The reordering algorithm is very efficient in terms of computation time, and the rout... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Techniques for finding Xs in test sequences for sequential circuits and applications to test length/power reduction

    Publication Year: 2004, Page(s):46 - 49
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (216 KB) | HTML iconHTML

    In this paper, we propose techniques for finding Xs in test sequences for sequential circuits. Also we show two applications that utilize the obtained test sequences with Xs: reduction of the power during test and test compaction. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A time domain built-in self-test methodology for SNDR and ENOB tests of analog-to-digital converters

    Publication Year: 2004, Page(s):52 - 57
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB) | HTML iconHTML

    In this paper, a built-in self-test (BIST) methodology used to test the important transmission parameters, signal-to-noise-and-distortion (SNDR) and effective number of bits (ENOB), of analog-to-digital converters (ADCs) is proposed. A sigma-delta modulation based signal generator is presented which can concurrently produce high frequency analog sinusoidal test stimuli and digital sinusoidal refer... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A new BIST scheme based on a summing-into-timing-signal principle with self calibration for the DAC

    Publication Year: 2004, Page(s):58 - 61
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (224 KB) | HTML iconHTML

    In this paper, we propose a BIST scheme for the digital-to-analog converter (DAC). For the scheme, an analog summer is employed and the tested signal is transformed into a timing signal for a more precise measurement. Also, a calibration circuit is added to calibrate analog imperfection to increase accuracy of the BIST circuit. An 8-bit DAC BIST circuit is designed for demonstration. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A ΣΔ modulation based analog BIST system with a wide bandwidth fifth-order analog response extractor for diagnosis purpose

    Publication Year: 2004, Page(s):62 - 67
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1720 KB) | HTML iconHTML

    A wide bandwidth Σ-Δ modulation based analog built-in self-test (BIST) system that can diagnose the prototype is presented. It consists of a low-cost design-for-testability (DJT) switched-capacitor filter as the circuit under test (CUT) and a wide bandwidth analog response extractor (ARE) to digitize the analog responses for final DSP analysis. The first stage of the DJT CUT is reconfi... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.