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Device Research Conference, 2004. 62nd DRC. Conference Digest [Includes 'Late News Papers' volume]

Date 21-23 June 2004

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Displaying Results 1 - 25 of 163
  • Novel self-defined field emission transistors with PECVD-grown carbon nano-tubes on silicon substrates

    Publication Year: 2004 , Page(s): 55 - 56 vol.1
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (282 KB) |  | HTML iconHTML  

    We report the fabrication of novel field-emission transistors on silicon substrates using vertically grown carbon nano-tubes. Transistors made here are formed on clusters of carbon nano-tubes and do not need nano-lithography. The main feature of the structure is the vertically grown nano-tubes on a silicon substrate, acting as the cathodes for the field emission phenomenon. The level of emission is controlled mainly by the voltage applied between the laterally-placed gate electrode and the silicon cathode electrode. Microscale lithography can be used to fabricate well-defined arrays of transistors suitable for switching applications. Further characterization of the tubes is underway. View full abstract»

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  • a-Si:H TFT phosphorescent OLED active matrix pixels fabricated on polymeric substrates

    Publication Year: 2004 , Page(s): 59 - 60 vol.1
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (279 KB) |  | HTML iconHTML  

    Organic light emitting diode (OLED) displays fabricated on polymeric substrates would be lightweight, flexible, rugged, and potentially less expensive to manufacture. Several passive matrix OLED displays fabricated on polymeric substrates have been demonstrated. For high information content displays, active-matrix pixel addressing provides improved display performance and reduced power consumption. To date, all active matrix OLED displays have been fabricated on rigid substrates and most used polysilicon thin film transistors (TFTs) as the active elements because they can provide sufficient current at low voltages and acceptable device dimensions. However, improvements in the efficiency of OLEDs allows lower mobility TFTs, such as those based on hydrogenated amorphous silicon (a-Si:H) or even organic semiconductors, to be used as OLED drive devices (M.A. Baldo et al, Appl. Phys. Lett., vol. 75, pp. 4-6, 1999). The lower processing temperatures of a-Si:H and organic TFTs may permit the use of polymeric substrates. In this work, 1 mm2 a-Si:H TFT phosphorescent OLED active matrix pixels and pixel arrays were fabricated on 50 μm thick polyimide substrates. View full abstract»

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  • Study of subthreshold electron mobility behavior in SOI-MESFETs

    Publication Year: 2004 , Page(s): 61 - 62 vol.1
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (225 KB) |  | HTML iconHTML  

    Micropower circuits based on sub-threshold MOSFETs are used in a variety of applications ranging from digital watches to medical implants. Alternate device structures are needed that will satisfy both the low-power and RF requirements and will allow much better operation of, for example, pacemakers. A candidate structure is the SOI-MESFET that is currently being fabricated and theoretically characterized within our Nanostructures Research Group at Arizona State University. Since the mobility is the key factor in determining the device cut-off frequency, it is the purpose of this study to investigate the electron mobility improvement of SOI MESFET when compared to SOI and conventional MOSFET devices. To accomplish this goal, we have utilized our in-house Ensemble Monte Carlo device simulator and performed extensive simulations of similar geometry SOI MOSFETs and Si MESFET channels. View full abstract»

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  • A novel program-erasable capacitor using high-κ AlN dielectric

    Publication Year: 2004 , Page(s): 77 - 78 vol.1
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    We demonstrate, for the first time, a novel high-κ AlN capacitor that can be program-erasable at voltages of ±4 V and that has good retention for 1T1C memory. These features are not shown by Al2O3, or other known single high-κ layer capacitors. Good data retention occurs with a threshold change of only 0.06 after ±4 V P/E for 104s and shows potentially long memory time. View full abstract»

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  • Full-swing pentacene organic thin-film transistor inverter with enhancement-mode driver and depletion-mode load

    Publication Year: 2004 , Page(s): 181 - 182 vol.1
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (260 KB) |  | HTML iconHTML  

    In this paper, we propose a pentacene organic thin-film transistor (OTFT) logic inverter circuit with a depletion mode load OTFT and an enhancement mode driving OTFT. It is confirmed that, with only two OTFTs, the minimum output voltage goes down to 0 V and it improves the noise margin characteristics. We believe that this scheme is a first but significant step for simple and reliable pentacene OTFT logic circuits. View full abstract»

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  • Linearity performance of GaN HEMTs with field plates

    Publication Year: 2004 , Page(s): 35 - 36 vol.1
    Cited by:  Papers (5)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (235 KB) |  | HTML iconHTML  

    Recently, electric field modification with GaN-based high-electron-mobility-transistors (HEMTs) using field plates (FP) has resulted in dramatically enhanced power performance. Power densities up to 32 W/mm at 4 GHz have been demonstrated with power-added-efficiency (PAE) of 55%. When scaled to a large periphery, a total output power of 149 W was obtained at 2 GHz. Modern communication applications also require high linearity for power devices. Here we present the linearity performance of GaN-channel HEMTs with various FP lengths at biases up to 108V. View full abstract»

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  • An organic thin-film transistor with photolithographically patterned top contacts and active layer

    Publication Year: 2004 , Page(s): 83 - 84 vol.1
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (226 KB) |  | HTML iconHTML  

    The organic thin film transistor (OTFT) fabrication process has labored under a constraint related to the source/drain contacts, which can be formed either above or below the active layer, referred to, respectively, as top and bottom contact geometries. The top contact geometry is known to provide better performance, e.g., higher field-effect mobilities, but until now only the bottom contact geometry has been compatible with a high level of integration, since the top contact geometry requires patterning of the source/drain metal on top of the organic semiconductor, which can be strongly degraded by typical solvents, rendering it incompatible with photoresist and developers. In this paper, we describe a simple process for simultaneously patterning OTFT top contacts and active layer by photolithography. This is the first report of OTFTs with photolithographically patterned top contacts. The new process closes the gap between the high performance achievable from single devices and that of highly integrated devices. View full abstract»

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  • Air-stable chemical doping of carbon nanotube transistors [CNFETs]

    Publication Year: 2004 , Page(s): 137 - 138 vol.1
    Cited by:  Papers (5)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (271 KB)  

    In this paper, we have successfully demonstrated, for the first time, air-stable chemical p-doping of CNFETs via charge transfer; introduced tunability of the Vth, transformed scaled CNFETs from ambipolar to unipolar, improved Ion by 2-3 orders of magnitude, suppressed minority carrier injection (immunity from drain induced Ioff degradation from intrinsic Schottky barrier CNFET), yielding an excellent Ion/Ioff ratio of 106, and demonstrated excellent DIBL-like behavior. View full abstract»

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  • A new fabrication method for self-aligned nanoscale I-MOS (impact-ionization MOS)

    Publication Year: 2004 , Page(s): 211 - 212 vol.1
    Cited by:  Papers (4)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (253 KB) |  | HTML iconHTML  

    I-MOS uses modulation of the avalanche breakdown voltage of a gated p-i-n structure to control the output current. Because the p-n junction barrier lowering is not the mechanism of current flow control in the device, it can reduce the subthreshold swing to less than 60 mV/dec at room temperature. However, there are two main obstacles to scale the I-MOS down to nanoscale regime: 1) the source and drain are made up of different types of dopants; 2) the i-region, which is not overlapped by the gate, lies between channel and source. Therefore, in the conventional I-MOS process, the gate, the source and the drain cannot be self-aligned. In this paper, a 130 nm n-channel I-MOS was fabricated for the first time using a novel self-aligned fabrication method. It showed normal transistor operation with dramatically small subthreshold swing (7.2 mV/dec) at room temperature. In addition, to make the I-MOS more practical, we also proposed a novel biasing scheme based on the device physics. View full abstract»

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  • Electrical properties of p- and n-type silicon nanowires

    Publication Year: 2004 , Page(s): 23 - 24 vol.1
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (279 KB) |  | HTML iconHTML  

    There has been considerable interest in bottom-up integration of semiconductor nanowires for their application in future logic, memory, and sensor circuits. The ability to integrate field effect devices with p- and n-type conduction channels is a challenge that must be overcome to fabricate complementary logic circuits using such technologies. In this talk, we present the results of four-point resistivity and gate-dependent conductance measurements taken on unintentionally-doped, p-type, and n-type silicon nanowires (SiNWs). These results emphasize that future efforts must address the source of the high p-type background doping concentration in vapor-liquid-solid grown SiNWs to facilitate improvements in the properties of n-channel devices. View full abstract»

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  • Influence of the heterostructure design on noise figure of AlGaN/GaN HEMTs

    Publication Year: 2004 , Page(s): 43 - 44 vol.1
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (233 KB) |  | HTML iconHTML  

    In this work, we cover four topics. Three studies are presented on the effect of different epilayer structures on the noise figure of AlGaN/GaN HEMTs in the 4-12 GHz frequency range. The material studies include varying aluminum composition in the barrier, sapphire vs. SiC substrates, and, for the first time, the influence of a thin AlN layer on the noise parameters; all three against frequency and drain current. In addition is a comparison of two equivalent circuit models at 5 GHz. View full abstract»

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  • Direct measurements of the AC performance of carbon nanotube field effect transistors

    Publication Year: 2004 , Page(s): 53 - 54 vol.1
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (226 KB) |  | HTML iconHTML  

    Carbon nanotube field-effect transistors are expected to operate at very high frequencies, possibly in the THz regime, making them attractive for future nanoelectronics technologies. However, due to formidable measurement difficulties, this performance has not yet been demonstrated. This paper reports: 1) the first direct observation of CNFETs operating at several hundred MHz; and 2) illustrates how to extend direct frequency response measurements to the GHz regime. View full abstract»

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  • 4-terminal FinFETs with high threshold voltage controllability

    Publication Year: 2004 , Page(s): 207 - 208 vol.1
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (267 KB) |  | HTML iconHTML  

    For future ultra-low power circuit designs, flexible Vth control will inevitably be required. To meet this requirement, four-terminal (4-T) DG MOSFETs are promising, thanks to the static and/or dynamic Vth controllability by one of the double gates. Recently, we demonstrated independent double gate FinFETs, fabricated by using orientation-dependent wet etching. This method has great advantages in forming precise Si-fins with an atomically flat channel surface. In this paper, we present the successful fabrication of the ultra-thin Si-fins by wet etching, and the fine separated double gates. We show the excellent Vth controllability of the fabricated 4-T FinFETs by reducing the Si-fin thickness (TSi) down to 13 nm. We also discuss the TSi dependence of the Vth tunable range on the TSi. View full abstract»

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  • Characteristics of high-performance 1.0 μm and 1.3 μm quantum dot lasers: impact of p-doping and tunnel injection

    Publication Year: 2004 , Page(s): 156 - 157 vol.1
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (244 KB) |  | HTML iconHTML  

    There is a need to understand the performance limitations and the role of special techniques to enhance quantum dot (QD) laser performance. In this context, we have examined the role of p-doping in the dots and tunnel injection of electrons into the active dots in the lasers. Utilizing these techniques, we demonstrate QD lasers with zero temperature dependence of the threshold current (T0=∞) and the output slope efficiency and small signal modulation bandwidth ≅25 GHz. It is apparent that an optimal level of p-doping, combined with tunnel injection, will lead to lasers with high modulation bandwidth, zero chirp and very high T0. These results are presented and discussed. View full abstract»

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  • Low noise GaAs-based avalanche photodiodes for long wavelength applications

    Publication Year: 2004 , Page(s): 79 - 80 vol.1
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    Currently available avalanche photodiodes (APDs) for use in telecommunication systems operating at 1.3/1.55 μm utilize InP and InGaAs as the multiplication and absorption medium respectively. The excess noise performance of the InP avalanching region is relatively poor, and is limited by the hole to electron ionization coefficient ratio (β/α). We have recently reported that Al0.8Ga0.2As may be a suitable material for the multiplication region in APDs due to its large α/β ratio in bulk structures (B.K. Ng et al, IEEE Photon. Technol. Lett., vol. 14, p. 522, 2002), which results in a very low avalanche excess noise. In this work, we extend our previous study by investigating the excess noise characteristics in both bulk and sub-micron AlxGa1-xAs diodes as a function of x. Our results here suggest that long wavelength GaAs-based APDs of superior noise characteristics than InP-based APDs can now be realized. View full abstract»

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  • Nano-scale MOSFETs with programmable virtual source/drain

    Publication Year: 2004 , Page(s): 213 - 214 vol.1
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (275 KB) |  | HTML iconHTML  

    In this work, we fabricated twin silicon-oxide-nitride-oxide-silicon (SONOS) memory (TSM) cell transistors, based on the 90 nm non-volatile memory technology and showed the implementation of programmable threshold voltage (Vth) MOSFETs in the nano-scale regime. It was clearly observed that the transistor has high Ion/Ioff ratio (>106) and small drain leakage (∼10 pA) in the 30 nm regime. From the experimental result from fabricated devices, it can be deduced that the TSM transistor has various MOSFET applications due to charged states in the nitride. To evaluate the various MOSFET applications of the TSM transistor in the nano-scale regime, the simulation of a 30 nm-long gate TSM transistor was carried out on the 2D ATLAS, including tunneling and impact ionization models. It is concluded that the proposed TSM MOSFET structure promises a well-controlled short channel effect and high Ion/Ioff characteristics. View full abstract»

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  • Planar device isolation for InP based DHBTs

    Publication Year: 2004 , Page(s): 71 - 72 vol.1
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (247 KB) |  | HTML iconHTML  

    Device isolation of InP based HBTs in the mesa technology, is done by etching down to the substrate; this process suffers from lack of planarity and does not lend itself well to high levels of integration. We report on two techniques for planar isolation of InP based HBTs using selective implantation. The first method involves Fe implantation to isolate the InP collector-subcollector layers. In the second approach, we have utilized selective Si implantation in SI InP to form an isolated, N++ subcollector. View full abstract»

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  • Fabrication of complimentary single-electron inverter in single-wall carbon nanotubes

    Publication Year: 2004 , Page(s): 57 - 58 vol.1
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (217 KB) |  | HTML iconHTML  

    Single-electron devices (SEDs) based on Coulomb blockade (CB) effects have prominent features in terms of ultra-low power consumption and miniaturization to a molecular scale. The performance of the device gets better as the dot size gets small because they rely on the classical CB effect. The single-wall carbon nanotube (SWNT) is attractive material as a building block of SEDs because of the extremely small diameter of a few nanometers. In this paper, we report on the fabrication of the complimentary single-electron inverter an elemental device for the single electron logic (J.R. Tucker, J. Appl. Phys. vol. 72, p. 4399, 1992), and show the electrical performance in the temperature range from 1.5 K to 10 K. View full abstract»

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  • Scaling issues of n-channel vertical tunnel FET with δp+ SiGe layer

    Publication Year: 2004 , Page(s): 215 - 216 vol.1
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (246 KB) |  | HTML iconHTML  

    The performance of a n-channel vertical tunnel field-effect transistor is shown to improve significantly by bandgap engineering at the tunneling junction. The bandgap modulation is achieved by inserting a heavily doped 3 nm delta SiGe layer at the p-source end. Since the bandgap at the tunneling junction determines the tunneling barrier height, having a SiGe delta layer results in lowering it. Thereby, increasing the tunneling probability under similar bias conditions. We show that controlling the Ge mole fraction, x, in SiGe, gives an additional parameter for control of device performance. Device on-current, Ion, and threshold voltage, VT, are seen to improve considerably. However, as the device is scaled down, the tunneling probability increases significantly even for VGS=0 V as x is increased. Thereby, leading to large increase in tunneling leakage current. Optimization of the device performance can then be done by appropriate choice of x with gate oxide thickness, tox, according to technology requirements. View full abstract»

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  • Polar heterostructure for multi-function devices: theoretical studies

    Publication Year: 2004 , Page(s): 103 - 104 vol.1
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (219 KB) |  | HTML iconHTML  

    It is well known that polar oxides such as BaTiO3 and LiNbO3 have extremely large piezoelectric and pyroelectric effects which make them highly suitable for sensor application. Semiconductors on the other hand have poor piezoelectric and pyroelectric effects but have their abilities to show large change in conductivity with small bias. In this paper we examine the potential of devices based on heterostructures made from highly polar materials and semiconductors. Such functional devices have superior sensor properties as well as transistor properties. The basis device examined is based on the use of a thin oxide with high piezoelectric coefficients or pyroelectric coefficients under the gate region. Channel charge and current are directly controlled by gate voltage (normal FET), temperature (thermal sensor), or stress (stress sensor). We examine the performance of three classes of heterostructures that form the basis of important semiconductor technologies: (i) Si/SiO2/BaTiO3 heterostructure junctions that would be an important breakthrough for silicon sensor technology; (ii) GaN/AlN/BaTiO3 heterostructure junctions that would be important especially in high temperature sensor application; and (iii) GaAs/AlGaAs/BaTiO3 heterostructure field effect transistors. View full abstract»

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  • Electronic and magnetic properties of ferromagnetic p-(In,Mn)As/n-InAs heterojunctions [spintronic device applications]

    Publication Year: 2004 , Page(s): 121 - 122 vol.1
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    In this work, (InMn)As/InAs p-n heterojunctions have been fabricated and their electronic and magnetic properties characterized. The (In,Mn)As films, deposited by atmospheric pressure meta organic vapor phase epitaxy, are ferromagnetic at room temperature as determined by magneto-optical Kerr effect (MOKE) measurements and variable-temperature magnetic force microscopy. The J-V characteristics of these junctions were measured over the temperature range of 78 to 300 K. In addition, the magnetic field dependence of the I-V characteristics has been measured. The magnetoresistive properties of these heterojunctions suggest they may be suitable for use in spintronic devices. View full abstract»

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  • High-temperature spin-polarized quantum dot light-emitting diodes

    Publication Year: 2004 , Page(s): 160 - 161 vol.1
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    We believe our demonstration of high-temperature operation in a GaMnAs spin-LED to be an important step in the quest toward room-temperature spin-LED operation. In this paper, we have investigated the properties of Mn-doped InAs quantum dot multilayers grown by LT-MBE. We find that the dilute magnetic quantum dot samples exhibit ferromagnetic behavior at and above room-temperature, possibly resulting from the joint effects of quantum confinement, epitaxial strain, and disorder introduced by the self-organization process. Electron energy loss spectroscopy (EELS) indicates that the Mn atoms incorporate predominantly with the InAs dots. Work is currently underway to incorporate InAs:Mn QDs in the spin-aligner of a spin-LED to demonstrate room-temperature operation; our results are presented. View full abstract»

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  • A high performance photodetector using a novel drift dominated structure in defected materials

    Publication Year: 2004 , Page(s): 4 - 5 vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (214 KB) |  | HTML iconHTML  

    By integrating InP photodiodes with Si, we can take advantage of the low cost and robustness of large Si substrates. However, the major challenge of this strategy is the high density of dislocations in InP grown on Si, due to the 8% lattice mismatch and large difference in thermal expansion coefficient. Large concentrations of dislocations act as recombination centers which greatly deteriorates the performance of the InP photodiodes. We have developed InP photodiodes whose photo-active regions have large electric fields in order to achieve high quantum efficiencies, even with defected material. We use a GaP substrate as the first step since GaP is lattice matched to Si, which could be used as a buffer layer between InP and Si. We compared two different structures: a normal p-i-n structure and a drift dominated structure. View full abstract»

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  • Improved high power thick-GaN-capped AlGaN/GaN HEMTs without surface passivation

    Publication Year: 2004 , Page(s): 39 - 40 vol.1
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (242 KB) |  | HTML iconHTML  

    A record high power density on sapphire without passivation was achieved using an epitaxial approach to dispersion reduction. SiN passivation has been employed to reduce DC-to-RF dispersion of GaN-based HEMTs, but is sensitive to surface and deposition conditions. A proposed epitaxial solution is to grow a thick GaN cap on top of the conventional HEMT to increase the distance between surface and channel, reducing the effect of surface potential fluctuations on device performance. Initial results from a gate-recessed device structure showed that dispersion was reduced greatly without surface passivation. Nevertheless, high gate leakage and low breakdown limited the output power. We investigate the cause of these leakage and breakdown issues, propose solutions, and discuss the results. As a consequence, 8.5 W/mm with a PAE of 57% was achieved at 50 V at 4 GHz from unpassivated HEMTs on sapphire, the highest power density reported. View full abstract»

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  • Hot carrier reliability of HfSiON NMOSFETs with poly and TiN metal gate

    Publication Year: 2004 , Page(s): 99 - 100 vol.1
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (258 KB) |  | HTML iconHTML  

    High-k dielectrics have been proposed to replace SiO2 to reduce gate leakage current. Among reliability concerns of the hafnium based metal oxides (Y.H. Kim et al., Tech. Dig. of IEDM, p. 861, 2002) hot carrier effects may represent one of the major limitations for the high-k gate dielectrics introduction (Q. Lu et al., IRPS, p.429, 2002; A. Kumar, VLSI, p. 152, 2003). However, most of the studies did not take into consideration that the hot carriers-induced degradation might be accompanied by the electron trapping in the bulk of the high-k film (C.D. Young et al., IRW, p. 28, 2003) due to the high density of structural defects in the high-k dielectrics (G. Bersuker et al., Materials Today, vol. 26, Jan. 2004). This bulk electron trapping, which is not observed in the case of SiO2 dielectrics, can significantly affect transistor parameters and, therefore, complicates evaluation of hot carrier degradation properties of the high-k gate stacks. In this paper, we investigate test conditions for the hot carrier stress of the poly and TiN gate NMOSFETs with HfSiON gate dielectric that would more accurately address the above issues. View full abstract»

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