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High Density Microsystem Design and Packaging and Component Failure Analysis, 2004. HDP '04. Proceeding of the Sixth IEEE CPMT Conference on

Date 30 June-3 July 2004

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Displaying Results 1 - 25 of 83
  • Materials and processes issues in fine pitch eutectic solder flip chip interconnection

    Page(s): 213 - 220
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1129 KB) |  | HTML iconHTML  

    New product designs within the electronics packaging industry continue to demand interconnects at microscopic geometry, both at the integrated circuit (IC) and supporting board level, thereby creating numerous manufacturing challenges. Flip chip on board (FCOB) applications are currently being driven by competitive manufacturing costs and the need for higher volume and robust production capabilities. One of today's low cost FCOB solutions has emerged as an extension of the existing infrastructure for surface mount technology (SMT) and combines an under bump metallisation (UBM) with a stencil printing solder bumping process, to generate mechanically robust joint structures with low electrical resistance between chip and board. Although electroless Ni plating of the UBM, and stencil printing for solder paste deposition, have been widely used in commercial industrial applications, there still exists a number of technical issues related to these materials and processes as the joint geometry is further reduced. This paper reports on trials with electroless Ni plating and stencil paste printing and the correlation between process variables in the formation of bumps and the shear strength of such bumps at different geometries. The effect of precise control of the tolerances of squeegees, stencils and wafer fixtures was examined to enable the optimisation of the materials, processes and tooling for reduction of bumping defects. View full abstract»

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  • Prevention of voids during the underfill process

    Page(s): 221 - 223
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (425 KB) |  | HTML iconHTML  

    This paper reports the void control in underfill process. In a flip chip package, there is void free as an important factor which acquires the stable reliability. We investigated the method of controlling void generation by the various technique. Conventionally, although importance was attached to pre-baking of a substrate, pre-heat in front of underfill process was effective. Moreover, the leaving time of before curing from after an application was also one method to control of void generation. We propose that control of void generation is possible by combining some techniques. View full abstract»

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  • Electrical conductive characteristics of ACA bonding: a review of the literature, current challenges and future prospects

    Page(s): 264 - 276
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1421 KB) |  | HTML iconHTML  

    Anisotropic conductive adhesives (ACAs) have been used in fine pitch electronics packaging for over a decade and provide a high density and low temperature bonding method in a range of niche applications. The principal objective of this paper is to provide significant insights into the basic conductive characteristics of ACAs based on a review of previously reported scientific research, and to identify the current challenges and future prospects for this technology. In order to provide a concise, structured overview of this topic, many detailed conductive models, mathematical solutions and research methodologies are presented based on the reviewed literature. These models can partially explain the conductive mechanisms of an ACA particle, but make a number of important simplifying assumptions. However, one model was developed and can be used to explain the conductive mechanism of an ACA particle more successfully. In conclusion, existing computational models, mathematical models and physical models have been used to estimate the resistance of an ACA particle and the particle contact area, and therefore constriction resistance, for a given degree of particle deformation, thereby almost achieving a model for the whole resistance of an ACA joint. The paper will close by identifying other research challenges remaining for this important electronics interconnection technology. View full abstract»

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  • Memory device packaging - from leadframe packages to wafer level packages

    Page(s): 21 - 24
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (598 KB) |  | HTML iconHTML  

    The digital revolution has taken the consumer electronics by a storm in just two-short years. Portable and handheld electronics devices now have insatiable appetite for digital storage. Hence, memory cards in the form of USB Drive (U-drive), compact flash (CF), secured digital (SD), memory stick, and multimedia card (MMC) are now proliferating in the market. Moreover, the volatile memory dynamic random access memory (DRAM) for PC and notebook computing and gaming are also increasing in density and speed. With all these improvement, the memory device packaging technology is also evolving rapidly, from the traditional leadframe packages to smaller chip scale packages (CSP) and wafer level packages (WLP). This paper will cover the four major topics: (1) Review of the DRAM packages and their applications - DRAM packages are used primarily in the fabrication of DIMM modules that are inserted to the motherboards in PC and notebook computers. With newer DRAM technology in double date rate (DDR) and its second generation, DDR2, to be deployed this year, the clock rate is much higher and the number of I/Os increasing. Packages therefore are changing from the leadframe TSOP type 2 to faster CSPs such as fine pitch BGA (FBGA). (2) Review of the flash memory card packages - non-volatile memory flash and SRAM packages are generally smaller and have had lower density of 256Mb and below. But more recently high density (512Mb) and hence larger flash devices are more common. The conventional package TSOP type 1 may become inadequate to meet new performance demands and the form factor for miniaturization. Alternative new packages such as VFBGA CSP are described. (3) Stacking - 3D stacking have now been widely utilized to increase the memory density and saving weight and space. The two main options for stacking - die stack and package stack, each has its own advantages and concerns. The selection criteria and suitable applications for both the DRAM DIMM modules and various flash memory card formats are discussed in detail. (4) Future trends and conclusion - the convergence of packaging technology for the computing and consumer electronics is apparent under the same market and technology drivers - form factor miniaturization, lightweight, low profile, high speed, and high perfor- mance. Packaging for high-density memory devices is moving toward faster and smaller CSP packages, with the technology and processes for wafer level CSP and wafer level 3D stacking emerging in the horizon. View full abstract»

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  • Characterisation of intermetallics and mechanical behaviour in the reaction between SnAgCu and Sn-Pb solder alloys

    Page(s): 52 - 59
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1342 KB) |  | HTML iconHTML  

    Due to the imminent wide-spread introduction of Pb-free solders, materials properties, manufacturing and reliability of solder joints are currently being investigated in the electronics packaging community. The interactions of new Pb-free alloys with other materials are of particular concern in order to understand and thereby enable the optimisation and control of the processes for reliable products. In the transition period from Sn-Pb to Pb-free soldering, existing Sn-Pb products that remain in the market, or with customers, is an issue when they have to be repaired with Pb-free solders. The complete elimination of Pb from the products that are specified in the legislation has to be account for Pb contamination that is inevitable in rework, repair or technology upgrades. As such, a number of technical problems in connection with mixing Sn-Pb with Pb-free alloys exist, including: (1) Uncertainty of the resulting microstructure and its properties; (2) The effect of unknown compositions and structures on the reliability; (3) Critical or tolerable levels of some elements that can be permitted in applications; (4) The relative content of the elements and the formation and morphology of intermetallic phases. In this paper thermodynamic calculations are presented that have studied the multicomponent material behaviour and possible formation of intermetallic precipitates during reactions between Sn-Pb and Sn-Ag-Cu Pb-free alloys. Two Sn-Ag-Cu alloys that are relevant to current industrial interests, namely Sn-3.9Ag-0.6Cu (known as '405 alloy' in Europe and North America), and Sn-3.0Ag-0.5Cu (known as '305' alloy in Asia), were selected to react with different contamination levels of eutectic Sn-37Pb solder. The paper also presents experimental work that has characterized the intermetallics and the mechanical behaviour following reaction of the Pb-free alloys with eutectic SnPb solder. The microstructure and phase identification was studied by optical microscopy and scanning electron microscopy (SEM), with the latter featuring the electron back scattered diffraction (EBSD) technique that offers details of phase morphology and orientation at nanoscales. Nanoindentation, which is suitable for the ultra-fine and complex microstructures in sma- ll volumes, was also used to investigate the micromechanical properties, including hardness, elastic modulus and creep, at both ambient and elevated temperatures. View full abstract»

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  • The improvement on the properties of silver-containing conductive adhesives by the addition of carbon nanotube

    Page(s): 382 - 384
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (386 KB)  

    A sprinkle multiwall-carbon nanotubes, adding into the system of epoxy resin (EP), can bring the resin system to semiconducting state. Adding such kind of carbon nanotubes in the Ag/EP system which the content of conducting particle is below the threshold, can ameliorate its conducting capacity. 0.4wt.% of carbon nanotubes in the 57wt%Ag/EP system, the bulk resistivity reduced from 106Ω.cm to 10-2Q.cm reduced 8 quantity steps. View full abstract»

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  • A novel surface passivation process for CdZnTe detector packaging

    Page(s): 377 - 379
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (401 KB) |  | HTML iconHTML  

    The CdZnTe (CZT) micro-strip detector packaging plays a dominant role in detector performance, which can decrease the noise of the detectors and improve the spectral energy resolution. The surface passivation of CdZnTe detectors is an important step in the device packaging. In this paper, comparison between chemical and physical passivation processes has been made. In particular, a new surface passivation process for CZT has been studied by depositing diamond like carbon (DLC) film with radio frequency plasma chemical vapor deposition (RFPCVD) method. The micro-structural, chemical and electric characteristics of the passivation layers were identified by AFM, AES and micro Raman spectroscopy and ZC36 micro-current testing instrument. The results show that the DLC on the detector has the characteristic diamond peak of the sp3 structure and can prevent the outward diffusions of Cd or Te components from the CZT surface. The inter-strip resistance in a coplanar grid detector by the DLC passivation is about 12GQ with inter-strip distance 25 μrn. Therefore, it could be inferred that DLC seems a more likely candidate for maintaining high long-term performance, especially for technology facilitation of the fabrication of micro-strip detectors. View full abstract»

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  • Multifunctional integrated substrate technology for high density SOP packaging

    Page(s): 83 - 90
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1425 KB) |  | HTML iconHTML  

    Advanced substrates or printed circuit boards (PCBs) are an essential part for building the advanced IC packages (BGA, CSP, flip chip and wafer-level package), MCMs, 3D package, system-in-package (SiP), system-on-package (SOP), and all high density microelectronic systems. As processors and memory move towards nanometer-size features and processor clock speeds increase 60% per year, development of next generation system level substrates technology is required to keep pace both the wiring density and high performance requirements. The packaging research center at Georgia Tech has been developing system-on-package (SOP) technology for future high density, high performance systems. This paper introduces three important aspects for future advanced package substrates or PCBs for high density and high performance systems applications. They are (1) ultra-high density wiring technology with ultra fine circuit traces and microvias, including novel non-conformal stacked vias. The ultra high wiring density substrate is critical for the use of fine pitch, high I/O count, flip chip application and. microsystem miniaturization. (2) Integrations of passive components, and (3) integrations of high speed optical interconnects for chip-to-chip data link. This will be the revolutionary advance in future PCBs. We have developed ultra high density wiring technology by a combination of ultra-fine lines and space of 10 μm or less and stacked microvias. We have developed optically smooth organic surfaces for optical components integration and have demonstrated a 10 Gbps chip-to-chip data rate on PCBs. The future high density, high performance, microsystems can be realized by the combinations of high density wiring technology and optoelectronics integration. Details of this work are the subject of this paper. View full abstract»

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  • Microsystems packaging from milli to microscale to nanoscale

    Page(s): 1 - 7
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (978 KB) |  | HTML iconHTML  

    So called "packaging", in the past, played two roles: (1) provide I/O connections to the semiconductor devices so the IC is tested and ready for board assembly. This is called IC packaging and (2) integrate components into systems to form end product systems such as cell phones, PDAs, Laptops. This is called systems packaging. Both the above IC and systems packaging are accomplished by interconnections or wiring at the package or board level so far. Packaging is currently at milliscale in manufacturing, microscale in development and nanoscale in research. In future, the role of packaging is more than interconnections. The IC devices themselves began to integrate more and more transistors and functions, leading to what the community have been calling SOC or system-on-chip with multiple systems functions in a single chip. This can be called horizontal or 2D integration of IC blocks toward system-level functionality. The community began to realize, however, that such an approach presents design complexity and fundamental limits for computing, and integration limits for wireless systems, over the long run. This led to 3D packaging approaches, often referred to as SIP or system-in-package. Both these are the latest and most leading-edge technologies pushing the IC integration in two and three dimensions. But they both have one major shortcoming. They depend on CMOS processing and hence are limited by what can achieved with CMOS. The SIP and SOC approaches, while providing major opportunities in both miniaturization and integration for advanced portable and desktop electronic products, are limited by CMOS processes. A new concept called SOP or system-on-package being pioneered by Georgia Tech PRC - where the package, and not the board, is the entire system. SOP addresses the shortcomings of both SOC and SIP in two ways: optimize silicon for what it is good for, and the package for what it is best at, by means of IC/package/system co-design, while doing so, SOP optimizes both for cost, performance, miniaturization and reliability. The package, in this concept, therefore overcomes both computing limitations and integration limitations of SOC and SIP. It does this by having global wiring as well as RF and optical component integration in the package level, and not in - the chip. The SOP, therefore, includes embedded digital, RF and optical components and functions built into a highly miniaturized package, module or board for emerging convergent systems of tomorrow. This Moore's Law for systems integration is akin to Moore's Law for ICs pushing component density by a factor of 100 to 10,000 by means of microscale thin film component integration in the short term to nanoscale integration in the long term. View full abstract»

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  • Low distortion cold rolled clad sheets for PWB

    Page(s): 91 - 96
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (442 KB) |  | HTML iconHTML  

    New cladding process has been developed by means of a surface activated bonding (SAB) technique. In this process, surfaces of materials to be bonded are cleaned, activated by Ar ion sputter etching, and rolled with low distortion at room temperature in vacuum. This is available for cladding not only between heterogeneous metals but also between metal and polymer film. The clad sheets manufactured by this process have advantages over conventional clad sheets. For instance, they have a clean and flat interface without alloy layer. In addition, thickness of each layer is constant, even thin metal foil can be bonded with the metal foil or polymer film. In such respects the clad sheets with those features have been applied to PWB. Metal/metal clad sheets are suitable for selective wet etching working. The developed Cu/Ni/Cu 3-layer clad material makes it possible to form the 3D structure, containing the bumps and circuits, only by means of wet etching process. Metal/polymer clad materials composed of very thin rolled Cu foil and LCP Liquid Crystalline Polymer) film, are superior to the conventional materials from the point of fine etching property and high frequency property because of their smooth bonding interface. This paper reports the features of clad sheets manufactured by SAB and their applications to PWB. View full abstract»

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  • A BS-BIST test circuit design for VAD-SOC

    Page(s): 385 - 389
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (442 KB) |  | HTML iconHTML  

    Along with the more complicated integrated circuit system and the emergence of intelligent properties (IP-based) system on a chip (SOC) system, the test of IC system becomes more difficult and faces new challenge. In this paper we design a BS-BIST test circuit after studying built in self test (BIST) and boundary-scan (BS) technique respectively. At the base of increasing little of cost in circuit complexity, it combines video add data (VAD) SOC to overcome many problems in the test of IP-based SOC system. View full abstract»

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  • Studies of microstructure characteristics and evolutions at the bond interface in bonding technology

    Page(s): 316 - 321
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    To enhance thermosonic bond development, an improved understanding is needed of the processes taking place at the bond interface. In this paper, lift-off and section characteristics at the interface of thermosonic bond were observed by using scanning electron microscope with EDS-test. It is obvious that the peeling underdeveloped bonds simulate a torus (or doughnut) with an unbonded central region and ridged peripheral region is bonded hardly. Bond strength is located between the severely ridged periphery and the non-adhering central area of the bond. For constant force and time, the ridged area of the bond pattern increases when more power is applied. For constant force and power, the ridged location of the bonded region moves closer to the bond center with time. Au-Al and Au-Ag microstructures were identified by EDS-tests, and 'Kirkendall' diffusibility in Au-Ag interface and inter-metallic compounds in Au-Al interface were confirmed. And these would be helpful for further research about thermosonic bonding. View full abstract»

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  • Realization of electron image stabilization based on TMS320C6416

    Page(s): 359 - 362
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (371 KB) |  | HTML iconHTML  

    To absolve image blur of high speed camera, fixed-point DSP TMS320C6416 and Wiener filtering algorithm are adopted. Degeneration model for moving blur is researched; the principle of Wiener filtering is explained: how to complete FFT of 32bit and how to exert DMA function of DSP to enhance processing speed; ringing effect and edge effect are analyzed, and the test results are presented. View full abstract»

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  • On the formation of Cu-Ni-Sn ternary intermetallics in SMT solder joints

    Page(s): 66 - 69
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1280 KB) |  | HTML iconHTML  

    Formation of intermetallics for SnPb eutectic solder in a sandwich structure with one side copper pad/HASL finish and other side copper pad/NiAu finish was studied. The experimental results strongly indicate that the interface IMCs depends not only on the solder material and the metallization it reacted to but also on the metallization on the other side of the soldering interface. Copper can diffuse fast across the molten solder to react with nickel layer on the other side to form (CuNiSn) ternary alloy. Depending on the quantity of diffused copper, different types of IMCs are formed. View full abstract»

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  • Prediction of stand-off height and 3D shape of solder joint in fiber attachment soldering

    Page(s): 151 - 153
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (368 KB) |  | HTML iconHTML  

    The 3D shape of solder joint in fiber attachment soldering was predicted by employing finite element method (FEM). Based on the minimum potential energy theorem and data from shape simulation, the influence of material and manufacturing parameters on the stand-off height (SOH) between optical fiber and substrate was analyzed in detail. The results showed that the z-axis alignment of optical fiber can be controlled by solder volume and solder joint design. View full abstract»

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  • Reliability predictions for high density packaging

    Page(s): 121 - 127
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1069 KB) |  | HTML iconHTML  

    Predicting the reliability of newly designed products, before manufacture, is obviously highly desirable for many organisations. Understanding the impact of various design variables on reliability allows companies to optimise expenditure and release a package in minimum time. Reliability predictions originated in the early years of the electronics industry. These predictions were based on historical field data which has evolved into industrial databases and specifications such as the famous MIL-HDBK-217 standard, plus numerous others. Unfortunately the accuracy of such techniques is highly questionable especially for newly designed packages. This paper discusses the use of modelling to predict the reliability of high density flip-chip and BGA components. A number of design parameters are investigated at the assembly stage, during testing, and in-service. View full abstract»

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  • On-chip high-Q solenoid inductors embedded in WL-CSP

    Page(s): 105 - 108
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (557 KB) |  | HTML iconHTML  

    On-chip Cu solenoid inductors on Si substrate with thick resin layer have been fabricated. These inductors were fabricated by dual Cu electroplating layers and separated more than 10 μm from Si substrate by thick resin layer. The self-resonance frequency of 17.7 and higher than 20 GHz with peak-Q of 18.5 and 24.2 were obtained for a 5 turn solenoid inductor in the resistivity of 4, 1k Ωcm, respectively. This technology realizes that high performance inductors are embedded in wafer-level chip-scale packages. View full abstract»

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  • Design and implementation of RS(255,223) decoder on FPGA

    Page(s): 390 - 393
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (396 KB) |  | HTML iconHTML  

    This paper proposes a RS(255,223) decoder for applications that require high-speed data communication and reliability. The proposed architecture employs a modified Euclidean algorithm, the Chien search and Forney's algorithm using parallel processing technology. The complexity of this decoder is about 130,000 gates; the total latency is 560 cycles; and the throughput is 180Mbps under 20MHz. Comparing with similar designs, this design has smaller latency, moderate area, and high throughput rate. View full abstract»

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  • Simulation on electroosmotic flow through a rectangular microchannel with different aspect ratios

    Page(s): 341 - 345
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (422 KB) |  | HTML iconHTML  

    A numerical study of electroosmotic flow through microchannels has been completed in this paper. A 2D Poisson-Boltzmann equation and a 2D Navier-Stokes equation governing the electric double layer (EDL) field and velocity field in the cross section of rectangular microchannels are numerically solved by employing SIMPLE method without the use of Debye-Huckel approximation. The volumetric flowrate with different aspect ratios for a fixed hydraulic diameter are compared. The comparison of the numerical simulation results show that significant influences of the channel cross-section geometry (i.e. the aspect ratio) on flow field. The objective of this paper is to provide the basis for electroosmotic pumping. View full abstract»

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  • Integrated MEMS technology

    Page(s): 177 - 180
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (484 KB) |  | HTML iconHTML  

    For developing the integrated low-loss MEMS, the number of the optical-electrical micro-transducers must be arrayed to the optimum for controlling, high photoelectric conversion efficiency is also necessary, then the high rate data source will arrive at its destination with high signal-to-noise ratio (SNR), the optical micro-units (in micro-arrays) can be located to the maximum. To guarantee the reliability and the stability of running, the package technology is critical. The vector adaptive finding technology (VAF) with the segmented stage packaging technology (SSP) can satisfy the requirements. The extended vector adaptive finding (EVAF) can supply wireless services well, the simple vector adaptive finding (SVAF) is low-cost to implement. View full abstract»

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  • Relationship between curing conditions and interconnect properties of flexible printed circuit/glass substrate joints using anisotropic conductive films

    Page(s): 248 - 253
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (561 KB) |  | HTML iconHTML  

    This paper investigates the mechanical and electrical properties of anisotropic conductive film (ACF) interconnects between flexible printed circuits (FPC) and glass substrates prepared under a variety of bonding conditions. The curing behavior of the ACF was analyzed by the time-temperature-superposition (TTS) method. TTS analysis using the superposition principle has been suggested as a suitable technique for analyzing the curing kinetics during the bonding process, although an appropriate shift factor needs to be established. However, the glass transition temperature of the cured ACF and the peel strength of the ACF joints cannot be determined uniquely from the degree of conversion. Therefore, the polymer structure of the adhesive binder obtained by the bonding process is inferred as being different depending on the bonding temperature, even for the same degree of conversion. The quality of the electrical connection of the joints after the bonding process is rarely affected by differences in the polymer structure. View full abstract»

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  • Development of ultrasonic flip chip bonding for flexible printed circuit

    Page(s): 307 - 310
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1047 KB) |  | HTML iconHTML  

    Small form factor and high density printed circuit boards (PCB) have been already realized by flip chip (FC) bonding technology. However, the requirement for finer pitch PCB is still increasing with shrinkage of die and wiring. Therefore, conventional flip chip bonding technology will not provide sufficient capability or productivity to meet future demands. The authors have focused on flip chip bonding method utilizing ultrasonic vibration. Flip chip modules using flexible printed circuit (FPC) are strongly required for such as mobile phone applications. For that purpose, we have investigated to assemble semiconductor devices with FPCs applying this method, particularly for large size die with multiple pads. In this report, we have evaluated relationship between bonding parameters and reliability using several kinds of copper clad laminate (CCL) with different plating conditions. We show the correlation between formation of microscopic metallic bond and actual chip on flex (COF) module performance. As a result, we succeed to realize 35μm pad pitch COF module. View full abstract»

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  • A study of threshold variation compensated inverter-comparator for pulse circuits

    Page(s): 363 - 366
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (407 KB) |  | HTML iconHTML  

    This paper studies an inverter-comparator and presents an improved scheme of threshold compensation to enhance the performance of avoiding power supply noise. The inverter can greatly predigest the structure of circuit and save the layout area and depress the power dissipation, so it can be applied in the equipment of moving communications better. It is already proved by simulation with Spectre based on CSMC 0.6μm CMOS technical library. There it will be verified with 555 timer and monostable trigger. View full abstract»

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  • Computer-based data acquisition for wire bonding studies

    Page(s): 227 - 230
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (708 KB) |  | HTML iconHTML  

    Ultrasonic bonding is the most commonly used interconnect technology in microelectronics manufacturing. This paper presents a data acquisition solution that enables reliable transfer of the data from digital storage oscilloscope to PC. Realizations of RS232 serial communications are discussed and accomplished. The measurement shows that the system works well for further processing in bonding studies. View full abstract»

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  • Packaging effects on the performances of MEMS for high-G accelerometer: frequency-domain and time-domain analyses

    Page(s): 282 - 289
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1013 KB) |  | HTML iconHTML  

    In this work, the finite element simulations have been applied in frequency-domain and time-domain analyses for a packaged MEMS accelerometer used in high-G environments. The results from simulations of packaging effects on the performances of MEMS for high-G accelerometer show that the Young's moduli of seal adhesive has important influences on the mode shapes of the packaged accelerometer and a small Young's modulus will bring in strong distortion of output signal of accelerometer. As the Young's moduli increased, the waveform of accelerometer output signal became better after digital filtering. The seal adhesive with Young's modulus like molding compound in IC packaging would not induce significant problems in signal distortion. The frequency and averaged amplitude of output signal of the packaged accelerometer were not affected by Young's modulus of seal material. The accelerometer output was linearly dependent on the input of acceleration impulse and the response was very well when the input of the acceleration amplitudes changed. View full abstract»

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