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Advanced System Integrated Circuits 2004. Proceedings of 2004 IEEE Asia-Pacific Conference on

Date 4-5 Aug. 2004

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Displaying Results 1 - 25 of 159
  • Independently controllable 3rd- and 5th-order analog predistortion linearizer for RF power amplifier in GSM

    Page(s): 146 - 149
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (325 KB) |  | HTML iconHTML  

    An individually controllable 3rd-order intermodulation (IM3) and 5th-order intermodulation (IM5) predistortion linearizer for RF power amplifiers of band-type global system of mobile (GSM) repeaters is proposed. In order to effectively improve the linearity of RF power amplifiers, the IM3 and the IM5 powers are canceled by the predistortion circuit, which independently controls amplitude and phase of the IM3 and the IM5. The fabricated predistorter linearizes the power amplifier at 940 MHz. The IMD3 and the IMD5 suppressions of 30 dB and 26 dB, respectively, are achieved with an average power of 33 dBm for the GSM repeaters. View full abstract»

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  • An efficient all-digital built-in self-test for chargepump PLL

    Page(s): 80 - 83
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (415 KB) |  | HTML iconHTML  

    Analog and mixed-signal testing is becoming an important issue that affects both the time-to-market and product cost of many SoCs. In order to provide an efficient test method for the PLL which is a mixed-signal circuit widely used in most of SoCs, a novel BIST method is developed. It uses the change of phase differences generated by selectively alternating the feedback frequency. This BIST can be easily implemented with several counters and combinational logic gates. The simulation results show higher fault coverage than that of previous test methods. Thus it provides an efficient structural test, which is suitable for a production test in terms of an area overhead, a test accessibility, and test time. View full abstract»

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  • Fast Fourier transform processor based on low-power and area-efficient algorithm

    Page(s): 198 - 201
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (346 KB) |  | HTML iconHTML  

    This paper proposes a new efficient FFT architecture with structured pipeline for OFDM systems, based on radix-24 algorithm. The pipeline architecture with the new algorithm has the same number of multipliers as that of the radix-22 algorithm. However, the multiplier complexity could be reduced by an amount of above 30% by means of replacing a half of programmable multipliers with the newly proposed constant multipliers. A newly proposed complex constant multiplier can enhance the area/power efficiency of the design. From synthesis simulations of a standard 0.35μm CMOS process, it achieved above 60% area reduction when compared with the conventional programmable multiplier. View full abstract»

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  • A low-power Booth multiplier using novel data partition method

    Page(s): 54 - 57
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (376 KB) |  | HTML iconHTML  

    The Booth algorithm has a characteristic that the Booth algorithm produces the Booth encoded products with a value of zero when input data stream have sequentially equal values. Therefore, partial products have greater chances of being zero when the one with a smaller dynamic range of two inputs is used as a multiplier. To minimize greater switching activities of partial products, we propose a novel multiplication algorithm and its associated architecture. The proposed algorithm divides a multiplication expression into four multiplication expressions, and each multiplication is computed independently. Finally, the results of each multiplication are added. Therefore, the exchanging rate of two input data calculations can be higher during multiplication. Implementation results show the proposed multiplier can maximally save about 20% in terms of power dissipation than the previous Booth multiplier. View full abstract»

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  • An 8b 220 MS/s 0.25 μm CMOS pipeline ADC with on-chip RC-filter based voltage references

    Page(s): 90 - 93
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (419 KB) |  | HTML iconHTML  

    This work proposes an 8b 220 MS/s 230 mW 3-stage pipeline CMOS ADC with on-chip filters for temperature- and power supply-insensitive voltage references. The proposed RC low-pass filters reduce reference settling time at heavy R & C loads and improve switching noise performance without conventional off-chip bypass capacitors. The prototype ADC fabricated in a 0.25 μm CMOS occupies the active die area of 2.25 mm2 and shows the measured DNL and INL of maximum 0.43 LSB and 0.82 LSB, respectively. The ADC maintains the SNDR of 43 dB and 41 dB up to the 110 MHz input at 200 MS/s and 220 MS/s, respectively, while the SNDR at the 500 MHz input is degraded as much as only 3 dB than the SNDR at the 110 MHz input. View full abstract»

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  • A parallel flop synchronizer for bridging asynchronous clock domains

    Page(s): 184 - 187
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (384 KB) |  | HTML iconHTML  

    Inter-domain communications on a chip require a synchronizer to resolve the timing problems between an input and a clock of a destination. This paper presents a parallel flop synchronizer and its interface circuit for transferring asynchronous data between clock domains. The proposed scheme uses a bank of independent two-flops in parallel and supports a two-phase handshake protocol. Compared to the conventional two-flop synchronizer, performance analysis shows that the proposed synchronization can reduce latency up to one and a half of clock cycles while retaining its safety to a tolerable level. View full abstract»

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  • A low-power wide-bandwidth fully differential operational amplifier with current re-using feedforward frequency compensation

    Page(s): 32 - 35
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (292 KB) |  | HTML iconHTML  

    A fully differential operational amplifier (op-amp) is described that simultaneously achieves low power consumption and wide bandwidth by employing current-reusing feedforward compensation scheme. In contrast to the conventional feedfoward frequency compensation, the newly developed scheme re-uses the bias current of the second stage of op-amp and therefore the power consumption is minimized. The op-amp designed in a 0.25μm CMOS technology achieves 77dB DC gain, 870MHz unity gain frequency and 56° phase margin for 1pF load capacitance. The op-amp draws 1.8mA from a 2.5V supply. View full abstract»

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  • Multiplierless multirate decimator/interpolator module generator

    Page(s): 58 - 61
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (370 KB) |  | HTML iconHTML  

    A module generator, which can automate the process of designing high-speed low-complexity multistage multirate decimator/interpolator, is presented. The generator exploit architectural symmetries in linear phase filters and multistage multirate interpolated FIR filter design methodology for low complexity. In addition, the polyphase representation is used to decompose the filter into subfilters. The resulting filters utilize canonic signed digit (CSD) multipliers, a transposed direct form structure, and carry-save addition for high speed. A filter design example with TSMC 0.25 μm standard cell for 64-QAM baseband demodulator shows that the area is reduced by 39% for low-complexity applications. Moreover, for high-speed application, the chip can operate at 714MHz. Finally, a designed decimator which is used in the CDMA cellular shows that the area is reduced by 70% as compared with conventional approach. View full abstract»

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  • A high resolution, wide range digital impedance controller for high-speed SRAM interface

    Page(s): 120 - 123
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (376 KB) |  | HTML iconHTML  

    This paper describes a digital impedance controller (DIC) for high-speed signal interface. The proposed DIC provides the wide range impedance control covering from 23Ω to 140Ω with 3.29% maximum quantization error. The maximum quantization error of the proposed DIC is +2.26% with RQ ranging from 23Ω to 53Ω the same range covered by conventional scheme. High-resolution and wide range impedance control are implemented by using automatic gate voltage optimization. The data input valid window is 623ps at 0.75±200mV and maximum eye open is 641mV meaning about 10% improvement at 1.5Gbps/pin DDR3 SRAM interface. View full abstract»

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  • An 8-bit 250MSPS CMOS pipelined ADC using open-loop architecture

    Page(s): 94 - 97
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (309 KB) |  | HTML iconHTML  

    This paper describes some design techniques for high speed and low power pipelined 8-bit 250MSPS ADC. To perform high-speed operation with relatively low power consumption, open loop architecture is adopted, while closed loop architecture (with MDAC) is used in conventional pipeline ADC. To reduce the power consumption and the die area, the number of amplifiers in each stage are optimized and reduced with proposed zero-crossing point generation method. At 250MHz sampling rate, measurement results show that the power consumption is 150mW including digital logic with 1.8V power supply. And the proposed ADC achieves 38dB (SNDR) with input frequency up to 125-MHz and input range of 1.2Vpp (Differential). The ADC is designed using a 0.18 μm 6-Metal 1-Poly CMOS process and occupies an area of 900 μm × 500 μm. View full abstract»

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  • A 1.8V 2.5-5.2 GHz CMOS dual-input two-stage ring VCO

    Page(s): 134 - 137
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (366 KB) |  | HTML iconHTML  

    A 1.8V 2.5-to-5.2 GHz dual-input two-stage CMOS voltage-controlled ring oscillator (VCO) is presented. A novel delay cell used for the two-stage ring VCO is proposed to achieve low power dissipation and better phase noise performance. The delay cell adopts both inductive-peaking and shunt-shunt feedback circuit techniques to obtain high gain and wide. Implemented in a 0.18 μm CMOS technology using 1.8V supply voltage, the VCO has a wide operating frequency range from 2.5GHz to 5.2GHz with coarse-tune VCO gain of 4.75GHz/V and fine-tune VCO gain of 80MHz/V. At 3.6GHz, the phase noise of the VCO is -90.1dBc/Hz at 1MHz frequency offset with low power consumption of 17mW. Because of the two-stage ring topology, the VCO can provide quadrature outputs. The total chip area is 0.4mm × 0.6mm. View full abstract»

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  • Handshake-wave combined approach with runtime reconfiguration for designing a low latency asynchronous FIFO

    Page(s): 188 - 191
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (434 KB) |  | HTML iconHTML  

    In this paper, a novel design scheme combining a handshake protocol and wave pipeline is proposed to improve latency performance of an asynchronous linear FIFO. The stage control of the proposed FIFO can be reconfigured dynamically to be one of two different operating styles, waving or handshaking, according to the status of data flow in the FIFO. The use of wave pipelining in a control and a datapath can eliminate delays of handshaking circuits and latching data respectively. The proposed circuits have been designed with 0.25 μm, 2.5 V CMOS process technology and simulated using HSPICE. Preliminary results show about two times improvement on latency performance over a state-of-art linear FIFO circuit while retaining throughput and a simple linear structure. View full abstract»

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  • A CMOS adiabatic logic for low power circuit design

    Page(s): 348 - 351
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (325 KB) |  | HTML iconHTML  

    In this paper, we designed the low power energy recovery circuit using the adiabatic method. The circuit avoids non-abiabatic loss using the output to ground path current control technique by the output signal. Since the circuit operates low frequency (down to 200MHz), we can save the power consumption than other adiabatic circuit. Proposed circuit was designed using TSMC 0.35μm CMOS Technology. Simulation result shows that the circuit can be operating up to 400MHz. View full abstract»

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  • High speed and low power global interconnect IP with differential transmission line and driver-receiver circuits

    Page(s): 384 - 387
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (394 KB) |  | HTML iconHTML  

    In Si ULSI, the transmission line can be realized by using the inductance of interconnects. In this paper, we design and report driver and receiver circuits for the differential transmission line, which achieve high speed and low power consumption for global interconnect. The delay time and power consumption are evaluated at 2GHz signal frequency. RLC differential transmission line is faster than RC line when interconnect length is over 4mm. RLC line has lower power consumption than RC line over 16mm. View full abstract»

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  • A 2.5-V, 14-bit MASH sigma-delta modulator for ADSL

    Page(s): 24 - 27
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (375 KB) |  | HTML iconHTML  

    This work presents a fourth order, multi-stage noise shaped (MASH) sigma-delta modulator (SDM) for wide bandwidth applications. Each stage of the SDM consists of a second order SDM with multi-level quantizer. The first stage is a low distortion second order single loop SDM, while the second stage of the SDM is a low distortion SDM with Chebyshev type II filter technique. The proposed architecture can reduce the signal distortion of circuits to improve the performance. A test SDM chip for ADSL application is designed and implemented by TSMC 0.25μm process. The simulation results indicate that the dynamic range (DR) could reach 87dB with power dissipation of 65mW. View full abstract»

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  • A 2.5Gbps serial-link data transceiver in a 0.35 μm digital CMOS technology

    Page(s): 232 - 235
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (388 KB) |  | HTML iconHTML  

    This paper presents the design of a single chip serial link data transceiver. Incorporating with 8 to 1 multiplexer and 1 to 8 demultiplexer, the transceiving data rate ranges from 640 Mbps to 2.56 Gbps. In the transmitter side, a novel precharged type multiplexer is proposed to minimize deterministic jitter. In the receiver side, an oversampling data recovery loop utilizing mixed-signal phase picking scheme is adopted for data resynchronization and demultiplexing. A novel phase interpolator with resistive averaging technique is proposed to generate uniformly distributed sampling phases over wide frequency range, so as to improve bit error rate performance. For data packet size less than 1000 bytes, the tolerated frequency offset between transmitter and receiver is about 1.3 % by a built in elastic buffer. The measured data jitter at the transmitter side after multiplexing is 5.8 ps (rms), and is 43.3 ps (rms) at the receiver side after demultiplexing. The measured bit error rate for 2.5 Gbps data receiving is about 10-10. Fabricated in a 0.35 μm digital CMOS process, this chip occupies 2.9 mm × 2.4 mm. The total power consumption is 280 mW under 2V supply. View full abstract»

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  • A word-based RSA crypto-processor with enhanced pipeline performance

    Page(s): 218 - 221
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (388 KB) |  | HTML iconHTML  

    We propose a high speed RSA crypto-processor based on an enhanced word-based Montgomery Multiplication (MM) algorithm. With the help of the proposed Correction Module (CM), the word-based modular multiplier can achieve 100% utilization. A simplified Parity Prediction Module (PPM) is also proposed to eliminate the pipeline stall. Using a 0.18 μm CMOS standard cell library, our RSA crypto-processor achieves a 512-bit RSA encryption rate of 375Kbps under 300MHz clock. The result shows that our architecture is cost-effective in terms of area and performance. View full abstract»

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  • Wire sizing considering skin effect for high frequency circuits

    Page(s): 282 - 285
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (352 KB) |  | HTML iconHTML  

    This paper proposes wire sizing considering skin effect. Previous work on wire sizing usually uses RC model which is independent of frequency. However, as increasing operating frequency, frequency-dependence of interconnect characteristics is becoming significant. Therefore, in interconnect design and analysis, frequency-dependence must be considered. By wire sizing considering frequency-dependence, the experimental results show about 50% ∼ 80% reduction of effective upper-bound wire width compared with previous work. View full abstract»

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  • Direct access test scheme for IP core protection

    Page(s): 262 - 265
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (400 KB) |  | HTML iconHTML  

    In this paper, we propose a novel direct access test scheme for intellectual property (IP) protection. The principles of new watermarking IP protection procedures depend on current IP-based design flow. The core concept is embedding a watermark generator and a test circuit into the IP core at the behavior design level. This method adopts the direct access test scheme. The ownership right is proven during the direct access test process. The watermark does not need to be designed case-by-case according to different IPs. On real designs, our approaches have low hardware overhead, tracking cost, processing time cost, and probability of coincidence. This scheme can protect the soft IP core at various design levels. It is still easy to detect the ownership rights of the IP provider after the chip has been manufactured and packaged Experimental results have demonstrated that the proposed direct access test scheme-based watermarking approaches are indeed practical. The IP provider will be able to trace a company that has engaged in the unauthorized reselling of copies of the IP. View full abstract»

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  • A 3.1-10.6 GHz CMOS cascaded two-stage distributed amplifier for ultra-wideband application

    Page(s): 296 - 299
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (348 KB) |  | HTML iconHTML  

    In this paper, a CMOS cascaded two-stage distributed amplifier for ultra-wideband (UWB) application is presented. The circuit using two-stage cascaded topology achieves better gain-bandwidth product performance than conventional CMOS distributed amplifiers. The simulated gain is 18dB with ±1dB gain flatness over 3.1∼10.6 GHz bands. Input and output are matched to 50Ω, and the return losses of input and output are below -10dB and -9dB respectively. The power dissipation is 54mW with 1.8V power supply. The circuit was fabricated in 0.18-μm 1P6M RF CMOS process. View full abstract»

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  • Reconfigurable RF circuit design for multi-band wireless chip

    Page(s): 418 - 419
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (291 KB) |  | HTML iconHTML  

    This paper presents a reconfigurable RF circuit architecture for Multi-band Wireless Chip. The circuit can be reconstructed and tuned to various applications and the best configuration by itself. Multi-band VCO using an on-chip variable inductor achieves tuning range of 37.8%, which is one of the key circuits of reconfigurable RF circuit. View full abstract»

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  • Design of LCD driver IP for SOC applications

    Page(s): 62 - 65
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (395 KB) |  | HTML iconHTML  

    This paper describes a scheme for the integration of a LCD driver IP embedded within an ARM-based system-on-chip platform. The LCD driver IP with dot matrix scalable capability can interface to AMBA on chip bus is implemented by hardware description language as a RTL design. The wrapper architecture for AMBA interface is proposed The advantages of the proposed design are easy modification of the common and segment output lines, increasing flexibility for various types of LCD panels with scalable architecture. In our study, the proposed module was verified in ARM AMRA University Kit (AUK) environment. View full abstract»

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  • Low-power design for real-time image segmentation LSI and compact digital CMOS implementation

    Page(s): 432 - 433
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (296 KB) |  | HTML iconHTML  

    We present a low-power design for real-time digital image segmentation LSI. We design the CMOS test-chip in a 0.35 μm 2-Poly 3-Metal CMOS technology, based on a boundary active only architecture. The design area for 41 × 31 pixels is 51.1mm2 and the integration density is 26.5pixel/mm2. From the circuit simulations at 3.3V supply voltage and 10MHz clock frequency, we obtain a power dissipation of 21.8mW and an image segmentation time of 23μsec. View full abstract»

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  • Comparative study of static and dynamic D-type flip-flop circuits using InP HBTs

    Page(s): 352 - 355
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (369 KB) |  | HTML iconHTML  

    A static and a dynamic D-type flip-flops (D-FFs) using InP heterojunction bipolar transistors (HBTs) were analyzed. Both the static and dynamic D-FFs employed conventional read/latch structure, however the dynamic D-FF had smaller latch current than the read current to improve the bandwidth. The static D-FF exhibited the maximum operating bit rate of 12 Gbit/s with rising/falling time of 67 ps/45 ps. The dynamic D-FF operated up to 20 Gbit/s with rising/falling time of 50 ps/32 ps. A dynamic D-FF exhibited the minimum operating bit rate of 1 Gbit/s. View full abstract»

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