Date 5-8 July 2004
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Displaying Results 1 - 25 of 140
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Effect of current crowding on copper dual damascene via bottom failure for ULSI applications
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PDF (348 KB)
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New insights into the charge loss components in a SONOS flash memory cell before and after long term cycling
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PDF (318 KB)
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Electrical characterization by sub-micron probing technique on 90 nm CMOS technology for failure analysis
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PDF (370 KB)
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Comparison of copper interconnect electromigration behaviors in various structures for advanced BEOL technology
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PDF (377 KB)
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Achievements and challenges for the electrical performance of MOSFETs with high-k gate dielectrics
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PDF (673 KB)
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The effect of geometry in the characterization of barrier profile in vias by transmission electron microscopy
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PDF (265 KB)
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Advances in magnetic-based current imaging for high resistance defects and sub-micron resolution
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PDF (387 KB)
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Active ESD shunt with transistor feedback to reduce latchup susceptibility or false triggering
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PDF (358 KB)
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Mechanism for slow programming in advanced low-voltage, high-speed ferroelectric memory
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PDF (330 KB)
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New latch-up failure mechanism between different power pins in the mixed-voltage process [CMOS ICs]
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PDF (382 KB)
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Polarity dependence of FN stress induced degradation on NMOSFETs with polysilicon gate and HfSiON gate dielectrics
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PDF (291 KB)
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Forward scattered scanning electron microscopy for semiconductor metrology and failure analysis
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PDF (167 KB)
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Magnetic microscopy for ICs failure analysis : comparative case studies using SQUID, GMR and MTJ systems
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PDF (362 KB)
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The application of scanning capacitance microscopy in device failure analysis [doping profile determination]
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PDF (343 KB)
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