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Communications, Circuits and Systems, 2004. ICCCAS 2004. 2004 International Conference on

Date 27-29 June 2004

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Displaying Results 1 - 25 of 188
  • A novel method for defect location using Iddq

    Page(s): 1325 - 1328 Vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (312 KB) |  | HTML iconHTML  

    A novel algorithm for fault location using Iddq has been presented in this paper. A significant advantage of this method is that it can effectively locate multiple defects in a circuit. An experiment used to illuminate this algorithm is discussed in detail. View full abstract»

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  • AL/RTL co-modeling and general test generation

    Page(s): 1329 - 1333 Vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (418 KB) |  | HTML iconHTML  

    Current hardware/software co-design and SOC design often need to handle system descriptions at different abstraction levels. This requires a unified modeling method across the levels to facilitate design validation. This paper addresses the problem of co-modeling across algorithmic level (AL) and register transfer level (RTL). A constraint satisfaction problem (CSP) is utilized to do the modeling. We give a framework on how to do general test generation based on this co-modeling technique with a constraint logic programming (CLP) tool as the problem-solving engine. By experimenting on an example we built, we demonstrate the application of co-modeling method. View full abstract»

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  • A boundary integral equation model for extracting frequency-dependent impedance of 3-D interconnects in VLSI

    Page(s): 1315 - 1319 Vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (359 KB) |  | HTML iconHTML  

    The accurate extraction of high frequency impedance of the 3D complex interconnects depends mainly on calculation of the 3D eddy current problem. The purpose of this paper is to put forward a boundary integral equation model for calculation of the 3D eddy current problem, which employs two separate imaginary sources, distributed over the interfaces of different regions, and the scalar potential on these interfaces as unknowns. As a boundary element method, this model avoids volume discretization of the conductors and substrate, endowing it with a potential speed. advantage. This model can be used to calculate mutual impedance between two perpendicular conductors by discarding the assumption that the current flows only along the axis direction of the conductors. Furthermore, it is applicable to general 3D structures. The validity of the new model is verified by the numerical results from several simple examples. View full abstract»

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  • The realization of fast gradient adjusted prediction method for lossless video compression with low memory requirement

    Page(s): 1165 - 1169 Vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (324 KB) |  | HTML iconHTML  

    Gradient adjusted prediction (GAP) is an efficient prediction method for lossless compression of video. By calculating its gradient in latitudinal and longitudinal orientation with the known context, the pixel value can be well estimated and used for predictive coding. However, when realizing this method in a real-time compression system, it needs a large amount of memory space. The number of operations for each pixel is also large. In this paper, we introduce an optimized algorithm to realize GAP in a digital signal processor (DSP) named Analog Device Blackfin™ DSP BF533. The GAP calculation is divided into two parts: gradient calculation and prediction calculation, and carefully designed to utilize the direct memory access (DMA) operation and parallel instruction provided by BF533. Worthless repetition and stalls in the DSP pipeline are avoided. View full abstract»

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  • Modulator evaluation method in Δ-Σ fractional-N frequency synthesis

    Page(s): 1174 - 1178 Vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (405 KB) |  | HTML iconHTML  

    The choice of a Δ-Σ modulator architecture has a significant impact on the performance of the Δ-Σ frequency synthesizer. The paper focuses on a modulator design method that allows full modulator and synthesizer characterization. It is shown that the MASH architecture can be designed to maintain a constant, arbitrarily long, output sequence for each input DC value. A modulator designed in such a way spreads the quantization noise over a known, arbitrarily large number of tones within the Nyquist bandwidth. Post modulator filtering is considered as a case study. View full abstract»

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  • Floating dynamic access technology

    Page(s): 1511 - 1515 Vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (402 KB) |  | HTML iconHTML  

    A dual gate cell with double injection one-transistor dynamic access structure is proposed. Based on the change of potential, using the floating effect, the cell works on high injection efficiency and low read-out time. The character of the dual gate cell with double injection is found to be better than the single injection cell using a two-dimensional simulator. The development history of the dynamic access cell based on a MOS structure is introduced; this is considered to decrease the chip area and to improve the integration level. The DRAM cell structure changes from the original four-transistor structure to a three-transistor structure, and to the mature product structure - one transistor and one capacitor (1T/1C). So far, the study has focused on the one-transistor structure. View full abstract»

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  • Parameter estimation of cascades model for network traffic

    Page(s): 855 - 858 Vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (334 KB) |  | HTML iconHTML  

    The cascades model was proposed recently to represent network traffic comprehensively. A parameter estimation procedure for the cascades model is proposed. Examples of the estimation procedure using artificially generated and real network collected traffic are given. It is pointed out that the stochastic process, which is in the cascades model, should not be the sequence of packet counts in unit time or the sequence of inter-arrival time between packets; instead, their cumulative sequences should be used. View full abstract»

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  • Medical image segmentation based on Mumford-Shah model

    Page(s): 942 - 945 Vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (372 KB) |  | HTML iconHTML  

    Segmentation of medical images has become an indispensable process to quantitative analysis of images of human organs and their functions. In this paper, we discuss a novel approach to the segmentation of medical images. The Mumford-Shah model segmentation problem can be solved using the level set method. The new model can detect objects whose boundaries are not necessarily defined by gradient, as well as interior contours automatically. The model algorithm can be simultaneously used to denoise, segment, detect-extract edges. The approach is fast and accurate. The experimental results on various cases demonstrate the accuracy of the approach. View full abstract»

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  • Thermal constraints for BBL placement

    Page(s): 1253 - 1256 Vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (334 KB) |  | HTML iconHTML  

    Trends in microelectronic design go toward increased component integrated density and higher power consumption. Thermal management has had a more prominent role in recent years. Therefore, an accurate thermal model was needed to develop a new placement algorithm designed to consider both minimization of chip area and thermal evenness. Simulated annealing was employed in our algorithm. The experimental results show that the thermal distribution was even and the temperature of the "hot spots" decreased greatly in the chip. View full abstract»

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  • Key design techniques of a 40 ns 16 Kbit embedded EEPROM memory

    Page(s): 1516 - 1520 Vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (389 KB) |  | HTML iconHTML  

    A 2K×8 bit EEPROM memory, which operates with a single 3.3 V power supply based on SMIC 0.35 μm EEPROM process, has been developed. Several key design techniques are summarized. An improved read out circuit that consists of SA (sense amplifier), bit line decoding and an optimized logic circuit to minimize the read access time, is described particularly, as well as the approaches to optimize the program operation and to generate on-chip high voltage. A 40 ns typical read access time and 2 ms page programming time are achieved. The active and standby currents are 10 mA and 100 μA respectively. View full abstract»

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  • Segmentation of osteosarcoma based on analysis of blood-perfusion EPI series

    Page(s): 955 - 959 Vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (500 KB) |  | HTML iconHTML  

    The treatment of osteosarcoma has suffered from the lack of the evaluation of the response of the tumor to chemotherapy. The main issue is that osteosarcoma does not shrink in response to chemotherapy; instead, viable tumor is replaced by necrotic tissue. To distinguish the portions within the osteosarcoma accurately, a new segmentation method based on the analysis of blood-perfusion EPI MRI series is proposed in this article. A similarity mapping method is used to analyze blood-perfusion EPI MRI series, and a watershed method with specific preprocessing is included to do the segmentation. A segmentation result of this method to a patient is shown and compared with the result of the surgery. View full abstract»

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  • A novel statistical method for segmentation of brain MRI

    Page(s): 946 - 949 Vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (383 KB) |  | HTML iconHTML  

    The expectation maximization (EM) algorithm has been used widely for computing the maximum likelihood (ML) parameters in the statistical segmentation of brain magnetic resonance (MR) images. As the standard EM algorithm is time and computer memory consuming, the segmentation is impractical in many real-world situations. In order to overcome this, an improved EM algorithm is presented. A novel statistical method is developed by combining the improved EM algorithm with a region growing algorithm, which is used to provide the a priori knowledge for the segmentation. The experimental results show that the proposed method can largely reduce the computing time and computer memory. View full abstract»

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  • Architecture analysis of MLP by geometrical interpretation

    Page(s): 1042 - 1046 Vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (427 KB) |  | HTML iconHTML  

    Traditionally, the main focus regarding the architecture selection of a multilayer perceptron (MLP) has been centered upon the growing and pruning and the evolutionary algorithms, in which a priori information regarding the geometrical shape of the target function is usually not exploited. In contrast to this, we demonstrate that it is the geometrical information that can simplify the task of architecture selection significantly. We wish to suggest some general guidelines for selecting the architecture of the MLP, provided that the basic geometrical shape of the target function is known in advance, or can be perceived from the training data. These guidelines are based on the geometrical interpretation of the weights, the biases, and the number of hidden neurons and layers. The controversial issue of whether the four-layered MLP is superior to the three-layered MLP is also carefully examined with this geometrical interpretation. View full abstract»

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  • Improved 3-D hierarchical interconnect capacitance extraction for the analog integrated circuit

    Page(s): 1305 - 1309 Vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (450 KB) |  | HTML iconHTML  

    The hierarchical block boundary element method (HBBEM), which can extract the whole interconnect capacitance matrix with one computation, is of very high efficiency. In analog integrated circuit layout, the feature size varies largely in different layers. According to this, we present an improved HBBEM in this paper, including a new hierarchical partition method of 3D blocks, the nonuniform partition of boundary elements and improved algorithm organization. Numerical results show that the new algorithm is several times faster than the original HBBEM and suitable for the capacitance extraction of real analog integrated circuits, with high accuracy as well. View full abstract»

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  • A general packing algorithm based on single-sequence

    Page(s): 1257 - 1261 Vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (372 KB) |  | HTML iconHTML  

    The single-sequence (SS) is simply a sequence of integers 1, 2, 3, ..., n. But it leads a unique set of ABLR-relations (above, below, left-of, right-of) that hold among n objects on a plane. The direct relation set (DRS) is used to represent the direct ABLR-relations among rooms. It can be reused for any packing under the same floorplan. In this paper we analyze the relation between DRS and SS, and propose a general packing algorithm based on SS. It can update each room's coordinates on the fly. As a feature of SS, this algorithm covers all possible placements, if our objective is in bounding-box area minimization. Experimental results showed that the proposed algorithm is pretty fast and efficient compared with the performance attained by conventional algorithms. View full abstract»

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  • Real-time signal processing system for weather radar

    Page(s): 883 - 886 Vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (305 KB) |  | HTML iconHTML  

    A new signal processing system used for modern weather radar is introduced. The system processing is used on dual-linear polarization Doppler weather radar. The conventional pulse weather radar only observes one parameter, Z (reflectivity factor), the data scale is smaller than modern pulse Doppler radars and dual-polarization radar. Therefore, a new digital signal processing system is desired to realize the demands. This system is composed of four parts: HSP (hardwired signal processor), signal interface, HSO (high speed operation module) and host port interface. View full abstract»

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  • Single observer bearings-only tracking with the unscented Kalman filter

    Page(s): 901 - 905 Vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (333 KB) |  | HTML iconHTML  

    The basic problem in target motion analysis (TMA) is to estimate the trajectory of an object from noise corrupted measurement data. The position and velocity of an emitter source can be determined from the bearing angle measurements of a passive observer. The paper introduces the recently developed unscented Kalman filter (UKF) in application to bearings-only tracking. What is more, the UKF is compared to the traditional extended Kalman filter (EKF). Simulation shows that the method performs very well even under the adverse circumstances of a noisy environment. View full abstract»

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  • An algorithm for checking slicing floorplan based on HPG and its application

    Page(s): 1223 - 1227 Vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (389 KB) |  | HTML iconHTML  

    The slicing floorplan has been intensively researched for its naive property to cut-based placement, soft-module packing, designers' intention even after packing and general floorplan representations were proposed. HPG, one easy-to-understand general floorplan representation, was proved to get the optimal solution in a shorter time than other representations. In this paper, we present an algorithm to show another outstanding feature of HPG. By using this algorithm, we can search and find the optimal slicing floorplan easily, which can provide more flexibility for placement and routing tools. Experiments show the effectiveness and promising perspective of our algorithm. View full abstract»

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  • Pitch recognition based on intelligent neural network system

    Page(s): 1081 - 1085 Vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (389 KB) |  | HTML iconHTML  

    Pitch detection may be used in content-based classification and retrieval of music and audio. Most pitch detection algorithms are based on the relationship between frequency and note; however, when the pitch is hummed by an untrained person, the accuracy of pitch recognition can obviously decline. A new intelligent pitch recognition (IPR) method based on intelligent neural networks is presented. Using the ideas of intelligent neural networks, a complex task of pitch recognition can be divided into several simple ones, each of which can be easily implemented by some simple intelligent neuron. Then a large network built out of those intelligent neurons can solve the original, complex problem and the work is much easier than with traditional neural network methods. Experimental results show it is a good way for pitch recognition. View full abstract»

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  • Low noise and high gain CMOS down conversion mixer

    Page(s): 1191 - 1194 Vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (342 KB) |  | HTML iconHTML  

    The paper represents a lowest noise ever high gain CMOS direct down-conversion mixer for 1.8 GHz applications, like GSM, PCS, etc., based on 0.18 μm CMOS technology. The designed mixer uses the current bleeding technique and an extra inductor to improve the conversion gain and noise figure (NF). Also, with an extra inductor and the careful choosing of transistor sizes, the mixer has the lowest ever reported flicker noise. Simulation results show the voltage conversion gain of 28.2 dB, the single-side band (SSB) NF of 4.09 dB. Flicker noise cut-off frequency is just a few kHz. SSB NF at 50 Hz reaches 16.8 dB. The circuit operates at the supply voltage of 1.8 V, and dissipates 11.34 mW. View full abstract»

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  • A novel performance-driven automatic layout tool for analog circuit

    Page(s): 1344 - 1348 Vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (449 KB) |  | HTML iconHTML  

    The quality of analog layout is a crucial factor to the final performance of analog circuits. We present a novel performance-driven automatic layout tool for analog circuits. Considering there is always a signal flow in each analog circuit and the circuits carrying signals are the most important parts in the whole circuit, we put forward a new performance-driven automatic layout approach based on signal flow analysis. Our tool can control the performance degradation induced by layout at all the stages of layout generation from device generation to placement and routing. The methodology guarantees that the resulting layout meets all the constraints of parasitic parameters and device matches induced from performance specifications of analog circuits by sensitivity analysis. Excellent circuit performance obtained by the methodology is demonstrated by practical circuit examples. View full abstract»

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  • An efficient rectilinear Steiner minimum tree algorithm based on ant colony optimization

    Page(s): 1276 - 1280 Vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (418 KB) |  | HTML iconHTML  

    The rectilinear Steiner minimum tree (RSMT) problem is one of the fundamental problems in physical design, especially in routing, which is known to be NP-complete. This paper presents a practical heuristic for RSMT construction based on ant colony optimization (ACO). This algorithm has been implemented on a Sun workstation with Unix operating system and the results have been compared with the GeoSteiner 3.1 and a recent work using batched greedy triple construction (BGTC). Experimental results show that our algorithm, named ACO-Steiner, can get a very short run time and keep the high performance. View full abstract»

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  • A new CMOS differential difference current conveyor and its applications

    Page(s): 1156 - 1160 Vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (343 KB) |  | HTML iconHTML  

    A new CMOS realization of differential difference current conveyor (DDCC) is presented. The negative feedback action is introduced by using a current mirror to reduce channel length modulation effect of MOS transistors. Furthermore, the circuit is insensitive to the threshold voltage variation caused by the body effect of MOS transistors. Compared with the conventional design, the proposed DDCC circuit has less harmonic distortion and larger linear range. A voltage-mode filter, which simultaneously provides band-pass, high-pass, and low-pass functions, is also described. The proposed DDCC circuit is quite useful as a powerful building block of current-mode circuits because of its high performance, and its application employs fewer passive elements. SPICE simulations confirm the excellent properties of the proposed circuits. View full abstract»

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  • High resolution time-delay estimation based on wavelet denoising

    Page(s): 876 - 879 Vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (265 KB) |  | HTML iconHTML  

    Wavelet denoising and TLS-ESPRIT (total least squares version of estimation of signal parameters via rotational invariance technique) are applied to time delay estimation. At first, the correlation method and a frequency domain deconvolution are used to convert the time delay estimation problem to an estimation of the frequencies of complex sinusoids in white nonstationary noise. After that, wavelet singularity detection is applied to reduce the impact of the noise. TLS-ESPRIT is then applied to estimate the unknown time delays. Computer simulation results show that the derived method can work at about 5 dB lower SNR than the ordinary TLS-ESPRIT. View full abstract»

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  • Carrier frequency and chip rate estimation based on cyclic spectral density of MPSK signals

    Page(s): 859 - 862 Vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (311 KB) |  | HTML iconHTML  

    The problem of estimating accurately the carrier frequency and chip rate of MPSK signals is always a challenging subject in the case of lacking prior knowledge of the random code sequence and other signal parameters. A novel method of estimating carrier frequency and chip rate in severe signal environments is presented, based on the characteristics of cyclostationarity of MPSK signals and the spectral lines on the bifrequency surface. This method, with a high estimating accuracy, is proved by computer simulations. View full abstract»

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