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Proceedings of 7th International Conference on VLSI Design

5-8 Jan. 1994

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  • Proceedings of 7th International Conference on VLSI Design

    Publication Year: 1994
    Request permission for commercial reuse | PDF file iconPDF (88 KB)
    Freely Available from IEEE
  • Testable realizations of CMOS combinational circuits for voltage and current testing

    Publication Year: 1994, Page(s):197 - 202
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (516 KB)

    This paper studies the potential invalidation of tests for detecting stuck-on faults derived by neglecting circuit delays. A design for testability (DFT) technique for detecting stuck-open and stuck-on faults using voltage testing in NAND/NAND (NOR/NOR) realizations derived from irredundant sum (product) of prime implicants (implicates) is presented. The proposed design has the advantage over prev... View full abstract»

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  • On testability of differential split-level CMOS circuits

    Publication Year: 1994, Page(s):191 - 196
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (484 KB)

    Differential Split-Level (DSL) CMOS logic offers large speed improvement in CMOS circuit techniques. In this paper, the problem of testing DSL circuits is addressed for the first time to the best of our knowledge. The behaviour of DSL circuits under single stuck-at, stuck-on and stuck-open faults is analyzed. It is shown that most of these faults in DSL circuits cannot be deterministically tested ... View full abstract»

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  • The effect of built-in current sensors (BICS) on operational and test performance [CMOS ICs]

    Publication Year: 1994, Page(s):187 - 190
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    Effects of built-in current sensors on IDDQ measurement as well as on the performance of the circuit under test are considered. Most of the Built-in Current Sensor designs transform the ground terminal of the circuit under test to a virtual ground. This causes increase in both propagation delay as well as IDDQ sampling time with increase in the number of gates, affecting both... View full abstract»

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  • A 600 MHz half-bit level pipelined multiplier macrocell

    Publication Year: 1994, Page(s):95 - 100
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB)

    In this paper a high throughput 8×8 bit multiplier in a 0.8 μ CMOS process is described. A novel pipelining technique in NPCPL (normal process complementary pass transistor logic) allows fine grain pipelining with minimal overhead of area and latency. This is in contrast to conventional approaches where highly pipelined designs are constrained by area and latency overhead of pipeline latc... View full abstract»

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  • IDDQ detection of CMOS bridging faults by stuck-at fault tests

    Publication Year: 1994, Page(s):183 - 186
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (344 KB)

    Many of the physical defects in CMOS circuits such as bridging and transistor stuck-on faults are not guaranteed to be detected by logic testing. In this paper, we examine the detection efficiency of stuck-at tests in covering all possible bridging faults in IDDQ environment. We generate stuck-at fault test vectors for combinational and sequential benchmark circuits using standard ATPG ... View full abstract»

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  • OTA based neural network architectures with on-chip tuning of synapses

    Publication Year: 1994, Page(s):71 - 76
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (476 KB)

    We propose and analyze analog VLSI implementations of neural networks in which both the neural cells and the synapses are realized using Operational Transconductance Amplifiers (OTAs). These circuits have inherent advantages of immunity to noise, very high input/output impedances, differential architecture with automatic inversion, and density. An efficient on-chip technique for weight adaptation ... View full abstract»

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  • A fast algorithm for performing vector quantization and its VLSI implementation

    Publication Year: 1994, Page(s):91 - 94
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    In this paper, we propose a new tree search algorithm for performing vector quantization (VQ), and a processor and area efficient architecture for implementing it. The proposed algorithm consists of two phases: in the first phase, we perform a fast approximate search without using multiplication. In the second phase, we employ a known tree search algorithm on the neighborhood of the codevector fou... View full abstract»

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  • IDDQ measurement based diagnosis of bridging faults in full scan circuits

    Publication Year: 1994, Page(s):179 - 182
    Cited by:  Papers (5)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (292 KB)

    An algorithm for diagnosing two node bridging faults in static CMOS combinational circuits (full scan circuits) is presented. This algorithm uses results from IDDQ testing. The bridging faults considered can be between nodes that are outputs of a gate or internal nodes of gates. Experiments on ISCAS89 circuits show that: IDDQ measurement based diagnosis, using a small number... View full abstract»

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  • nOHM-a multi-process device synthesis tool for lateral DMOS structures

    Publication Year: 1994, Page(s):323 - 327
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (372 KB)

    This paper presents a synthesis tool that generates layouts of Lateral Doubly-Diffused MOS (LDMOS) structures from electrical parameters of the device or from the current and thermal requirements of the package. Optionally, it generates layouts from physical parameters like DMOS width, area and floorplan constraints. Multiple layout and metal bus styles are supported. Source and drain sense DMOSs ... View full abstract»

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  • Multiobjective search in VLSI design

    Publication Year: 1994, Page(s):395 - 400
    Cited by:  Papers (4)  |  Patents (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (572 KB)

    Many optimization problems in VLSI design involve multiple, conflicting and non-commensurate objectives. The multiobjective approach, which models each objective by a scalar-valued criterion and attempts to find all non-dominated solutions, is a natural and efficient alternative to the conventional practice of combining all objectives into a single optimization criterion. In this paper we illustra... View full abstract»

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  • A sea-of-gates style FPGA placement algorithm

    Publication Year: 1994, Page(s):221 - 224
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (380 KB)

    The placement objectives for field programmable gate arrays (FPGAs) is to achieve 100% routability within the architectural constraints. We present a hierarchical placement approach for a sea-of-gates style FPGA. The global placement phase minimizes congestion estimates of the global routing regions and satisfies all constraints at a coarser level. The detailed placer seeks to maximize the routabi... View full abstract»

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  • Application of high-level synthesis in an industrial project

    Publication Year: 1994, Page(s):5 - 10
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (572 KB)

    This paper describes the use of high-level synthesis in conjunction with logic synthesis for designing an industrial product specified at system-level in behavioral VHDL and realized in FPGAs. The designers' experiences from using the high-level synthesis tool and its interaction with the other tools are analyzed. Important problems were the handling of precise timing constraints and feedback of a... View full abstract»

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  • The design of analog self-checking circuits

    Publication Year: 1994, Page(s):67 - 70
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (344 KB)

    In this paper we introduce a new class of analog circuits, self-checking analog circuits. We develop and discuss methods to design members of this new class. We target the class of fully differential analog circuits and use the inherent dual-rail code to develop self-checking circuits. We describe the design of a self-checking operational amplifier and the associated subcircuits. Our methodology h... View full abstract»

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  • A VLSI architecture of an inverse discrete cosine transform

    Publication Year: 1994, Page(s):87 - 90
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    The inverse discrete cosine transform (IDCT) is an important function in HDTV and multimedia systems complying with JPEG or MPEG standards for video compression. However, the IDCT is computationally intensive and therefore very expensive to implement in VLSI using direct matrix multiplication. By properly arranging the sequence of input coefficients and the output data, the rows and columns of the... View full abstract»

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  • HSIM1 and HSIM2: object oriented algorithms for VHDL simulation

    Publication Year: 1994, Page(s):175 - 178
    Cited by:  Papers (1)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (356 KB)

    In this paper we present two algorithms, HSIM1 and HSIM2, for the simulation of VHDL circuit descriptions. HSIM1 and HSIM2 are both object-oriented event-driven algorithms which maintain the hierarchical nature of the simulation network. The objects in the system are instances of classes which are classes are created by compiling VHDL code into C++. These algorithms have been implemented and teste... View full abstract»

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  • Behavioral design and prototyping of a fail-safe system

    Publication Year: 1994, Page(s):159 - 162
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB)

    This paper presents a methodology for designing and prototyping a fail-safe system at behavioral level. The theoretical framework for fail-safe circuits in the literature is difficult to apply in practice because of the complexity of practical systems. In this paper, a fail-safe system is defined at the behavioral level. The fail-safe rules in the system specification allow fault-tree analysis to ... View full abstract»

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  • Finite element analysis of SiGe npn HBT

    Publication Year: 1994, Page(s):319 - 322
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (216 KB)

    A two dimensional general purpose device simulator (BISOF), based on finite element method, has been developed. The various material parameters, such as dielectric constant, energy bandgap, intrinsic carrier concentration, mobilities and life time etc., which vary with position due to the spatial variation of the composition of the have been taken into account. An npn heterojunction bipolar transi... View full abstract»

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  • Mechanical identification of inductive properties during verification of finite state machines

    Publication Year: 1994, Page(s):389 - 394
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB)

    This paper describes a method to verify a finite state machine by theorem proving. For some instances, inductive reasoning comes in handy to support the proof of verification. In this work the theorem prover itself tries to find out the properties on which induction needs to be applied. A short account of the proof procedure which is based on goal directed backward reasoning is given. A nontrivial... View full abstract»

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  • GLOVE: a graph-based layout verifier

    Publication Year: 1994, Page(s):215 - 220
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (588 KB)

    A technique for the design rule verification of layouts composed of library cells is presented. Instead of directly manipulating mask geometries, DRC correctness is tied to a set of user defined patterns of allowed cell interactions called templates. Design rule verification is achieved by covering the layout with these templates. Both layouts and templates are defined in terms of graphs and all o... View full abstract»

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  • An empirical study on the effects of physical design in high-level synthesis

    Publication Year: 1994, Page(s):11 - 16
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB)

    The authors explore the combined effect of style and aspect ratio variations on the area and delay of RT level components, which in turn affects high-level synthesis decisions. Their results indicate that point models, where a component's area and delay are assumed to be constant for a given style, are inadequate for use in the synthesis process due to the large variations in the area and delay th... View full abstract»

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  • Multiple fault testing in analog circuits

    Publication Year: 1994, Page(s):61 - 66
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (552 KB)

    Analog circuit testing is considered to be a very difficult task. This difficulty is mainly due to the lack of fault models and accessibility to internal nodes. To overcome this problem, an approach is presented for analog circuit testing. The testability of the circuit is analyzed by the multiple fault model and by functional testing. Component deviations are deduced by measuring a number of outp... View full abstract»

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  • Calculation of minimum number of registers in arbitrary life time chart

    Publication Year: 1994, Page(s):83 - 86
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (276 KB)

    This paper presents a general approach to calculate the minimum number of registers in any digital signal processing (DSP) circuit for any arbitrarily specified life-time chart and periodicity of computation. DSP operations are repetitive and periodic in nature. The life-time chart specifies the life period of all variables in a single frame and the subsequent frames are computed in a periodic man... View full abstract»

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  • An object oriented environment for modeling and synthesis of hardware circuits

    Publication Year: 1994, Page(s):407 - 412
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (484 KB)

    Presents an object oriented design environment for modeling as well as synthesis of circuits. The modeling of circuits as classes and storage of presynthesized modules has been discussed. A design approach is presented which synthesizes both the datapath and control path of a circuit from its behavioral specification provided in object oriented style. The synthesis approach can synthesize circuits... View full abstract»

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  • High speed digital filtering on SRAM-based FPGAs

    Publication Year: 1994, Page(s):229 - 232
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    Field programmable gate arrays (FPGAs) represent a very promising technology that attempts to provide the benefits of custom VLSI with low turn-around time. However, the applicability of this technology for serious DSP applications, that are compute-intensive and typically demand high throughput, has not yet been fully explored. As a case study, real time digital FIR filters of both the constant a... View full abstract»

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