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Proceedings of 7th International Conference on VLSI Design

5-8 Jan. 1994

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  • Proceedings of 7th International Conference on VLSI Design

    Publication Year: 1994
    Request permission for commercial reuse | PDF file iconPDF (88 KB)
    Freely Available from IEEE
  • IDDQ measurement based diagnosis of bridging faults in full scan circuits

    Publication Year: 1994, Page(s):179 - 182
    Cited by:  Papers (5)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (292 KB)

    An algorithm for diagnosing two node bridging faults in static CMOS combinational circuits (full scan circuits) is presented. This algorithm uses results from IDDQ testing. The bridging faults considered can be between nodes that are outputs of a gate or internal nodes of gates. Experiments on ISCAS89 circuits show that: IDDQ measurement based diagnosis, using a small number... View full abstract»

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  • HSIM1 and HSIM2: object oriented algorithms for VHDL simulation

    Publication Year: 1994, Page(s):175 - 178
    Cited by:  Papers (1)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (356 KB)

    In this paper we present two algorithms, HSIM1 and HSIM2, for the simulation of VHDL circuit descriptions. HSIM1 and HSIM2 are both object-oriented event-driven algorithms which maintain the hierarchical nature of the simulation network. The objects in the system are instances of classes which are classes are created by compiling VHDL code into C++. These algorithms have been implemented and teste... View full abstract»

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  • A 600 MHz half-bit level pipelined multiplier macrocell

    Publication Year: 1994, Page(s):95 - 100
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB)

    In this paper a high throughput 8×8 bit multiplier in a 0.8 μ CMOS process is described. A novel pipelining technique in NPCPL (normal process complementary pass transistor logic) allows fine grain pipelining with minimal overhead of area and latency. This is in contrast to conventional approaches where highly pipelined designs are constrained by area and latency overhead of pipeline latc... View full abstract»

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  • A CAD tool for design of on-chip store and generate scheme

    Publication Year: 1994, Page(s):169 - 174
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (500 KB)

    Cellular Automata (CA) and Linear Feed back Shift Register (LFSR) have been proposed for on-chip generation of pseudo-random, pseudo-exhaustive and two-pattern test vectors. The `store and generate' scheme evolved for on-chip generation of an arbitrary set of deterministic patterns for a combinational logic circuit using LFSR and CA as basic building blocks. In the present work, we report an analy... View full abstract»

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  • Multiple fault testing in analog circuits

    Publication Year: 1994, Page(s):61 - 66
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (552 KB)

    Analog circuit testing is considered to be a very difficult task. This difficulty is mainly due to the lack of fault models and accessibility to internal nodes. To overcome this problem, an approach is presented for analog circuit testing. The testability of the circuit is analyzed by the multiple fault model and by functional testing. Component deviations are deduced by measuring a number of outp... View full abstract»

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  • On testability of differential split-level CMOS circuits

    Publication Year: 1994, Page(s):191 - 196
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (484 KB)

    Differential Split-Level (DSL) CMOS logic offers large speed improvement in CMOS circuit techniques. In this paper, the problem of testing DSL circuits is addressed for the first time to the best of our knowledge. The behaviour of DSL circuits under single stuck-at, stuck-on and stuck-open faults is analyzed. It is shown that most of these faults in DSL circuits cannot be deterministically tested ... View full abstract»

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  • TWTXBB: a low latency, high throughput multiplier architecture using a new 4→2 compressor

    Publication Year: 1994, Page(s):77 - 82
    Cited by:  Papers (4)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (448 KB)

    A fast multiplier is an essential component in any high-performance system. Existing fast multiplier architectures, like Wallace Tree architecture, result in irregular layout with a complex interconnection pattern. We propose a new architecture called Tree of Wallace Tree with XORs as Building Blocks (TWTXBB) and offers a 33% improvement in performance over that of the Wallace tree. It is highly r... View full abstract»

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  • A fast algorithm for performing vector quantization and its VLSI implementation

    Publication Year: 1994, Page(s):91 - 94
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    In this paper, we propose a new tree search algorithm for performing vector quantization (VQ), and a processor and area efficient architecture for implementing it. The proposed algorithm consists of two phases: in the first phase, we perform a fast approximate search without using multiplication. In the second phase, we employ a known tree search algorithm on the neighborhood of the codevector fou... View full abstract»

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  • BINET: an algorithm for solving the binding problem

    Publication Year: 1994, Page(s):163 - 168
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (616 KB)

    In this paper we present BINET (BInding using NETwork flows), a heuristic for solving the binding problem which occurs in high-level synthesis of digital systems. BINET is derived from an ILP formulation by mapping the binding problem for each time step onto a network optimization problem which can be optimally solved in polynomial time. Solving a sequence of these network flow problems gives a he... View full abstract»

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  • An optimal design for parallel test generation based on circuit partitioning

    Publication Year: 1994, Page(s):297 - 300
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (276 KB)

    A parallel testing graph (PTG) is offered to deal with the test scheduling problem; test scheduling in this paper refers to finding an optimal test generation scheme that allocates subcircuits or part of each subcircuit to the processors in a multiprocessor system. Test generation of subcircuits that can be run simultaneously should not share the same multiplexer in the process of test generation.... View full abstract»

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  • Mechanical identification of inductive properties during verification of finite state machines

    Publication Year: 1994, Page(s):389 - 394
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB)

    This paper describes a method to verify a finite state machine by theorem proving. For some instances, inductive reasoning comes in handy to support the proof of verification. In this work the theorem prover itself tries to find out the properties on which induction needs to be applied. A short account of the proof procedure which is based on goal directed backward reasoning is given. A nontrivial... View full abstract»

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  • SAGA : a unification of the genetic algorithm with simulated annealing and its application to macro-cell placement

    Publication Year: 1994, Page(s):211 - 214
    Cited by:  Papers (20)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB)

    In this paper a stochastic optimization algorithm called SAGA is presented, which is a generalization of the genetic algorithm and the simulated annealing algorithm. Depending on the settings of its control parameters, SAGA executes as a genetic algorithm, a simulated annealing algorithm, or a mixture of these. SAGA represents an application independent approach to optimization, and the resulting ... View full abstract»

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  • A SPICE model of RLGC transmission line with error control

    Publication Year: 1994, Page(s):57 - 60
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB)

    We present a SPICE model for a length of RLGC transmission line. The line is modeled as a characteristic two-port in which the characteristic impedance is approximated as the input impedance of a lumped circuit and the propagation function is approximated as the transfer function of a second lumped circuit plus an ideal delay. We provide a new method to realize a Pade approximation of the characte... View full abstract»

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  • Design of an application specific VLSI chip for image rotation

    Publication Year: 1994, Page(s):275 - 278
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (324 KB)

    Design of an ASIC chip for on-line rotation of a digital image is reported here. A CORDIC based scheme has been used to compute the displacement of a pixel. In order to achieve high throughput, the complete image frame is divided into windows and a combination of parallel and pipeline architectures has been developed to compute the rotation of individual windows and for computing the final displac... View full abstract»

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  • Impact of logic module routing flexibility on the routability of antifuse-based channelled FPGA architectures

    Publication Year: 1994, Page(s):233 - 236
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (296 KB)

    In an antifuse based FPGA, a macro can be implemented by configuring a logic module in multiple ways. The paper evaluates the impact of the flexibility offered by these multiple layout views on the 3 main components of routability : netlength, freeway usage end maximum channel congestion. The paper presents placement and routing techniques that use the routing flexibility to enhance the routabilit... View full abstract»

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  • Two-layer wiring with pin preassignments is easier if the power supply nets are already generated

    Publication Year: 1994, Page(s):149 - 154
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (516 KB)

    We examine the constrained via minimization problem with pin preassignments (CVMPP) which arises in connection with hierarchical physical synthesis. Let A be a circuit composed of subcircuits B, C, D,.... Assume that the placement and routing phase together with the 2-layer wiring of the subcircuits, and the placement and routing phase without the 2-layer wiring of A are completed. CVMPP is the pr... View full abstract»

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  • A CORDIC based programmable DXT processor array

    Publication Year: 1994, Page(s):343 - 348
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB)

    A CORDIC based processor array which can be programmed by switch setting to compute the Discrete Hartley, Cosine or Sine Transforms or their inverses is described. Through a novel formulation of the transform computations in the CORDIC framework, N-point transforms are mapped on to a linear array of [N/2]+1 CORDIC processors with minimal control overhead to incorporate the programmability View full abstract»

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  • The effect of built-in current sensors (BICS) on operational and test performance [CMOS ICs]

    Publication Year: 1994, Page(s):187 - 190
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    Effects of built-in current sensors on IDDQ measurement as well as on the performance of the circuit under test are considered. Most of the Built-in Current Sensor designs transform the ground terminal of the circuit under test to a virtual ground. This causes increase in both propagation delay as well as IDDQ sampling time with increase in the number of gates, affecting both... View full abstract»

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  • Simulated annealing for target-oriented partial scan

    Publication Year: 1994, Page(s):107 - 112
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB)

    In this paper, we describe algorithms based on simulated annealing for selecting a subset of flip-flops to be connected into a scan path. The objective for selection is to maximise the coverage of faults that are aborted by a sequential fault simulator. We pose the problem as a combinatorial optimization, and present a heuristic algorithm based on simulated annealing. The SCOAP testability measure... View full abstract»

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  • OTA based neural network architectures with on-chip tuning of synapses

    Publication Year: 1994, Page(s):71 - 76
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (476 KB)

    We propose and analyze analog VLSI implementations of neural networks in which both the neural cells and the synapses are realized using Operational Transconductance Amplifiers (OTAs). These circuits have inherent advantages of immunity to noise, very high input/output impedances, differential architecture with automatic inversion, and density. An efficient on-chip technique for weight adaptation ... View full abstract»

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  • A VLSI architecture of an inverse discrete cosine transform

    Publication Year: 1994, Page(s):87 - 90
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    The inverse discrete cosine transform (IDCT) is an important function in HDTV and multimedia systems complying with JPEG or MPEG standards for video compression. However, the IDCT is computationally intensive and therefore very expensive to implement in VLSI using direct matrix multiplication. By properly arranging the sequence of input coefficients and the output data, the rows and columns of the... View full abstract»

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  • Architecture for VLSI design of CA based byte error correcting code decoders

    Publication Year: 1994, Page(s):283 - 286
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (256 KB)

    This paper reports a novel architecture for byte error correcting code decoders using Cellular Automata (CA). The chip architecture of the basic building blocks for double byte error locating/correcting code (DbEL/DbEC) is presented. Extension of the architecture to detect arbitrary number of byte errors has also been included. The proposed decoder provides a simple, modular, cascadable and cost e... View full abstract»

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  • A switch-memory chip for packet switching at gigabits per second

    Publication Year: 1994, Page(s):243 - 246
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (284 KB)

    The performance of store-and-forward packet switches is limited by access speeds of memory components used in the switch. Although the memory technology continues to improve, the memory bandwidth is expected to remain the bottleneck as networks move to the multi-gigabit range. The switch architecture described here offers a novel solution to this problem. The key component of the architecture is a... View full abstract»

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  • Behavioral design and prototyping of a fail-safe system

    Publication Year: 1994, Page(s):159 - 162
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB)

    This paper presents a methodology for designing and prototyping a fail-safe system at behavioral level. The theoretical framework for fail-safe circuits in the literature is difficult to apply in practice because of the complexity of practical systems. In this paper, a fail-safe system is defined at the behavioral level. The fail-safe rules in the system specification allow fault-tree analysis to ... View full abstract»

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