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Memory Technology, Design and Testing, 2004. Records of the 2004 International Workshop on

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Memory Technology, Design and Testing, 2004. Records of the 2004 International Workshop on

Date 9-10 Aug. 2004

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Records of the 2004 International Workshop on Memory Technology, Design and Testing

Do we need anything more than single bit error correction (ECC)?

A parallel built-in diagnostic scheme for multiple embedded memories

Influence of bit line twisting on the faulty behavior of DRAMs

Fast error-correcting circuits for fault-tolerant memory

A BIST algorithm for bit/group write enable faults in SRAMs

Embedded memory reliability: the SER challenge

A novel method for silicon configurable test flow and algorithms for testing, debugging and characterizing different types of embedded memories through a shared controller

Markov models of fault-tolerant memory systems under SEU

Built-in self-test and repair (BISTR) techniques for embedded RAMs

An integrated memory self test and EDA solution

Redundancy - it's not just for defects any more

SF-LRU cache replacement algorithm

Micro programmable built-in self repair for SRAMs

A programmable built-in self-diagnosis for embedded SRAM

The state-of-art and future trends in testing embedded memories

Tag skipping technique using WTS buffer for optimal low power cache design

Tutorial on magnetic tunnel junction magnetoresistive random-access memory

The effectiveness of the scan test and its new variants

Records of the 2004 International Workshop on Memory Technology, Design and Testing

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Records of the 2004 International Workshop on Memory Technology, Design and Testing

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