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Memory Technology, Design and Testing, 2004. Records of the 2004 International Workshop on

Date 9-10 Aug. 2004

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Displaying Results 1 - 25 of 26
  • The effectiveness of the scan test and its new variants

    Publication Year: 2004, Page(s):26 - 31
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (298 KB) | HTML iconHTML

    Many industrial experiments have shown that the very simple and time-efficient Scan test detects many unique faults. This paper shines a new light on the properties of Scan test; such properties will be evaluated using industrial data. In addition, it will be shown that many faults in a memory, which are not in the cell array, are detectable using the appropriate read-write sequences. The traditio... View full abstract»

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  • Built-in self-test and repair (BISTR) techniques for embedded RAMs

    Publication Year: 2004, Page(s):60 - 64
    Cited by:  Papers (6)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (375 KB) | HTML iconHTML

    High-density and high capacity embedded memories are important components for successful implementation of a system-on-a-chip. Since embedded memory cores usually occupy a large portion of the chip area, they will dominate the manufacturing yield of the system chips. In this paper, a built-in self-test and repair (BISTR) approach is proposed for semiconductor memories with 1-D redundancy (redundan... View full abstract»

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  • Micro programmable built-in self repair for SRAMs

    Publication Year: 2004, Page(s):72 - 77
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (392 KB) | HTML iconHTML

    A built-in self-repair (BISR) machine is herewith proposed, able to test at speed and repair embedded static random access memories. Unlike the common approach to blow laser-fuse registers, here the repair operation is completely accomplished by the BISR machine, with no external intervene. The information related to the repair operation is stored into an on-chip FLASH memory. The machine is user ... View full abstract»

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  • A novel method for silicon configurable test flow and algorithms for testing, debugging and characterizing different types of embedded memories through a shared controller

    Publication Year: 2004, Page(s):78 - 83
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (227 KB) | HTML iconHTML

    In present day system-on-chips (SOC), a large part (∼70%) is occupied by memories. The overall yield of the SoC relies heavily on the memory yield. To minimize the test and diagnosis effort, we present a system for silicon configurable test flow and algorithms for different types of memories including multi-port memories, through a shared controller. It supports manufacturing tests as well as ... View full abstract»

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  • A BIST algorithm for bit/group write enable faults in SRAMs

    Publication Year: 2004, Page(s):98 - 101
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (244 KB) | HTML iconHTML

    The use of group (or bit) write enable in memories is becoming very common in embedded memories. The circuitry used to achieve these functions need be thoroughly tested for different kind of defects using specific test sequence. However, most BIST algorithms assume that these write enables are forced active during the global write cycle in the BIST run. This paper presents a serial interface BIST ... View full abstract»

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  • Embedded memory reliability: the SER challenge

    Publication Year: 2004, Page(s):104 - 110
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (391 KB) | HTML iconHTML

    Drastic decreases in device dimensions and power supply have significantly reduced noise margins and challenged the reliability of very deep-submicron chips. Soft error rate is the main cause behind this challenge. Even though both logic block and embedded memories are impacted by this challenge, but the failure rate in embedded memories remains dominant and requires infrastructure IP for self-cor... View full abstract»

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  • SF-LRU cache replacement algorithm

    Publication Year: 2004, Page(s):19 - 24
    Cited by:  Papers (14)  |  Patents (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (264 KB) | HTML iconHTML

    In this paper we propose a replacement algorithm, SF-LRU (second chance-frequency - least recently used) that combines the LRU (least recently used) and the LFU (least frequently used) using the second chance concept. A comprehensive comparison is made between our algorithm and both LRU and LFU algorithms. Experimental results show that the SF-LRU significantly reduces the number of cache misses c... View full abstract»

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  • The state-of-art and future trends in testing embedded memories

    Publication Year: 2004, Page(s):54 - 59
    Cited by:  Papers (28)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (313 KB) | HTML iconHTML

    According to the International Technology Roadmap for Semiconductors (ITRS 2001), embedded memories will continue to dominate the increasing system on chips (SoCs) content in the next years, approaching 94% in about 10 years. Therefore the memory yield will have a dramatical impact on the overall defect-per-million (DPM) level, hence on the overall SoC yield. Meeting a high memory yield requires u... View full abstract»

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  • Tutorial on magnetic tunnel junction magnetoresistive random-access memory

    Publication Year: 2004, Page(s):46 - 51
    Cited by:  Papers (4)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB) | HTML iconHTML

    Magnetic tunnel junction magnetoresistive random-access memory (MTJ-MRAM) appears to be in an advanced stage of development at several companies, including Motorola Inc., IBM Corporation, Infineon Technologies and Cypress Semiconductor Corp. MRAM has the potential to become a universal memory technology, with the high speed of SRAM, the nonvolatility of flash memory (but with much greater write-er... View full abstract»

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  • A parallel built-in diagnostic scheme for multiple embedded memories

    Publication Year: 2004, Page(s):65 - 69
    Cited by:  Papers (1)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (238 KB) | HTML iconHTML

    Hundreds of memory cores can be found on a typical system-on-chip (SOC) today. Diagnosing such a large number of memory cores using a conventional built-in self-test (BIST) architecture consumes too much time, as its on-chip diagnostics support is for sequential diagnosis only. In this paper, we present a memory BIST architecture with parallel diagnosis scheme. The proposed parallel built-in self-... View full abstract»

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  • An integrated memory self test and EDA solution

    Publication Year: 2004, Page(s):92 - 95
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (290 KB) | HTML iconHTML

    Memory built-in self-test (BIST) is a critical portion of the chip design and electronic design automation (EDA) flow. A BIST tool needs to understand the memory at the topological and layout levels in order to test for the correct fault models. The BIST also needs to be fully integrated into the overall EDA flow in order to have the least impact on chip area and have the greatest ease of use to t... View full abstract»

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  • A programmable built-in self-diagnosis for embedded SRAM

    Publication Year: 2004, Page(s):84 - 89
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (402 KB) | HTML iconHTML

    In this work we present a built-in self-diagnosis (BISD) module, an integrated solution for the fault diagnosis of embedded memories. The BISD methodology proposed includes a built-in self-test block and an additional circuitry to perform the on-chip failure analysis in order to detect the main defects. The fault diagnosis system developed is aimed to the maturation of the technology as well as to... View full abstract»

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  • Redundancy - it's not just for defects any more

    Publication Year: 2004, Page(s):117 - 120
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (227 KB) | HTML iconHTML

    This paper shows how process variation affects memory margin and performance, and shows that in some cases additional redundancy capability can be used to recover yield due to process variation in addition to yield recovery for defects. View full abstract»

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  • Do we need anything more than single bit error correction (ECC)?

    Publication Year: 2004, Page(s):111 - 116
    Cited by:  Papers (23)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (240 KB) | HTML iconHTML

    For a long time, single bit error correction (with double bit error detection) has been the mainstay ECC technology for covering soft errors in the cache. From the soft error rate that has been observed (at least terrestrially), people have been content with what single bit correction can offer. For the rare occasion that a double error occurs, ECC will also be able to alert the system and result ... View full abstract»

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  • Fast error-correcting circuits for fault-tolerant memory

    Publication Year: 2004, Page(s):8 - 12
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (290 KB) | HTML iconHTML

    This work explores the design and analysis of an error-correcting circuit as applied to high density and low latency memories, especially NOR Flash and DRAM. In very high density semiconductor memory products, exhaustive testing and repair procedures are essential to insure the proper operation of every memory location under worst possible conditions and can account for a significant portion of th... View full abstract»

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  • Influence of bit line twisting on the faulty behavior of DRAMs

    Publication Year: 2004, Page(s):32 - 37
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (297 KB) | HTML iconHTML

    Bit line twisting is an effective design method commonly used to reduce the impact of bit line coupling noise in high density memory devices. This paper investigates the way bit line twisting influences the faulty behavior of DRAMs, based on an analytical evaluation of coupling effects on the one hand, and a simulation-based fault analysis using a Spice simulation model on the other. Two different... View full abstract»

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  • Tag skipping technique using WTS buffer for optimal low power cache design

    Publication Year: 2004, Page(s):13 - 18
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (280 KB) | HTML iconHTML

    In this paper we present a robust technique to reduce the power consumption for a 4-way set-associativity cache. Our algorithm is a modification of the technique proposed by H. Choi et al. (2000) which allows skipping tag look-ups to achieve a better power consumption design. Previous work shows that implementing tag-skipping technique on a Not-Load-on-write-miss architecture, though reduces the o... View full abstract»

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  • Markov models of fault-tolerant memory systems under SEU

    Publication Year: 2004, Page(s):38 - 43
    Cited by:  Papers (11)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (342 KB) | HTML iconHTML

    A single event upset (SEU) can affect the correct operation of digital systems, such as memories and processors. This paper proposes Markov based models for analyzing the reliability and availability of different fault-tolerant memory arrangements under the operational scenario of an SEU. These arrangements exploit redundancy (either duplex or triplex replication) for dynamic fault-tolerant operat... View full abstract»

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  • Records of the 2004 International Workshop on Memory Technology, Design and Testing

    Publication Year: 2004
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  • Records of the 2004 International Workshop on Memory Technology, Design and Testing

    Publication Year: 2004, Page(s): i
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    Publication Year: 2004, Page(s): ii
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  • Records of the 2004 International Workshop on Memory Technology, Design and Testing

    Publication Year: 2004, Page(s): iii
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  • Copyright page

    Publication Year: 2004, Page(s): iv
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  • Table of contents

    Publication Year: 2004, Page(s):v - vi
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  • Conference organization

    Publication Year: 2004, Page(s): vii
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