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Memory Technology, Design and Testing, 2004. Records of the 2004 International Workshop on

Date 9-10 Aug. 2004

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  • Micro programmable built-in self repair for SRAMs

    Publication Year: 2004 , Page(s): 72 - 77
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (392 KB) |  | HTML iconHTML  

    A built-in self-repair (BISR) machine is herewith proposed, able to test at speed and repair embedded static random access memories. Unlike the common approach to blow laser-fuse registers, here the repair operation is completely accomplished by the BISR machine, with no external intervene. The information related to the repair operation is stored into an on-chip FLASH memory. The machine is user programmable, since it can test memories of different capacity, architecture and aspect ratio, with up to four test algorithms and two test flows. An "industrial" test flow is intended for production; while, in case of failure, a more complex "screening flow" allows to distinguish whether the unsuccessful repair operation is due to exceeded redundancy capacity or to faulty FLASH programming. This system is aimed to enhance test diagnostic capability and to improve production yield of devices which it is connected to, by-passing the actual losses in time and resources of currently used laser-fuse approach. View full abstract»

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  • A novel method for silicon configurable test flow and algorithms for testing, debugging and characterizing different types of embedded memories through a shared controller

    Publication Year: 2004 , Page(s): 78 - 83
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (227 KB) |  | HTML iconHTML  

    In present day system-on-chips (SOC), a large part (∼70%) is occupied by memories. The overall yield of the SoC relies heavily on the memory yield. To minimize the test and diagnosis effort, we present a system for silicon configurable test flow and algorithms for different types of memories including multi-port memories, through a shared controller. It supports manufacturing tests as well as diagnosis and electrical AC characterisation of memories. With low area overhead, the proposed microcode based configurable controller gives the test engineer freedom to do complete testing on-chip with few micro-codes. View full abstract»

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  • The state-of-art and future trends in testing embedded memories

    Publication Year: 2004 , Page(s): 54 - 59
    Cited by:  Papers (16)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (313 KB) |  | HTML iconHTML  

    According to the International Technology Roadmap for Semiconductors (ITRS 2001), embedded memories will continue to dominate the increasing system on chips (SoCs) content in the next years, approaching 94% in about 10 years. Therefore the memory yield will have a dramatical impact on the overall defect-per-million (DPM) level, hence on the overall SoC yield. Meeting a high memory yield requires understanding memory designs, modelling their faulty behaviors in the presence of defects, designing adequate tests and diagnosis strategies as well as efficient repair schemes. This paper presents the state of art in memory testing including fault modeling, test design, built-in-self-test (BIST) and built-in-self-repair (BISR). Further research challenges and opportunities are discussed in enabling testing (embedded) memories, which use deep submicron technologies. View full abstract»

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  • The effectiveness of the scan test and its new variants

    Publication Year: 2004 , Page(s): 26 - 31
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (298 KB) |  | HTML iconHTML  

    Many industrial experiments have shown that the very simple and time-efficient Scan test detects many unique faults. This paper shines a new light on the properties of Scan test; such properties will be evaluated using industrial data. In addition, it will be shown that many faults in a memory, which are not in the cell array, are detectable using the appropriate read-write sequences. The traditional version of Scan test performs 'some' of such read-write sequences, but lacks the capability of performing all of them for both the 'up' and the 'down' address orders and the '0' and the '1' data values. Therefore a new set of scan based tests are proposed to fill that vacuum. View full abstract»

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  • Do we need anything more than single bit error correction (ECC)?

    Publication Year: 2004 , Page(s): 111 - 116
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (240 KB) |  | HTML iconHTML  

    For a long time, single bit error correction (with double bit error detection) has been the mainstay ECC technology for covering soft errors in the cache. From the soft error rate that has been observed (at least terrestrially), people have been content with what single bit correction can offer. For the rare occasion that a double error occurs, ECC will also be able to alert the system and result in a graceful shutdown or otherwise. However, things are changing. As technology scaling continues, we are approaching the point where we will have a billion transistors on a single piece of silicon, with a big part of this budget as memory elements. In a system, the number of memory bits is also on the rise. The scaled technology also brings with it many variations and sensitivities that can cause memory cells to function improperly, or may not function well at certain environmental conditions. Increasingly, ECC is no longer serving as just radiation induced soft error correction, but may be able to affect other forms of fault corrections as well. Will ECC be able to serve this multi-faceted role? Do we need more than single bit error correction? Can we afford the cost of multiple bit error correction? Should we need it? This paper will attempt to answer some of these questions and raise issues with the status quo. View full abstract»

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  • A BIST algorithm for bit/group write enable faults in SRAMs

    Publication Year: 2004 , Page(s): 98 - 101
    Cited by:  Papers (3)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (244 KB) |  | HTML iconHTML  

    The use of group (or bit) write enable in memories is becoming very common in embedded memories. The circuitry used to achieve these functions need be thoroughly tested for different kind of defects using specific test sequence. However, most BIST algorithms assume that these write enables are forced active during the global write cycle in the BIST run. This paper presents a serial interface BIST algorithm that is used to test defect on bit/group write enables of these memories. View full abstract»

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  • A programmable built-in self-diagnosis for embedded SRAM

    Publication Year: 2004 , Page(s): 84 - 89
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (402 KB) |  | HTML iconHTML  

    In this work we present a built-in self-diagnosis (BISD) module, an integrated solution for the fault diagnosis of embedded memories. The BISD methodology proposed includes a built-in self-test block and an additional circuitry to perform the on-chip failure analysis in order to detect the main defects. The fault diagnosis system developed is aimed to the maturation of the technology as well as to the diagnosis of circuits in case of sudden yield drop. The fault diagnosis is a key factor for the technology maturation. New technologies require a certain time to get stability before being used for massive production. On the other hand, problems of sudden yield drop can occur also when the technology is stable. In this case a fast recovery on yield is required. This BISD module is highly re-configurable, its main characteristics are the programmability with different test algorithms, the flexibility with respect to memory sizes and address scrambling and the reconfigurability with respect to the part of the array to diagnose. The BISD block has been implemented in a 0.13 μm flash technology with a 512Kbit SRAM, it has an area overhead of 13% and its maximum operation frequency is 150MHz. View full abstract»

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  • An integrated memory self test and EDA solution

    Publication Year: 2004 , Page(s): 92 - 95
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (290 KB) |  | HTML iconHTML  

    Memory built-in self-test (BIST) is a critical portion of the chip design and electronic design automation (EDA) flow. A BIST tool needs to understand the memory at the topological and layout levels in order to test for the correct fault models. The BIST also needs to be fully integrated into the overall EDA flow in order to have the least impact on chip area and have the greatest ease of use to the chip designer. View full abstract»

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  • Built-in self-test and repair (BISTR) techniques for embedded RAMs

    Publication Year: 2004 , Page(s): 60 - 64
    Cited by:  Papers (6)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (375 KB) |  | HTML iconHTML  

    High-density and high capacity embedded memories are important components for successful implementation of a system-on-a-chip. Since embedded memory cores usually occupy a large portion of the chip area, they will dominate the manufacturing yield of the system chips. In this paper, a built-in self-test and repair (BISTR) approach is proposed for semiconductor memories with 1-D redundancy (redundant rows) structures. The memory rows are virtually divided into row blocks and reconfiguration is performed at the row block level instead of the traditional row level. That is, the virtual divided word line (VDWL) concept is used for repairing of memory cores. The hardware overhead is almost negligible. An experimental chip is implemented and shows a low area overhead - about 3.06% for a 256 × 512 SRAM with 4 spare rows. We also compare the repair rate of our approach with previous memory repair algorithms. It also concludes that our approach improves the repair rate significantly. View full abstract»

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  • SF-LRU cache replacement algorithm

    Publication Year: 2004 , Page(s): 19 - 24
    Cited by:  Papers (8)  |  Patents (17)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (264 KB) |  | HTML iconHTML  

    In this paper we propose a replacement algorithm, SF-LRU (second chance-frequency - least recently used) that combines the LRU (least recently used) and the LFU (least frequently used) using the second chance concept. A comprehensive comparison is made between our algorithm and both LRU and LFU algorithms. Experimental results show that the SF-LRU significantly reduces the number of cache misses compared the other two algorithms. Simulation results show that our algorithm can provide a maximum value of approximately 6.3% improvement in the miss ratio over the LRU algorithm in data cache and approximately 9.3% improvement in miss ratio in instruction cache. This performance improvement is attributed to the fact that our algorithm provides a second chance to the block that may be deleted according to LRU's rules. This is done by comparing the frequency of the block with the block next to it in the set. View full abstract»

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  • Tutorial on magnetic tunnel junction magnetoresistive random-access memory

    Publication Year: 2004 , Page(s): 46 - 51
    Cited by:  Papers (3)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (312 KB) |  | HTML iconHTML  

    Magnetic tunnel junction magnetoresistive random-access memory (MTJ-MRAM) appears to be in an advanced stage of development at several companies, including Motorola Inc., IBM Corporation, Infineon Technologies and Cypress Semiconductor Corp. MRAM has the potential to become a universal memory technology, with the high speed of SRAM, the nonvolatility of flash memory (but with much greater write-erase endurance than flash memory), and with storage densities that could approach those of DRAM. MRAM is embeddable in conventional CMOS processes with as few as four additional masks. We briefly review early MRAM technologies such as anisotropic MRAM, spin valve MRAM, and pseudo spin valve MRAM. Then we survey both conventional MTJ-MRAM and the recently-developed read-before-write toggle-mode MTJ-MRAM. View full abstract»

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  • A parallel built-in diagnostic scheme for multiple embedded memories

    Publication Year: 2004 , Page(s): 65 - 69
    Cited by:  Papers (1)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (238 KB) |  | HTML iconHTML  

    Hundreds of memory cores can be found on a typical system-on-chip (SOC) today. Diagnosing such a large number of memory cores using a conventional built-in self-test (BIST) architecture consumes too much time, as its on-chip diagnostics support is for sequential diagnosis only. In this paper, we present a memory BIST architecture with parallel diagnosis scheme. The proposed parallel built-in self-diagnosis (PBISD) scheme was developed to work with our existing memory optimization and reconfiguration (MORE) system, which configures small memory cores into the large one specified by the user, subject to the power and geometry constraints. With PBISD and MORE, memory test and diagnosis can be done in a much shorter time, and the whole system provides a good balance among test time, test power, and test hardware overhead. Experimental results show that, when compared with a conventional BISD scheme, the diagnosis time for a case with four memory cores is only 25%. Moreover, the area overhead is only 49%, as only one test pattern generator is required. View full abstract»

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  • Markov models of fault-tolerant memory systems under SEU

    Publication Year: 2004 , Page(s): 38 - 43
    Cited by:  Papers (9)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (342 KB) |  | HTML iconHTML  

    A single event upset (SEU) can affect the correct operation of digital systems, such as memories and processors. This paper proposes Markov based models for analyzing the reliability and availability of different fault-tolerant memory arrangements under the operational scenario of an SEU. These arrangements exploit redundancy (either duplex or triplex replication) for dynamic fault-tolerant operation as provided by arbitration (for error detection and output selection) as well as in the presence of dedicated circuitry implementing different correction/detection codes for bit-flips as errors. The primary objective is to preserve either the correctness, or the fail-safe nature of the data output of the memory system for long mission time. It is shown that a duplex memory system encoded with error control codes has a higher reliability than the triplex arrangement. Moreover, the use of a code for single error correction and double error detection (SEC-DED) improves both availability and reliability compared to an error correction code with same error detection capabilities. View full abstract»

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  • Redundancy - it's not just for defects any more

    Publication Year: 2004 , Page(s): 117 - 120
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (227 KB) |  | HTML iconHTML  

    This paper shows how process variation affects memory margin and performance, and shows that in some cases additional redundancy capability can be used to recover yield due to process variation in addition to yield recovery for defects. View full abstract»

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  • Embedded memory reliability: the SER challenge

    Publication Year: 2004 , Page(s): 104 - 110
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (391 KB) |  | HTML iconHTML  

    Drastic decreases in device dimensions and power supply have significantly reduced noise margins and challenged the reliability of very deep-submicron chips. Soft error rate is the main cause behind this challenge. Even though both logic block and embedded memories are impacted by this challenge, but the failure rate in embedded memories remains dominant and requires infrastructure IP for self-correctness. ECC is such an IP. It operates in the field during normal mode operation of a chip. The infrastructure IP in this case need to be fully integrated with the functional memory IP. This allows for timing and area optimization and provides protection throughout the life cycle. This work discusses the growing SER challenge and discusses the integrated IP approach to help resolve it. View full abstract»

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  • Influence of bit line twisting on the faulty behavior of DRAMs

    Publication Year: 2004 , Page(s): 32 - 37
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (297 KB) |  | HTML iconHTML  

    Bit line twisting is an effective design method commonly used to reduce the impact of bit line coupling noise in high density memory devices. This paper investigates the way bit line twisting influences the faulty behavior of DRAMs, based on an analytical evaluation of coupling effects on the one hand, and a simulation-based fault analysis using a Spice simulation model on the other. Two different DRAM twisting schemes, in addition to a third untwisted bit line scheme, are presented and analyzed. Both the analytical and the simulation-based evaluation results show that each scheme has its own specific impact on the faulty behavior. The same approach presented in the paper can be used to analyze the impact of other bit line twisting schemes on the memory faulty behavior. View full abstract»

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  • Fast error-correcting circuits for fault-tolerant memory

    Publication Year: 2004 , Page(s): 8 - 12
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (290 KB) |  | HTML iconHTML  

    This work explores the design and analysis of an error-correcting circuit as applied to high density and low latency memories, especially NOR Flash and DRAM. In very high density semiconductor memory products, exhaustive testing and repair procedures are essential to insure the proper operation of every memory location under worst possible conditions and can account for a significant portion of the total production cost. The implementation of error-correcting circuits in conjunction with other currently-used methods for designing more fault-tolerant high density memory could allow for more simplified testing procedures after memory fabrication and significantly reduce the overall cost. Also, error-correcting circuits could increase the reliability of the memory and extend its lifetime. This paper illustrates one possible implementation of error-correcting circuits, in the form of a Hamming decoder. Clocking was accomplished with asynchronous pulse generators to ensure fast cycle times and minimal decoding delay. These circuits were designed to show that error correction can be achieved with minimal additional circuitry, system complexity, power consumption and latency. View full abstract»

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  • Tag skipping technique using WTS buffer for optimal low power cache design

    Publication Year: 2004 , Page(s): 13 - 18
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (280 KB) |  | HTML iconHTML  

    In this paper we present a robust technique to reduce the power consumption for a 4-way set-associativity cache. Our algorithm is a modification of the technique proposed by H. Choi et al. (2000) which allows skipping tag look-ups to achieve a better power consumption design. Previous work shows that implementing tag-skipping technique on a Not-Load-on-write-miss architecture, though reduces the overall power consumption, yet still consumes significant power in write miss by frequently accessing main memory. We propose the use of a write tag-skipping (WTS) buffer (WTSB) to reduce the number of write misses by 50-85% therefore reducing accesses to more power consuming devices such as main memory. This results in shifting all tag-skipping operations occurring during a miss to a hit. View full abstract»

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  • Records of the 2004 International Workshop on Memory Technology, Design and Testing

    Publication Year: 2004
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  • Records of the 2004 International Workshop on Memory Technology, Design and Testing

    Publication Year: 2004 , Page(s): i
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  • [Blank page]

    Publication Year: 2004 , Page(s): ii
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  • Records of the 2004 International Workshop on Memory Technology, Design and Testing

    Publication Year: 2004 , Page(s): iii
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  • Copyright page

    Publication Year: 2004 , Page(s): iv
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  • Table of contents

    Publication Year: 2004 , Page(s): v - vi
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  • Conference organization

    Publication Year: 2004 , Page(s): vii
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