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Acoustics, Speech, and Signal Processing, 2004. Proceedings. (ICASSP '04). IEEE International Conference on

Date 17-21 May 2004

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  • 2004 IEEE International Conference on Acoustics, Speech and Signal Processing

    Publication Year: 2004, Page(s): 0_1
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  • 2004 IEEE International Conference on Acoustics, Speech, and Signal Processing

    Publication Year: 2004, Page(s): i
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  • Copyright page

    Publication Year: 2004, Page(s): ii
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  • IEEE Signal Processing Society 2004 Board of Governors

    Publication Year: 2004, Page(s): iii
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  • ICASSP 2004 Conference Committee

    Publication Year: 2004, Page(s): iv
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  • Technical Program Committee

    Publication Year: 2004, Page(s):v - xi
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  • Future ICASSP conferences

    Publication Year: 2004, Page(s): xii
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  • ICASSP 2005 Philadelphia

    Publication Year: 2004, Page(s): xiii
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  • Conference proceedings overview

    Publication Year: 2004, Page(s): xiv
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  • Table of contents

    Publication Year: 2004, Page(s):xv - XVIII
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  • ICASSP 2004 technical program

    Publication Year: 2004, Page(s): XIX
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  • Asynchronous multi-core architecture for level set methods

    Publication Year: 2004, Page(s):V - 1-4 vol.5
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (265 KB) | HTML iconHTML

    The paper proposes an asynchronous multi-core architecture for embedded systems using partial differential equation-based image processing algorithms. A study of data flow and timing analysis is carried out in order to reveal optimal global architecture specifications. The global architecture uses a semi-parallel approach with several processing units running in parallel and shared memory blocks. ... View full abstract»

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  • Energy efficient cluster co-processors [3G wireless applications]

    Publication Year: 2004, Page(s):V - 5-8 vol.5
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (239 KB) | HTML iconHTML

    New 3G wireless algorithms require more performance than can be currently provided by embedded processors. ASICs provide the necessary performance but are costly to design and sacrifice generality. This paper introduces a clustered VLIW coprocessor approach that organizes the execution and storage resources differently than a traditional general-purpose processor or DSP. The execution units of the... View full abstract»

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  • Fully utilized and reusable architecture for fractional motion estimation of H.264/AVC

    Publication Year: 2004, Page(s):V - 9-12 vol.5
    Cited by:  Papers (33)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (742 KB) | HTML iconHTML

    We contributed a new VLSI architecture for fractional motion estimation of the H.264/AVC video compression standard. Seven inter-related loops extracted from the complex procedure are analyzed and two decomposing techniques are proposed to parallelize the algorithm for hardware with a regular schedule and full utilization. The proposed architecture, also characterized by a reusable feature, can su... View full abstract»

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  • Memory analysis and architecture for two-dimensional discrete wavelet transform

    Publication Year: 2004, Page(s):V - 13-16 vol.5
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (249 KB) | HTML iconHTML

    The large amount of the frame memory access and the die area occupied by the embedded internal buffer are the most critical issues for the implementation of the two-dimensional discrete wavelet transform (2D DWT). The former may consume the most power and waste the system memory bandwidth. The latter may enlarge the chip size and also consume much power. We categorize and analyze the 2D DWT archit... View full abstract»

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  • A low power reconfigurable DCT architecture to trade off image quality for computational complexity

    Publication Year: 2004, Page(s):V - 17-20 vol.5
    Cited by:  Papers (12)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (452 KB) | HTML iconHTML

    We present a low power reconfigurable DCT design, which achieves considerable computational complexity reduction in DCT operation with minimum image quality degradation. The approach is based on the modification of DCT bases in a bit-wise manner. Different computational complexity/image quality trade off levels are presented and a reconfigurable architecture. which can dynamically change from one ... View full abstract»

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  • Pipelining of parallel multiplexer loops and decision feedback equalizers

    Publication Year: 2004, Page(s):V - 21-4 vol.5
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (307 KB) | HTML iconHTML

    The high speed implementation of a DFE (decision feedback equalizer) requires reformulation of the DFE into an array of comparators and a multiplexer loop. The throughput of the DFE is limited by the speed of the multiplexer loop. This paper proposes a novel look-ahead computation approach to pipeline multiplexer loops. The proposed technique is demonstrated and applied to design multiplexer loop ... View full abstract»

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  • Interleaved trellis coded modulation and decoding for 10 Gigabit Ethernet over copper

    Publication Year: 2004, Page(s):V - 25-8 vol.5
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (259 KB) | HTML iconHTML

    It is highly likely that 10 Gigabit Ethernet over copper (10GBASE-T) transceivers will use a 10-level pulse amplitude modulation (PAM 10) as well as a 4D trellis code as in 1000BASE-T. The traditional trellis coded modulation scheme, as in 1000BASE-T, leads to a design where the corresponding decoder with a long critical path needs to operate at 833 MHz. It is difficult to meet the critical path r... View full abstract»

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  • Memory sub-banking scheme for high throughput turbo decoder

    Publication Year: 2004, Page(s):V - 29-32 vol.5
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (330 KB) | HTML iconHTML

    Turbo codes have revolutionized the world of coding theory with their superior performance. However, the implementation of these codes is both computationally and memory-intensive. Recently, the sliding window (SW) approach has been proposed as an effective means of reducing the decoding delay as well as the memory requirements of turbo implementations. In this paper, we present a sub-banked imple... View full abstract»

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  • Reduced-complexity implementation of algebraic soft-decision decoding of Reed-Solomon codes

    Publication Year: 2004, Page(s):V - 33-6 vol.5
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (290 KB) | HTML iconHTML

    A reduced complexity implementation of a soft Chase algorithm for algebraic soft-decision decoding of Reed-Solomon (RS) codes, based on the recently proposed algorithm of Koetter and Vardy, is presented. The reduction in complexity is obtained at the algorithm level by integrating the re-encoding and Chase algorithms and at the architecture level by considering a backup mode which sharply reduces ... View full abstract»

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  • Wordlength optimization with complexity-and-distortion measure and its application to broadband wireless demodulator design

    Publication Year: 2004, Page(s):V - 37-40 vol.5
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (252 KB) | HTML iconHTML

    Many digital signal processing algorithms are first developed in floating point and later mapped into fixed point for digital hardware implementation. During this mapping, wordlengths are searched to minimize total hardware cost and maximize system performance. Complexity and distortion measures have been separately researched for optimum wordlength selection. This paper proposes a complexity-and-... View full abstract»

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  • Floating-point to fixed-point conversion with decision errors due to quantization

    Publication Year: 2004, Page(s):V - 41-4 vol.5
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (251 KB) | HTML iconHTML

    Most existing analyses of quantization effects are given under the condition that all decision-making blocks, if they exist in a system, produce identical decisions in both fixed-point and infinite-precision (IP) implementations. However, in doing floating-point to fixed-point conversion (FFC), a fixed-point design with occasional decision errors may still be an acceptable approximation of the IP ... View full abstract»

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  • A methodology for IP integration into DSP SoC: a case study of a MAP algorithm for turbo decoder

    Publication Year: 2004, Page(s):V - 45-8 vol.5
    Cited by:  Papers (3)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (456 KB) | HTML iconHTML

    The re-use of complex digital signal processing (DSP) coprocessors can be improved using IP cores described at a high abstraction level. System integration, which is a major step in SoC design, requires taking into account communication and timing constraints to design and integrate IP. In this paper, we describe an IP design approach that relies on three main phases: constraints modeling, IP cons... View full abstract»

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  • Area efficient decoding of quasi-cyclic low density parity check codes

    Publication Year: 2004, Page(s):V - 49-52 vol.5
    Cited by:  Papers (6)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (289 KB) | HTML iconHTML

    This paper exploits the similarity between the two stages of belief propagation decoding algorithm for low density parity check codes to derive an area efficient design that re-maps the check node functional units and variable node functional units into the same hardware. Consequently, the novel approach could reduce the logic core size by approximately 21% without any performance degradation. In ... View full abstract»

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  • A fast Newton/Smith algorithm for solving algebraic Riccati equations and its application in model order reduction

    Publication Year: 2004, Page(s):V - 53-6 vol.5
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1016 KB) | HTML iconHTML

    A very fast Smith-method-based Newton algorithm is introduced for the solution of large-scale continuous-time algebraic Riccati equations (CAREs). When the CARE contains low-rank matrices, as is common in the modeling of physical systems, the proposed algorithm, called the Newton/Smith CARE or NSCARE algorithm, offers significant computational savings over conventional CARE solvers. The effectiven... View full abstract»

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