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Thermal and Thermomechanical Phenomena in Electronic Systems, 2004. ITHERM '04. The Ninth Intersociety Conference on

Date 1-4 June 2004

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  • Measurement of the temperature dependent constitutive behavior of underfill encapsulants

    Page(s): 145 - 152 Vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (551 KB) |  | HTML iconHTML  

    Reliable, consistent, and comprehensive material property data are needed for microelectronic encapsulants for the purpose of mechanical design, reliability assessment, and process optimization of electronic packages. In our research efforts, the mechanical responses of several different capillary flow snap cure underfill encapsulants are being characterized. A microscale tension-torsion testing machine has been used to evaluate the uniaxial tensile stress-strain behavior of underfill materials as a function of temperature, strain rate, specimen dimensions, humidity, thermal cycling exposure, etc. A critical step to achieving accurate experimental results has been the development of a sample preparation procedure that produces mechanical test specimens that reflect the properties of true underfill encapsulant layers. In the developed method, 75-125 μm (3-5 mil) thick underfill uniaxial tension specimens are dispensed and cured using production equipment and the same processing conditions as those used with actual flip chip assemblies. Although several underfills have been examined, this work features results for the mechanical response of a single typical capillary flow snap cure underfill. A three parameter hyperbolic tangent empirical model has been shown to provide accurate fits to the observed underfill nonlinear stress-strain behavior over a range of temperatures and strain rates. View full abstract»

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  • Constitutive model and numerical analysis for high lead solder interconnects

    Page(s): 153 - 159 Vol.2
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    High lead solder interconnects are extensively used in the electronic industry. This paper uses a unified creep plasticity (UCP) constitutive model to numerically simulate the mechanical performance of such interconnects under thermomechanical cyclic loading. The UCP model is capable of incorporating thermal and cyclic hardening effects. To make the model more objective, cyclic loading induced damage was also incorporated. The model is programmed into the commercially available FEM software ABAQUS. A uniaxial tension case was analyzed to verify the model and reasonable agreement with experimental results was achieved. A typical three-dimensioned (3D) solder bump under shear loading was analyzed and the strain/stress distribution within the solder bump was obtained. View full abstract»

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  • Mechanical fatigue reliability of PBGA assemblies with lead-free solder and halogen-free PCBs

    Page(s): 165 - 170 Vol.2
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    In order to comply with the environmental legislations in Europe (WEEE) and Japan and to capture the market share in 'green' products, electronics manufacturers are beginning to introduce lead-free solder and halogen-free PCBs into their products. The change of materials impacts the entire manufacturing supply chain, from component and solders material suppliers to assembly equipment vendors. The industry has identified possible alternatives to the Sn/Pb solder alloy but the majority of US based companies, working with NEMI, are selecting SnAgCu alloys, with minor compositional variations. However, much work is still required in the area of component and assembly reliability, especially in mechanical fatigue and impact loading, where the failure drivers are independent of the coefficient of thermal expansion. In this paper, the mechanical bend fatigue reliability of Plastic Ball Grid Array (PBGA) assemblies is investigated. Reliability of traditional PBGA assemblies is compared to those built with environmentally friendly materials. Experimental data is presented for four different combinations of Tin-Lead & Lead-Free solders as well as FR4 & Halogen-Free laminate substrates - TL/FR4, LF/FR4, TL/HF and LF/HF. The fatigue life was correlated to the different failure modes. A transition in failure modes as a function of the applied load was observed. A 3-D parametric finite element model was developed to correlate the local PCB strains and solder joint plastic strains with the fatigue life of the assembly. View full abstract»

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  • Nucleation characteristics of a structured surface in a dielectric coolant in the absence of spreading effects

    Page(s): 82 - 89 Vol.2
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    The demand for faster computing has propelled the development of faster and denser circuit technologies resulting in the increase in heat fluxes at the chip level. Chip heat fluxes are expected to exceed 250 W/cm2. In a continuing effort to understand the capabilities of phase-change liquid immersion cooling, a square silicon heat sink featuring an etched cavity array (7.4 mm×7.4 mm) was anodically bonded to a Borofloat® glass substrate and thin-film aluminum heaters (6.9 mm×6.9 mm) were deposited on the rear side to simulate chip-sized heat sources and corresponding structured immersion-cooled heat sinks. The glass substrate was selected to minimize thermal spreading and symmetry to eliminate back heat loss, in order to yield one-dimensional heat transfer data. The pool boiling characteristics of pyramidal shaped re-entrant cavities (characteristic size 40 μm) etched in silicon were evaluated in this study. The effect of cavity spacing of 0.5 mm, 0.75 mm and 1.0 mm on the heat dissipation is reported. The effect of convection plumes, on nucleate boiling parameters, from a heat source located below the test heater, with two different inter-module spacings, is also documented. High-speed photography was used to record and quantify the departure frequency, the bubble departure diameter and also to observe the effect of interaction between neighboring nucleation sites. All experiments were conducted in the dielectric fluid FC 72 at saturation temperature and at atmospheric pressure. View full abstract»

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  • Fabrication of a silicon-carbide micro-capillary pumped loop for cooling high power devices

    Page(s): 480 - 486 Vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (591 KB) |  | HTML iconHTML  

    This paper reports on the fabrication of a silicon carbide (SiC) micro-capillary pumped loop thermal management system. The micro-capillary pumped loop was fabricated using a two wafer design from SiC and glass substrates. The evaporator, condenser, and connecting lines were etched into the silicon carbide wafer and are 150 microns deep with vertical sidewalls. Capillary wicking grooves were dry-etched into borosilicate glass and are 30 microns deep and 6-30 microns wide with trapezoidal sidewalls. Glass was selected for the capillary grooves wafer in order to provide optical access of the micro-capillary pumped loop performance during testing and evaluation. The footprint of the micro-CPL device is approximately 13 mm×30 mm. View full abstract»

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  • A novel technique for in-plane thermal conductivity measurements of electrically conductive interconnects and nanostructures

    Page(s): 564 - 569 Vol.2
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    Accurate modeling of heat transport in multi-level interconnects of advanced microprocessors requires accurate knowledge of the thermal properties in thin film structures. The commonly used suspended bridge structures for the lateral thermal conductivity measurements of the metallic thin films involves significant microfabrication process and often cannot produce suspended structures with dimensions near 100 nm×100 nm. In this paper, a novel technique for the in-plane thermal conductivity measurements of electrically conductive structures is presented. Thin interconnects or nanostructures can be deposited on a silicon dioxide layer of thickness near ∼1 μm and then patterned to form a bridge with the width comparable to or less than 100 nm. Joule-heating in the patterned bridge results in a temperature distribution that is strongly dependent on the lateral conduction along the bridge itself through the silicon dioxide layer. The feasibility of the proposed structure for thermal conductivity measurement is investigated by performing careful sensitivity analysis. View full abstract»

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  • An accurate assessment of interconnect fatigue life through power cycling

    Page(s): 397 - 404 Vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (535 KB) |  | HTML iconHTML  

    A more realistic and accurate prediction of fatigue life in the second level solder interconnect was conducted through power cycling. Fatigue is the dominating failure mechanism of solder interconnects and enhancement of its life is one of the major concerns for package designers and users. Conventionally, fatigue life is obtained empirically through accelerated thermal cycling (ATC) with hundreds of parts. To reduce development time and cost, virtual qualification attempts are made using numerical simulation tools, such as finite element analysis. Modeling of life prediction has been conducted for ATC condition, which assumes uniform temperature throughout the assembly. In reality, an assembly is subjected to Power Cycling i.e. non-uniform temperature with chip as the only source of heat generation. This non-uniform temperature and different coefficient of thermal expansion (CTE) of each component makes the package deform differently than the case of uniform temperature. In this work, a proper power cycling (PC) analysis scheme was proposed and conducted to predict solder fatigue life for a flip chip plastic ball grid array (FC-PBGA) package. Numerical simulations were performed by combination of computational fluid dynamics (CFD) and finite element analyses (FEA). CFD analysis was used to extract transient heat transfer coefficients while subsequent thermal and structural FEA was performed with heat generation and heat transfer coefficient from CFD as thermal boundary condition. It was found that for organic packages Power Cycling was more severe condition and caused solder interconnects to fail earlier than ATC. View full abstract»

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  • Phase change materials as a viable thermal interface material for high-power electronic applications

    Page(s): 687 - 691 Vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (456 KB) |  | HTML iconHTML  

    Phase change materials (PCMs) are an attractive alternative to thermal greases/pads. While their thermal conductivity is not as good as greases, they are more manufacturable. This paper reports on evaluation of PCMs for high power electronic applications. Conductivity measurements were carried out for several OEM PCMs. In addition experiments were carried out to determine process parameters (to attain target thermal impedance). A few candidates were then evaluated in a single chip module, under different environmental stresses and the results are presented here. The design concept was then extended to an MCM test vehicle and two candidate PCMs were evaluated. Differences in the reliability performance between SCM and MCM form factor are explained. View full abstract»

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  • Simulation of PWB warpage during fabrication and due to reflow

    Page(s): 674 - 678 Vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (523 KB) |  | HTML iconHTML  

    As the electronic packaging industry moves towards the manufacturing of high density, multi layer PWBs, a key challenge, is the warpage of a PWB during fabrication, solder masking and reflow soldering process. Residual stresses caused by the coefficient of thermal expansion (CTE) mismatch between different board materials combined with thermo mechanical effects introduce the warpage. The excessive warpage not only adversely creates various manufacturing difficulties but also significantly causes serious reliability problems during normal operation. This paper investigates the warpage of large multi layered, high-density boards, and the effect of the layup on the warpage. Finite element analysis was used to model the thermally induced warpage of a 24 layer 492 mm×208 mm×4.88 mm PWB, due to reflow soldering. Wide ranges of, peak temperatures and cooling rates during reflow soldering were used to study the warpage of boards of varying thickness. The whole range of material properties of copper and FR4, which have been published, are used in this analysis. The warpage results, which were obtained at the end of the simulation, is presented. This analysis aid in identifying the impact of PWB layup on warpage and make recommendations to minimize warpage. View full abstract»

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  • Novel flow control concepts in microchannels

    Page(s): 622 - 628 Vol.2
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    A novel microfluidic mixing device for microsystems with electroosmotic flow (EOF)-driven liquid pumping is proposed and examined numerically. Previously demonstrated microchannel structure is considered, and the effect of various parameters have been examined numerically. The numerical results confirms the importance of effectively creating lateral velocity component in the microchannel. The results also suggest design information of the length, position and material of channel wall patterning for maximizing mixing enhancement effect. View full abstract»

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  • Investigations on the reliability of lead-free CSP subjected to harsh environments

    Page(s): 121 - 130 Vol.2
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    A study of the performance of Flip-Chip Chip-Scale Packages (FC-CSPs) with lead-free solder interconnects was undertaken. The parametric studies on the CSPs were performed considering a wide variation of geometric and material parameters. Two geometrical versions on organic interposer with different die sizes were investigated theoretically and experimentally by thermal cycling tests -40°C to 150°C. In the FE-analyses, several additional parameters were examined including BT-interposer thickness, standoff, perimeter vs. full array, and solder-mask defined vs. non-solder-mask defined (NSMD) balls. Underfilling of the CSPs was an additional option. In the finite element analyses (FEA) both SnAg and SnAgCu solders were considered. For the latter a newly developed combined primary-secondary creep law was applied in the calculations. Both the inelastic strain (creep strain) and dissipated strain energy density represent suitable indicators to evaluate cyclic damage. It is demonstrated that for a thermal test cycle both measures result in similar critical cycle numbers. The calculations show that the creep strain always concentrates at the interfaces of the balls to the package. Maximum straining typically occurs at the inner ball row. Major effects on ball fatigue life are shown to be standoff height, ball geometry on both sides non solder mask defined (NSMD), and a stiff underfill. It is also shown that the CSP reliability using a soft underfill with high CTE or a similar "average soft underfill layer", composed of the solder-mask layers and the underfill itself, can be worse than for a non-underfilled CSP. Testing results are compared to theoretical predictions. In many cases they agree reasonably well. Finally, differences between simulation and testing results are discussed. View full abstract»

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  • Thermal, mechanical and optical modelling of VCSEL packaging

    Page(s): 405 - 410 Vol.2
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    Hybrid OECB (Opto-Electrical Circuit Boards) are expected to make a significant impact in the telecomm switches arena within the next five years, creating optical backplanes with high speed point-to-point optical interconnects. OECB's incorporate short range optical interconnects, and are based on VCSEL (Vertical Cavity Surface Emitting Diode) and PD (Photo Diode) pairs, connected to each other via embedded waveguides in the OECB. The VCSEL device is flip-chip assembled onto an organic substrate with embedded optical waveguides. The performance of the VCSEL device is governed by the thermal, mechanical and optical characteristics of this assembly. During operation, the VCSEL device will heat up and the thermal change together with the CTE mismatch in the materials, will result in potential misalignment between the VCSEL apertures and the waveguide openings in the substrate. Any degree of misalignment will affect the optical performance of the package. This paper will present results from a highly coupled modelling analysis involving thermal, mechanical and optical models. The paper will also present results from an optimisation analysis based on Design of Experiments (DOE). View full abstract»

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  • A new MEMS optimal design method using CASE

    Page(s): 529 - 534 Vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (516 KB) |  | HTML iconHTML  

    We report on the development of a new micro-electro-mechanical systems (MEMS) optimal design method called Computer Aided System Evaluation (CASE), which supports the total system evaluation of MEMS devices before the design stage. Recently total system simulation and design using CAE (Computer Aided Engineering) analyses have become important in MEMS device development due to their fabrication and design complexity. Although a lot of CAE methods that can be applied to MEMS have been demonstrated, time-consuming trial-and-error processes are inevitable at the design stage in order to obtain an optimal structure. In our design method, we can clarify and simplify the relation between design parameters and the system characteristics using a CASE weighted orthogonal array. In the CASE array, the sensitivity of each design factor for the system performance shows numerically how the design parameter influences the system characteristics. The existent trade-offs between design parameters can be minimized by both modifying the design concept and adjusting the sensitivities. Therefore MEMS designers are able to optimize the total system based on the information from the CASE array. Moreover, particular system characteristics can be enhanced in order to meet the system requirement through the adjustment of weight values for the sensitivities. The CASE makes the evaluation of system validity possible at the concept design stage. To conduct the informative optimal design method at the beginning of development leads the reduction of the total MEMS design time and cost. View full abstract»

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  • Effects of combined cyclic thermal and mechanical loading on fatigue of solder joints

    Page(s): 280 - 286 Vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (575 KB) |  | HTML iconHTML  

    In the past, laboratory tests have been used to examine surface mount solder joint fatigue by means of an accelerated test to failure and to establish correlations between thermal amplitude and cycles to failure of a specimen. In this work, mechanical loading is applied in addition to thermal loading. Test coupons populated with components are tested in an apparatus enclosed in a thermal chamber that applies cyclic four-point bending to printed circuit boards (PCBs) simultaneously with synchronized thermal cycles. Bending is regulated to a given surface strain measured by a thermally insensitive strain gauge circuit mounted on the surface of the PCB. During a cycle the temperature varied nearly linearly between -50°C and 150°C in 15 minutes and had 15 minute dwells at each extreme. The bending cycle was fully reversed and applied either in or out of phase with the temperature cycle. Electrical continuity and resistance in the solder joints is monitored, and the specimens are tested until failure criteria are met. As expected, the addition of mechanical strain to the thermal load results in shorter fatigue life. At a surface strain of 1000 με the fatigue life is significantly reduced in capacitors. In addition, the failure shifted from the solder to the component with visible cracks forming in the capacitor and at the interfaces between the capacitor and solder. View full abstract»

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  • A numerical and experimental study of delamination of polymer-metal interfaces in plastic packages at solder reflow temperatures

    Page(s): 245 - 252 Vol.2
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    This paper describes a numerical and experimental study of the failure of polymer-metal interfaces in plastic-encapsulated IC packages subjected to hygrothermal loading during solder reflow. All the analyses performed are under plane strain conditions. A finite element fracture mechanics approach was employed in conjunction with the Interaction Integral Method to predict the temperature at which a small delamination in the polymer-metal interface of an IC package will propagate. In order to confirm the accuracy of the above prediction, actual package specimens were fabricated and subjected to various levels of moisture preconditioning followed by thermal loading at varying temperatures. The specimens were then examined to determine the temperature at which the interface failed. Very good agreement was found between numerical prediction and experiment. View full abstract»

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  • Carrier depletion effects and heat generation in thermal modeling of GaInP/p-GaAs heterojunction bipolar transistors

    Page(s): 439 - 446 Vol.2
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    Usually, thermal modeling of semiconductor devices is based on a heuristic reasoning for appropriating the heat generation areas in the active device regions, involving several a priori assumptions. This paper establishes the rationale for appropriating suitable regions inside the active device as sources for heat generation - Joule heat, Thomson heat and Recombinant heat, along with a brief discussion of the causes for their generation. Moreover, the primary heat generation regions have been identified in a nGaInP-Si/pGaAs-C heterojunction bipolar transistor (HBT), through analytical determination of the depletion regions in both the GaInP emitter and the n-GaAs collector, based on ab-initio calculations. Energy band diagrams have been developed, and a detailed thermal model of a 2 μm×16.5 μm emitter device with six emitters has been developed using Finite Difference Analysis (FDA). Additionally, the temperature profile across the active region of the device was characterized using emission spectroscopy. Close agreement was found between the results from the thermal model and physical measurements. View full abstract»

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  • Thermal and electro-mechanical challenges in design and operation of high heat flux processors

    Page(s): 694 - 696 Vol.2
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    Many advances in Complementary Metal Oxide Semiconductor (CMOS) technology (deep sub micron feature scales, GHz frequencies, and Silicon On Insulator (SOI)fabrication) have been made possible by increases in the packaging density of electronics. These advances began with the introduction of very large scale integration (VLSI). The combination of increased power dissipation and packaging density led to substantial growth in the chip and system heat fluxes, as well as the amplified complexity in electrical signal integrity and mechanical stackup design in the recent years, particularly in high-end computers. With the trend towards miniaturization, heat removal has become a major bottleneck in product development, especially, in low profile systems, telecom servers and blades. According to ITRS roadmap, power dissipation of high performance single chip packages is predicted to be in 218-288 W range, posing a serious challenge with no proven air-cooled solutions to exist. View full abstract»

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  • High power AlGaAs/GaAs laser diode array cm-bars and their thermal management

    Page(s): 501 - 506 Vol.2
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    High power AlGaAs/GaAs laser diode array (LDA) cm-bars emitting at around 808 nm have been designed and fabricated for applications in diode bumped solid-state laser technology. Both thermoelectric and water coolers were used for thermal management and compared for their heat dissipation efficiency. At a quasi-continuous working condition of 20% duty cycle and 1 kHz, the peak operating power of the LDA is about 61.8 W with an electro-optical conversion efficiency about 38%. The laser operation temperatures determined from redshifts of the laser-emitting spectrum are compatible with direct measurement from thermocouples. Finally, both static and transient thermal analyses were applied to the LDAs using finite element modeling (FEM) and the results match well with the spectral analysis and thermocouple measurement. View full abstract»

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  • Recent developments in nanostructured thermoelectric materials and devices

    Page(s): 731 - 732 Vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (268 KB) |  | HTML iconHTML  

    Thermal management is a critical issue for microelectronic and microphotonic devices. The efficiency of actual thermoelectric devices is determined by the thermoelectric figure of merit Z. Because Z has unit of inverse temperature, nondimensional figure-of-merit ZT that appears often in device analysis is commonly used. The best ZT materials are found in heavily doped semiconductors which has ZT ∼ 1. One particularly fruitful and exciting approach has been the use of nanostructures. In this paper, the low-dimensional structures can be considered as new materials, despite the fact that they are made of the same atomic structures as their parent materials. Because the constituent parent materials of low-dimensional structures are typically simple materials with well-known properties, the low-dimensional structures are amenable to a certain degree of analysis, prediction and optimization. The state-of-the-art of thermoelectric materials research is described here. In thermoelectric devices it is the electrons that do the useful energy conversion work and the electron temperature that matters for energy conversion. If there is a way to impart energy to electrons while minimizing the coupling to phonons, it is possible to decouple the electrons and phonons. The schematic diagram of surface plasmon coupled nonequilibrium thermoelectric cooler, which uses surface plasmons to transfer energy preferentially to electrons and utilizes non-equilibrium electron-phonon effect in thermoelectric device is shown. View full abstract»

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  • Use of superlattice thermionic emission for "hot spot" reduction in a convectively-cooled chip

    Page(s): 610 - 616 Vol.2
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    The ITRS roadmap indicates the thermal solution for high performance and cost performance computers must improve by a factor of two over the next decade to keep pace with the development of electronic equipment. However, the roadmap does not address the spatially non-uniform heating issues caused by densely routed circuitry. The localized high heat fluxes that occur due to non-uniform heating require an even more aggressive thermal solution to ensure the circuit temperature stays below the specified value. An approach to mitigating the effect of localized "hot spots" is the spread some of the heat from the high heat flux areas to areas of lower heat flux on the chip and/or substrate. Heat spreading at the die level may be accomplished through high thermal conductivity coatings on the backside of the silicon and/or the use of micro heat pipes. Alternatively, solid-state-energy-conversion devices, such as those employing thermionic emission, can be bonded to the back of the silicon chip. The solid state coolers absorb heat at the localized "hot spot" region and transport it via electrons to a region of lower heat flux. Si/SiGe superlattice micro-coolers have demonstrated a cooling power density exceeding 500 W/cm2 in an isolated configuration. In this study we investigate the integration and packaging of such micro-coolers with IC chips. Preliminary results suggest that a significant reduction in temperature can be achieved for 70 micron localized hot spots dissipating 100's of W/cm2. View full abstract»

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  • The importance of computer architecture in microprocessor thermal design

    Page(s): 729 - 730 Vol.2
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    The microarchitecture has a unique role to play in maintaining continued performance growth, since it combines runtime knowledge of program behaviour with the ability to modify the hardware's behavior-both of which can be tracked and controlled at multiple granularities in space and time. A clear phase behavior in the SPECcpu2000 program mesa, as well as substantial temperature variation across different architectural units is shown. A dynamic compact model can be constructed using only information available in pre-RTL planning stages, namely architecture parameters, floorplan, and geometric and material properties of candidate packages. Thermal-RC pairs are constructed to represent heat flow in both the lateral and vertical directions. Power dissipation in each architecture unit is represented as a current source in the RC circuit and can be modeled using any architectural modeling tool, e.g. IBM's Power Timer. This model has been validated against Micred test chip to within 7% for both steady state and transient behavior and is boundary- and initial-condition independent (BICI). One example of "temperature-aware" architecture is dynamic thermal management (DTM) in conjunction with reducing packaging cost. View full abstract»

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  • Mechanical characterization in failure strength of silicon dice

    Page(s): 203 - 210 Vol.2
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    The trend in die size decrease of the microelectronics circuits has been driven by modern IC manufacturing technology. Due to its brittle nature, high stresses induced in the die due to packaging, assembly and reliability test could result in detrimental fracture in the die. Due to its large diameter and thin layer, determination of the fracture strength of a silicon wafer would be difficult. Thus it is more applicable for silicon strength to be characterized at die level. This paper discusses the approach for the characterization of silicon die failure strength employing a simple three-point bending test, thereby providing a better understanding of the stress accumulated in the die before failure. The effects of die thickness, die size and backgrinding patterns on the die stress have been investigated. The results showed that the die strength is largely dependent on its geometry and damages due to wafer processes (surface/edge defects and backgrinding pattern). A set of thickness dependent threshold stress values for die failure has been obtained for wafers that have undergone mechanical grinding. The determined failure stress values would be useful for solving future die failure problems encountered in new packaging and process development work. View full abstract»

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  • Fluid flow and heat transfer characteristics of liquid cooled foam heat sinks

    Page(s): 640 - 647 Vol.2
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    In this paper, the fluid flow and heat transfer characteristics of liquid cooled foam heat sinks (FHSs) are investigated. Open-celled copper foam materials with two pore densities of 60 and 100 PPI (pore per inch) and four porosities varying from 0.6 to 0.9 were bonded onto copper base plates to form the FHSs. The FHSs were then assembled on flip chip BGA packages (FBGA) with thermal grease as the thermal interface material. A liquid cooling test loop was established to study the flow and heat transfer characteristics. Both pressure drops and thermal resistances were obtained through experiments. For the four 60 PPI FHSs, the one with the lowest porosity of 0.6 is found to possess the lowest thermal resistance level with the largest pressure drop. The FHSs with 100 PPI generally have slightly lower thermal resistances at the same flowrates but much larger pressure drops than the FHSs with 60 PPI. For overall performance assessment, the thermal resistances of the FHSs are plotted against the pressure drop and the pump power, together with a microchannel heat sink. At the given pressure drop and pump power, the thermal resistance of the FHS with a porosity of 0.8 and pore density of 60 PPI is the lowest among all the FHSs and is comparable to that of the microchannel heat sink. This study reveals that FHSs are a promising option in high performance electronics cooling. View full abstract»

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  • Package cooling designs for a dual-chip electronic package with one high power chip

    Page(s): 23 - 33 Vol.2
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    Dual-chip microelectronic packages (DCP) with one high power chip are being increasingly encountered in computer and other electronic systems where a common chip carrier, whether a ceramic or an organic laminate, has a central processing unit (CPU) accompanied by a memory chip. In this study, package cooling designs are developed and presented for cooling two product applications of the DCP, with one application having larger power dissipation on the CPU compared to the other. Thermal analysis was conducted to identify the encapsulation solutions for the DCP. Mechanical analysis was then conducted to identify any structural integrity concerns and include appropriate verification tests during reliability assurance testing. The encapsulation processes were optimized to ensure the reliability of the package under field operation. The reliability of the packaging structures was assured using thermal measurements, acoustic sonography, and shear and tensile strength measurements of using test vehicles and actual product DCPs. View full abstract»

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  • Description of a standardized measurement set-up to test the thermal behaviour of disk drives under well-defined forced convection boundary conditions

    Page(s): 669 - 673 Vol.2
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    This paper describes design and operation of a small wind tunnel to measure thermal behavior of DVD and CD drives under well-defined boundary conditions. Presently it is common practice that these measurements are performed either under free convection conditions or in some type of convection oven with unknown airflow conditions. It is proposed to use the measurement set-up in order to obtain after calibration the thermal resistance of critical components in the disk drive as function of average airflow along the encasing of the drive. The measurement set-up consists of a Perspex box with a standard 60 mm fan mounted in the back. A disk drive is mounted in the center of the box. The measurement set-up was designed using a commercial CFD code. The design goal is to obtain a standardized measurement set-up to measure a disk drive where test velocities can be set from 0.1 to 3 m/s, using only cheap components. After design the measurement set-up was build and measurements were carried out on a DVD drive for various air speeds and power settings. These results can be used for instance to benchmark a DVD drive mounted in a DVD recorder application. The temperatures measured in the application are compared to the results for the wind-tunnel set-up. In this way an effective air velocity can be derived for the drive mounted in the application and possible design options for the cooling system can be compared to the benchmark. View full abstract»

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