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Electronic Components and Technology Conference, 2004. Proceedings. 54th

Date 1-4 June 2004

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  • Lead free packaging and Sn-whiskers

    Publication Year: 2004 , Page(s): 1314 - 1324 Vol.2
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (980 KB) |  | HTML iconHTML  

    Replacement of Pb/Sn terminations on electronic devices with pure Sn has proven to be much more difficult than expected. The main problem is Sn whisker formation. Sn whiskers are single crystal, mechanically strong, metallic filaments that can nucleate and grow over time in such a way as to lead to device failure in the field. In this study, we present the results of Sn-whisker formation and growth studies for plated matte-Sn on copper lead frames employing stress tests as outlined in the proposed JEDEC Sn-whisker specification. The results indicate that the propensity for whisker formation decreases with increasing Sn-thickness, and with a post plate heat treatment. The propensity for whisker growth is found to dramatically change once the devices are subjected to a melting of the matte-Sn plating. A reflow preconditioning is found to be a major variable influencing the formation and growth of Sn-whiskers on bare Cu lead frames which even negates the potential benefits for thicker Sn-plates and a post-plate anneal. Only the application of a Ni-underplate was found to produce a truly robust matte-Sn whisker solution resistant to excessive whisker growth in both the as-made and post-reflowed states. View full abstract»

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  • Wetting interaction between Pb-free Sn-Zn series solders and Cu, Ag substrates

    Publication Year: 2004 , Page(s): 1310 - 1313 Vol.2
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (534 KB) |  | HTML iconHTML  

    This study investigated the wetting behavior of Cu and Ag with pure Sn and several Sn-Zn solders, including Sn-9Zn (abbreviated as Sn-Zn), Sn-8.55Zn-0.5Al (abbreviated as Sn-Al), and Sn-8.55Zn-0.5Ag-0.1Al-0.5Ga (abbreviated as Sn-Zn-Ag-Al-Ga). Results show that Sn-Zn solders exhibit better wettability with both Cu and Ag than pure Sn. The primary interfacial intermetallics in Sn-Zn are (Ag,Cu)Zn rather than (Ag,Cu)Sn. By way of alloying modification, the Sn-Zn-Ag-Al-Ga alloy exhibits a greater wetting behavior than other solders. View full abstract»

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  • Components' emissivity in reflow soldering process

    Publication Year: 2004 , Page(s): 1921 - 1924 Vol.2
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (362 KB) |  | HTML iconHTML  

    Thermal processes encountered in surface mount assembly are very complex. Transferring heat between hot source (reflow oven) to assembly (printed circuit board, components and interconnecting alloy) is done through well known possibilities: convection, infrared radiation, conduction and phase changing. The convection and the IR radiation are the main ways to transfer heat from source to assembly. The conduction and the phase changing are secondary forms. They are very important to establish the uniform temperature distribution in an assembly. Modeling the four heat transfers in case of surface mount technology it is the necessarily to split the problem in two parts. First, the reflow oven must be modeled. Second, the assembly must be modeled. Since the model for the oven is known, the assembly could be different (in the same oven are passing through different equipped PCBs). The paper present some steps of assembly modeling in fact the capability of the assembly to take heat from the heat source(reflow oven) through IR radiation. For IR heat transfer the most important parameter is the emissivity of exposed surfaces. These surfaces are: heater sources', the SMD components', and the PCB's solder mask. Supposing heater's surface emissivity to be constant to know how the assembly will absorb the heat through IR, it's necessary to know the emissivity of components', surfaces (and the emissivity of exposed PCB). The components emissivity usual is established by measurements. The method, measurements (including the corrections) and conclusions are presented in the paper. View full abstract»

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  • FR4 printed circuit board design for Giga-bits embedded optical interconnect applications

    Publication Year: 2004 , Page(s): 1996 - 2001 Vol.2
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (569 KB) |  | HTML iconHTML  

    As the demand of high data rate increases, electrical interconnects on the board becomes a bottleneck for the overall system performance because of crosstalk, transmission line effects, clock skew, and timing jitter. Thus, considerable effort has been made to investigate alternatives to board-level electrical interconnect, such as optical interconnects. However, current board-level optical interconnects still have limitations such as board fabrication cost, optical loss, and alignment tolerance. In this paper we discuss an optical board-level interconnect that uses optoelectronic devices embedded in an optical waveguide, to provide a solution to for Giga-bit data range interconnect, on FR4 printed circuit board (PCB). FR4 PCB is an attractive candidate because it is low-cost and widely used technology. However, the design of electrical interfaces to the optical interconnect still faces all the challenges of FR4 PCB design. Therefore, careful design of electrical path by EM/Schematic co-simulation is inevitable to use the FR4 PCB for 10 giga-bit per second (Gbps) applications even with optical interconnect. From the results of the measurements and simulations provided in this research, we see that fully embedded optical interconnect is a feasible solution to replace the current board-level electrical interconnect in high speed digital systems, however, the design of the optical electrical interfaces remains a challenging part of the interconnect problem. View full abstract»

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  • Development of a curriculum in nano and MEMS packaging and manufacturing for integrated systems to prepare next generation workforce

    Publication Year: 2004 , Page(s): 1706 - 1711 Vol.2
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (529 KB) |  | HTML iconHTML  

    In this narrative author has described background of nano and MEMS and related Microsystems packaging and manufacturing revolution and thus evolved educational framework that is essential to create desired workforce. This technology and market driven revolution is at the stem of new economy and demands training of skilled workforce to harbor and progress realization of novel and advanced products. The highlighted findings and examples are based upon author's experience in the related research and education for the past eight years at the University of Arkansas, where there is a major attention in building a nano and micro packaging and manufacturing program. View full abstract»

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  • Innovative packaging techniques for wearable applications using flexible silicon fibres

    Publication Year: 2004 , Page(s): 1216 - 1219 Vol.2
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    A novel technology (A. Mathewson et al., Irish Preliminary Patent P129447) that has the potential to make current wearable electronics recede even further into the background of everyday life has been developed in the form of electronically functional fibres (EFF). This is achieved by building a device in silicon on insulator (SOI) (James B. Kou and Ker-Wei Su, CMOS VLSI Engineering Silicon on Insulator (SOI), Kluwer Academic Publishers, Boston, pp. 15-59, 1998) material and under-cutting the sacrificial SiO2 layer by means of an isotropic etch process to leave a freestanding functional fibre. A demonstration of functionality based on this technology was produced in the form of a PN diode on a fibre (T. Healy et al., IEEE 53rd Electron. Comp. and Tech. Conf., pp. 1119-1122, 2003). One of the key initial considerations involved with this technology is the interconnection of such flexible structures. One approach to resolving this issue is to use a flexible printed circuit board (PCB) and a conductive adhesive paste to interconnect the individual fibres. A prototype demonstration of this technology in the form of a flexible light emitting diode (LED) circuit, using the EFF as the resistor of the circuit, is presented in this publication. View full abstract»

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  • Aging and creep behavior of Sn3.9Ag0.6Cu solder alloy

    Publication Year: 2004 , Page(s): 1325 - 1332 Vol.2
    Cited by:  Papers (24)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (602 KB) |  | HTML iconHTML  

    Aging effects and creep behavior along with microstructure changes in eutectic PbSn and the lead-free solder alloy Sn3.9Ag0.6Cu were studied. The room temperature aged Sn3.9Ag0.6Cu alloy continually age-softened due to the growth of relatively large tin-rich crystals. The 180°C aged Sn3.9Ag0.6Cu alloy initially age-softened, and the minimum flow strength was reached after one day at 180°C. This softening correlated with the growth of relatively large tin-rich crystals and with the coarsening of Ag3Sn particles. When aged at 180°C beyond one day the Sn3.9Ag0.6Cu alloy age-hardened corresponding to the dispersion of Ag3Sn particles into tin-rich crystals which previously had not contained intermetallic precipitates. The Sn3.9Ag0.6Cu alloy showed much lower absolute creep rates than the PbSn eutectic. This extreme increase in creep resistance may result from finely dispersed IMC precipitates in the tin matrix. The β-Sn dendrites after creep appear to have some orientational features (aligned at approximately 45° to the flow direction). The size and distributions of IMC is somewhat coarsened with increasing creep temperature. A number of coarsened precipitates of Cu6Sn5 segregate around the β-Sn grain boundary. The simple power-law model was found inapplicable to the whole stress regime for both types of alloy. In addition, two hyperbolic-sine models were developed to describe the creep behavior of both alloys. View full abstract»

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  • Electrical characteristics of fine pitch flip chip solder joints fabricated using low temperature solders

    Publication Year: 2004 , Page(s): 1952 - 1958 Vol.2
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (562 KB) |  | HTML iconHTML  

    The electrical characteristics of low temperature solder joints were investigated for an LCD application. The contact resistances of ultra-small eutectic 97In-3Ag (m.p.: 143°C) and eutectic 58Bi-42Sn (m.p.: 138°C) solder joints were measured and the microstructures of solder joints were characterized after flip chip joining, underfill, and reliability testing. The octagonal shaped UBMs of 50 μm and 80 μm pitches were fabricated through a photolithographic process and wet chemical etching. Low temperature solders were evaporated on UBMs, and solder bumps were formed by the lift-off and reflow process. After flip chip bonding, the resistance of the solder joint was measured from a daisy chain test structure using a 4-point technique. The real contact resistances of eutectic In-Ag and eutectic Bi-Sn solder joints were calculated as 5 mΩ and 8 mΩ, respectively, after subtracting conductor line resistances. The contact resistance of the 50 μm pitch In-Ag solder joint was similar to that of the 80 μm pitch. The 50 μm pitch Bi-Sn solder joint had higher contact resistance than that of the 80 μm pitch. The contact resistance of the In-Ag solder joint did not increase after thermal cycling test (-55°C to 125°C/1000 cycles). The contact resistance of the Bi-Sn solder joint increased up to the four times as large as the initial value after 611 cycles. View full abstract»

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  • Nanocrystalline copper and nickel as ultra high-density chip-to-package interconnections

    Publication Year: 2004 , Page(s): 1647 - 1651 Vol.2
    Cited by:  Papers (8)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (420 KB) |  | HTML iconHTML  

    Nanocrystalline (nc) copper and nickel are being explored as candidate interconnect materials for nanoscale interconnections to meet the requirements of fine pitch, superior electrical and mechanical performance while also catering to the environmental and cost concerns. Bulk nanocrystalline copper and nickel (99.999% purity) specimens of average grain size of about 50 nm were prepared by equichannel angular extrusion (ECAE). Both micro- and nanohardness measurements showed a significant increase in the hardness of the bulk specimens. The grain size analysis shows that copper is stable up to 100°C and the activation energy for grain growth was calculated to be around 35 KJ/mol. The nickel specimens were found to be stable up to 250°C. The tensile strength of these materials has been found to be 5-6 times of the conventional microcrystalline forms and the fracture toughness, JIC, values for nc- copper and nickel have been found to be 21.66 KJ/m2 and 12.13 KJ/m2, respectively, which are high for these strength levels indicating considerable capacity for plastic deformation in these materials prior to fracture. View full abstract»

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  • Chip-on-chip 3D optical interconnect with passive alignment

    Publication Year: 2004 , Page(s): 2015 - 2019 Vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (408 KB) |  | HTML iconHTML  

    In this paper, a chip-on-chip 3D optical interconnect is introduced. The package consists of a SiOB and a flip chip mirror carrier. The light beam is deflected by two pairs of micro-mirrors on both the SiOB and the flip chip mirror carrier. The optical fibers are passively aligned with the pre-defined V-grooves on the SiOB. The mirror pairs on both the SiOB and the flip chip mirror carrier are self-aligned during the reflow of flip chip solder joints. The light is coupled form one optical fiber to another fiber through an "overpass" type of 3D optical path. The prototype shown in this paper is mainly for illustration purpose. In practice, the flip chip mirror carrier may be replaced by other devices such as VCSELs and photo detectors. The presented chip-on-chip 3D optical interconnects are suitable for coupling VCSELs or photo detectors with optical fibers. It is a low cost manufacturing process compared with the TO-can, which requires active alignment. Also, the potential capability to accommodate a small form factor laser array may be another major advantage of the proposed package. View full abstract»

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  • Design of CMOS voltage controlled oscillators using package inductor

    Publication Year: 2004 , Page(s): 1682 - 1686 Vol.2
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (424 KB) |  | HTML iconHTML  

    This paper presents three different types of CMOS Voltage-Controlled-Oscillators (VCO) with the integration of embedded inductors in a multi-layer package. A high quality (Q) inductor, pertinent to creating an efficient VCO, is easily made with a thick wiring line in a multi-layer package, The embedded inductors are designed with two different packaging technologies. One is a Fine Pitch Ball Grid Array Packaging (FBGA) technology and the other is a Wafer Level Packaging (WLP) technology. The FBGA inductor showed a Q-factor about 60 at the frequency of 2GHz and that of a WLP inductor was about 25 while at 2GHz. The performances of VCOs using embedded inductors were compared with the control, a VCO designed with conventional on-chip inductors. The use of FBGA and WLP created numerous advantages. The Total Figure-Of-Merit (FOM) was enhanced due to not only reduced phase-noises, but also to improved efficiency and tuning range. View full abstract»

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  • Wafer-level integration of on-chip antennas and RF passives using high-resistivity polysilicon substrate technology

    Publication Year: 2004 , Page(s): 1879 - 1884 Vol.2
    Cited by:  Papers (10)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (506 KB) |  | HTML iconHTML  

    High-resistivity polycrystalline silicon (HRPS) wafers are utilized as low-loss substrates for three-dimensional integration of on-chip antennas and RF passive components (e.g. large inductors) in wafer-level chip-scale packages (WLCSP). Sandwiching of HRPS and silicon wafers enables to integrate large RF passives with a spacing of >150 μm to the conductive silicon substrate containing the circuitry, while providing mechanical stability, reducing form factor and avoiding any additional RF loss. Antenna performance comparable to glass substrates and high quality factors for large spiral inductors (Q=11 at 1 GHz; 34 nH) are demonstrated. The HRPS substrates have high dielectric constant, low RF loss, high thermal conductivity, perfect thermal matching, and processing similar to single-crystalline silicon. View full abstract»

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  • Improving signal integrity of system packaging by back-drilling plated through holes in board assembly

    Publication Year: 2004 , Page(s): 1220 - 1226 Vol.2
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (638 KB) |  | HTML iconHTML  

    The development and deployment of very fast signaling technologies for communication across the backplane has introduced the need for a multidisciplinary design approach where the performance of the silicon to silicon communication channel is addressed from a variety of different perspectives. SerDes technology, connectors, vias, via stubs, and board materials are among the elements that need to be considered and modeled to reach-the desired trade off with respect to performance, cost and quality. In this study, component and system level electrical performance with back-drilled (or Counter Bored) Plated Through Holes is investigated, with simulation and testing examples. The methodology that is presented leverages multidisciplinary aspects of design and puts quality as a key ingredient of the development process. The results of this work and the associated methodology have been successfully shared across Business Units and Technology Groups. View full abstract»

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  • Process technology of electronics - a graduate textbook

    Publication Year: 2004 , Page(s): 1720 - 1724 Vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (486 KB) |  | HTML iconHTML  

    The Electronics Packaging Laboratory (German abbreviation: IAVT) of Dresden University of Technology is focused on research and education in the field of the production of electronic modules and devices. Together with the Centre of Microtechnical Manufacturing (German abbreviation: ZμP), which is also a part of the Department of Electrical Engineering and Information Technology, many projects are realized. Beside this there is also a long tradition and a lot of scientific experiences in process technology, which means all questions of analyzing, describing, modeling, simulating and calculating production processes with special focus on electronics production. A number of lectures are offered. Beginning of 2003 a group of scientists of both the Electronics Packaging Lab and the Center of Microtechnical Manufacturing decided to write a summarized textbook about process technology. Edited by Prof. Wilfried Sauer the book was issued in September 2003. It is useful as a textbook for the different lectures during the main (graduate) study of Electrical Engineering, specialization Electronics Packaging, as well as a summary of the whole scientific field of process technology of electronics. View full abstract»

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  • LTCC and thick-film microresistors

    Publication Year: 2004 , Page(s): 1885 - 1890 Vol.2
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (445 KB) |  | HTML iconHTML  

    The dimensions of discrete passives, passive integrated components (arrays, networks) and embedded integral ones should be significantly reduced in the near future. Therefore the relations between minimal geometrical dimensions, technological accuracy and limitations and electrical properties become more and more important. This paper presents systematic studies of a wide spectrum of geometrical and electrical properties of thick-film and LTCC microresistors (with designed dimensions down to 50×50 μm2). The geometrical parameters (average length, width and thickness, relations between designed and real dimensions, distribution of planar dimensions) are correlated with basic electrical properties of resistors (sheet resistance, hot temperature coefficient of resistance, their distribution) as well as durability of microresistors to short electrical pulses. View full abstract»

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  • Constrained collapse solder joint formation for wafer-level-chip-scale packages to achieve reliability improvement

    Publication Year: 2004 , Page(s): 1479 - 1485 Vol.2
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (646 KB) |  | HTML iconHTML  

    Wafer-level-chip-scale-packages (WLCSP) are rapidly proving to be the package of choice for portable electronics applications. National Semiconductor's micro SMD package family has been a front-runner in the development of this package type. These packages have a proven reliability in the lower pin-count range (up to 36 I/O) when used in conjunction with standard surface mount assembly (SMT). However, extending this technology to higher pin-counts is a significant challenge. Since the preferred assembly method is to not employ an additional underfill step after reflow soldering, the options available to enhance the package reliability are limited. Several options including a pre-applied epoxy layer that will flow and form the underfill layer during solder reflow are under investigation as a potential solution. This approach has constraints in terms of compatibility with flux type used and the reflow profile used. Another approach involves creating a non-reflowable underfill layer. This is the approach described in this paper, and it has proven to work with all commercial assembly processes and to all extents and purposes is transparent to the surface mount assembly method used. This approach is based on the creation of an epoxy layer in either a film or paste layer form that acts as a layer surrounding and partially submerging the solder bumps. This layer achieves two results that directly impact the reliability of the WLCSP assembly. The primary advantage is the increase in solder joint height achieved, which improves the fatigue life when subjected to thermal excursions. The other major advantage is that with the solder bump being constrained from collapsing completely, the angle of wetting formed on the die side is increased, resulting in a more 'cylindrical' or barrel-shaped joint rather than a shape like a truncated sphere. Finite element modeling (P. Borgesen et al., IEEE Trans. on Comp., Hybrids, and Manuf. Tech., vol. 16, no. 3, pp. 272-283) has also borne out that a higher wetting angle results in higher reliability. There also appears to be an interaction between the pre-applied underfill layer thickness and the reliability of the outermost solder joint, which itself depends on the bump matrix size. A higher stand-off may not necessarily translat- e to a higher reliability due to this interaction effect. View full abstract»

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  • A multiple frequency signal generator for 802.11a/b/g VoWLAN type applications using organic packaging technology

    Publication Year: 2004 , Page(s): 1664 - 1670 Vol.2
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (620 KB) |  | HTML iconHTML  

    This paper proposes a signal generator that simultaneously generates multiple frequencies while using the same set of passive components. The first example demonstrates the capability of simultaneously generating 2.45GHz and 5.2 GHz (WLAN a/b/g). Additionally, an oscillator capable of concurrently generating 900 MHz and 1.9 GHz (GSM and DCS-1800 band) is also presented. This paper uses the theory of multi-resonant passives and shows their immediate effects on different topologies of signal generators that generate signals for two or more frequency bands. In addition, measured and simulated results of individual blocks of such a simultaneous signal generator, such as, filters, individual oscillators, and feedback networks, are demonstrated. View full abstract»

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  • Design and optimization of 3D RF modules, microsystems and packages using electromagnetic, statistical and genetic tools [mm-wave interdigitated passband filter application]

    Publication Year: 2004 , Page(s): 1412 - 1415 Vol.2
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (415 KB) |  | HTML iconHTML  

    The successful use of the design of experiments (DOE) and response surface modeling (RSM) approaches in an optimization study for a multilayer interdigitated passband filter is presented. The medium of interest is liquid crystal polymer (LCP) and the frequency band is in the 60 GHz range. The two figures of merit chosen are the resonating frequency and the quality factor Q with the optimization goals of fo=60 GHz and maximum Q. The electromagnetic performance of the filter is determined with a method of moments commercial simulator. The results of these simulations are incorporated into DOE and RSM techniques, statistical models are developed for the two output variables, and then applied to optimize the filter. The effectiveness of the method is compared to that of the genetic algorithm (GA) optimization. View full abstract»

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  • Lead-free solder interconnect by variable frequency microwave (VFM)

    Publication Year: 2004 , Page(s): 1989 - 1995 Vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (638 KB) |  | HTML iconHTML  

    A novel lead-free interconnect technique using a variable frequency microwave (VFM) was investigated. Melting the Sn-3.5Ag, Sn-3.8Ag-0.7Cu and Sn46Pb solder pastes and their wetting on the metal pads were achieved by heating the organic flux vehicle through a radio frequency microwave. The lead-free solder interconnection between the component chips and the metal pads through VFM was first demonstrated. The microstructures of the lead-free solders/Cu and Sri surface joints formed by a conventional thermal reflow process and VFM were analyzed. From the intermetallic compound (IMC) formation study, it was found that more heat energy could be employed into the solder paste by the VFM heating process than by the thermal reflow process at the peak temperatures used in this study, because VFM provided more uniform heat than the reflow oven that may lead a temperature gradient in the test boards. It is believed that by VFM the soldering process at a lower peak temperature could be feasible than by a conventional reflow process. View full abstract»

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  • Effect of wafer level packaging, silicon substrate and board material on gigabit board-silicon-board data transmission

    Publication Year: 2004 , Page(s): 1506 - 1512 Vol.2
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (481 KB) |  | HTML iconHTML  

    This paper discusses the effect of wafer level packaging, silicon substrate, and board material on gigabit data transmission. A test vehicle consisting of a co-planar silicon transmission line, two board transmission lines and wafer level packaging was used for evaluation. A silicon substrate with 100 Ω-cm resistivity was compared with a silicon substrate with 2000 Ω-cm resistivity to investigate the effect of silicon substrate on gigabit data transmission. For board transmission lines, six board materials such as Ciba thin film, Vialux from Dupont, FR4, Hitachi MCL-LX67, Nelco N4000-12, and APPE were compared to investigate the effect of board material. For wafer-level packaging, solder bumps with 50 μm diameter and 100 μm pitch were used, and the effect of parasitic capacitance in the solder bumps on gigabit data transmission was investigated. For the accurate simulation of the test vehicle in the time domain, a TDR characterization method and non-physical RLGC models for lossy transmission lines were used to characterize board and silicon transmission lines. This paper shows that better signal integrity in the test vehicle cannot be achieved only by using lower loss material, but also requires low parasitic capacitance for gigabit data transmission. View full abstract»

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  • Liquid crystalline polymer based RF/wireless components for multi-band applications

    Publication Year: 2004 , Page(s): 1866 - 1873 Vol.2
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (574 KB) |  | HTML iconHTML  

    This paper presents for the first time the design, implementation, measurements, reliability data and integration of multiple RF components such as filters, baluns, diplexers, and a combination of the above on liquid crystalline polymer (LCP) based substrates for communication standards such as 802.11 a/b/g, LMDS/MMDS, satellite/digital TV, UWB, cellular and Bluetooth type applications. These components and process technologies are being targeted as a cost-effective high-performance, miniaturized alternative to the primary technologies of choice for multi-band RF/wireless applications, namely, low-temperature co-fired ceramic (LTCC), multi-layer ceramic (MLC) and ceramic monoblock technologies. The first examples of this platform substrate technology are very compact 12 mm3 fully packaged SMT front-end filters with center frequencies of 2.45, 5.25 and 5.775 GHz. One embodiment of the filter at 2.45 GHz, which is well suited for 802.11 b/g and Bluetooth type applications, provides a passband of 100 MHz with maximum inband insertion loss less than 1.7 dB at 25°C, greater than 25 dB attenuation at 2700-2800 MHz, greater than 10 dB attenuation below 2.2 GHz, greater than 20 dB rejection at the second and third harmonic and inband VSWR less than 1.5 matched to 50 ohms at the input and output. View full abstract»

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  • An accurate electromagnetic modeling of the die-to-die interconnect link for gigabit systems applications

    Publication Year: 2004 , Page(s): 1891 - 1894 Vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (364 KB) |  | HTML iconHTML  

    The cost-effective design of gigabit per second signaling (Gb/s) for the interconnect systems requires optimizing components with accurate full channel simulations. The gigabit system performance is often defined in the time-domain (TD), but the modeling and characterization for the interconnect structures are done in the frequency-domain (FD). Due to non-linear behavior of the devices, the relation between FD and TD performances is not intuitively obvious, and therefore it is necessary to perform accurate analysis in both domains. To achieve an accurate modeling of the complex packaging structure often used a full-wave modeling tool that analyzes the propagation of electromagnetic waves through a three-dimensional model. In addition to the needs of characterization of the extended packaging boundaries, the accurate modeling utilizes a frequency-dependant material characterization. This paper describes the electromagnetic modeling methods, such as use of the frequency-dependent material properties, the method of discontinuity segmentation, and the validation technique. The vector network analyzer (VNA) where used for validation and choosing the best modeling method. Using measured and modeled data, we provide simulation in the time and the frequency domain, with comparison results. Good correlation between the modeling and measurement is reported in this paper. View full abstract»

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  • Development of a new improved high performance flip chip BGA package

    Publication Year: 2004 , Page(s): 1174 - 1180 Vol.2
    Cited by:  Papers (4)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (639 KB) |  | HTML iconHTML  

    The recent advancement in high performance semiconductor packages has been driven by the need for higher pin count and superior heat dissipation. A one-piece cavity lid flip chip BGA package with high pin count and targeted reliability has recently been developed by UTAC. The flip chip technology can accommodate I/O count of more than five hundreds, and the die junction temperature can be reduced to a minimum level by a metal heat spreader attachment. Nonetheless, greater expectations on these high performance packages arose such as better substrate land estate utilization for multiple chips, ease in handling for thinner core substrates and improved board level solder joint reliability. A new design of the flip chip BGA package has been looked into for meeting such requirements. By encapsulating the flip chip with molding compound leaving the die top exposed, a planer top surface can be formed. And a flat lid can then be mounted on the planer mold/die top surface. In this manner the direct interaction of the metal lid with the substrate can be removed. The new package is thus less rigid under thermal loading and solder joint reliability enhancement is expected. This paper discusses the process development of the new package and its advantages for improved solder joint fatigue life, and being a multi-chip package and thin core substrate options. Finite element simulations have been employed for the study of its structural integrity, thermal and electrical performances. Detailed package and board level reliability test results will also be reported. View full abstract»

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  • Accelerated thermal cycling: is it different for lead-free solder?

    Publication Year: 2004 , Page(s): 1579 - 1585 Vol.2
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (619 KB) |  | HTML iconHTML  

    Accelerated test parameters such as extreme temperatures, temperature range, temperature ramps and dwell times have a major influence on deformation mechanisms in solder joints. With the increasing push for the introduction of lead-free solders, there is a need to revisit the accelerated thermal cycling regimes, as the solder composition can also influence the deformation mechanisms in solder joints. Time independent plastic deformation due to dislocations leading to slip bands and time dependent creep deformation due to diffusional flow of vacancies leading to grain boundary sliding are the two primary deformation mechanisms in solder joints. It is recognized, for example, that the lead-free solders creep 10 to 100 times slower than tin-lead solders under a given stress state. This paper examines the inelastic deformation mechanisms in lead and lead-free solders in BGA packages. Accelerated thermal cycling guidelines have been developed keeping in perspective the field-use conditions. The accelerated thermal cycles developed mimic the solder deformation mechanisms as in the field-use conditions and also reduce the time and the cost associated with accelerated testing. The finite-element models developed in this work are validated using experimental thermal cycling data and Moire interferometry data. View full abstract»

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  • Effect of intermetallic phases on performance in a mechanical drop environment: 96.5Sn3.5Ag solder on Cu and Ni/Au pad finishes

    Publication Year: 2004 , Page(s): 1288 - 1295 Vol.2
    Cited by:  Papers (9)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (938 KB) |  | HTML iconHTML  

    Mechanical drop test reliability risk due to incompatibility between component and board surface finishes of thin (30-100 μm) 96.5Sn3.5Ag solder joint assemblies is examined in this study. Failures in test components with ENIG plated interposers occurred owing to inhibition of any Ni-Sn(Cu) intermetallic phase growth at the interposer/solder interface on account of Cu migration from the solder/ceramic interface, i.e. a coupling effect between the two interfaces of the solder joint and consequently the lack of a metallurgical bond between solder and interposer. Results of this study demonstrate that interface reaction coupling phenomena play a critical role in determining the performance of thin lead-free solder joints under mechanical loading. View full abstract»

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