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Electronic Components and Technology Conference, 2004. Proceedings. 54th

Date 1-4 June 2004

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Displaying Results 1 - 25 of 160
  • Electrical characteristics of fine pitch flip chip solder joints fabricated using low temperature solders

    Page(s): 1952 - 1958 Vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (562 KB) |  | HTML iconHTML  

    The electrical characteristics of low temperature solder joints were investigated for an LCD application. The contact resistances of ultra-small eutectic 97In-3Ag (m.p.: 143°C) and eutectic 58Bi-42Sn (m.p.: 138°C) solder joints were measured and the microstructures of solder joints were characterized after flip chip joining, underfill, and reliability testing. The octagonal shaped UBMs of 50 μm and 80 μm pitches were fabricated through a photolithographic process and wet chemical etching. Low temperature solders were evaporated on UBMs, and solder bumps were formed by the lift-off and reflow process. After flip chip bonding, the resistance of the solder joint was measured from a daisy chain test structure using a 4-point technique. The real contact resistances of eutectic In-Ag and eutectic Bi-Sn solder joints were calculated as 5 mΩ and 8 mΩ, respectively, after subtracting conductor line resistances. The contact resistance of the 50 μm pitch In-Ag solder joint was similar to that of the 80 μm pitch. The 50 μm pitch Bi-Sn solder joint had higher contact resistance than that of the 80 μm pitch. The contact resistance of the In-Ag solder joint did not increase after thermal cycling test (-55°C to 125°C/1000 cycles). The contact resistance of the Bi-Sn solder joint increased up to the four times as large as the initial value after 611 cycles. View full abstract»

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  • High frequency thermosonic flip chip bonding for gold to gold interconnection

    Page(s): 1461 - 1465 Vol.2
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    Our main objective is to compare the process windows under different ultrasonic frequencies for thermosonic flip chip application. The interaction effects of bond power and bond force on the die shear strength and package standoff height are elucidated. The effects due to different substrate materials (FR-4 and ceramic substrates) are also included. It is interesting to notice that, apparently, the vibrating amplitude and thence the bonding frequency play a key role in determining the robustness of the thermosonic flip chip bond. Based on our findings, the process windows of 63 kHz and 109 kHz bonding on FR-4 and ceramic substrates are established, respectively, and compared. Unlike some earlier studies on high frequency bonding in wirebonding, the findings in this work suggests that the process window of the 109 kHz bonding is in fact wider than the 63 kHz bonding on both substrate materials, where rigid ceramic substrates allowed larger process windows for both frequencies bonding than FR-4 substrates. View full abstract»

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  • Impediments to impedance and coupled noise: characteristic impedance design and coupled noise control on flexible circuits

    Page(s): 1788 - 1795 Vol.2
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    Signal integrity analysis is largely neglected in flexible circuit design. Referred to as "cables," ribbons or discrete connections, minimal, if any, analysis is typically performed. However, due to their ability to successfully address mechanical flexibility and cost constraints, flexible circuits have become increasingly appealing solutions for high-speed, controlled impedance interconnect. Design for signal integrity, characteristic impedance and attenuation control are critical to successfully placing flexible circuits in the highspeed market at GHz frequencies. This paper addresses the following: (1) mesh reference plane impedance prediction using solid plane techniques; (2) characteristic impedance variations caused by inconsistent orientation to reference planes; (3) uneven adhesive distribution in mesh reference constructs; (4) cross-talk resulting from signal-to-mesh orientation and dielectric separation; (5) material alternatives to lower dielectric loss in high-speed applications. View full abstract»

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  • Constrained collapse solder joint formation for wafer-level-chip-scale packages to achieve reliability improvement

    Page(s): 1479 - 1485 Vol.2
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    Wafer-level-chip-scale-packages (WLCSP) are rapidly proving to be the package of choice for portable electronics applications. National Semiconductor's micro SMD package family has been a front-runner in the development of this package type. These packages have a proven reliability in the lower pin-count range (up to 36 I/O) when used in conjunction with standard surface mount assembly (SMT). However, extending this technology to higher pin-counts is a significant challenge. Since the preferred assembly method is to not employ an additional underfill step after reflow soldering, the options available to enhance the package reliability are limited. Several options including a pre-applied epoxy layer that will flow and form the underfill layer during solder reflow are under investigation as a potential solution. This approach has constraints in terms of compatibility with flux type used and the reflow profile used. Another approach involves creating a non-reflowable underfill layer. This is the approach described in this paper, and it has proven to work with all commercial assembly processes and to all extents and purposes is transparent to the surface mount assembly method used. This approach is based on the creation of an epoxy layer in either a film or paste layer form that acts as a layer surrounding and partially submerging the solder bumps. This layer achieves two results that directly impact the reliability of the WLCSP assembly. The primary advantage is the increase in solder joint height achieved, which improves the fatigue life when subjected to thermal excursions. The other major advantage is that with the solder bump being constrained from collapsing completely, the angle of wetting formed on the die side is increased, resulting in a more 'cylindrical' or barrel-shaped joint rather than a shape like a truncated sphere. Finite element modeling (P. Borgesen et al., IEEE Trans. on Comp., Hybrids, and Manuf. Tech., vol. 16, no. 3, pp. 272-283) has also borne out that a higher wetting angle results in higher reliability. There also appears to be an interaction between the pre-applied underfill layer thickness and the reliability of the outermost solder joint, which itself depends on the bump matrix size. A higher stand-off may not necessarily translat- e to a higher reliability due to this interaction effect. View full abstract»

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  • Micromachined double-side 45° silicon reflectors for dual-wavelength DVD optical pickup heads

    Page(s): 1390 - 1395 Vol.2
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    This paper presents hybrid integration of a dual-wavelength laser module using silicon optical benches with double-side 45° micro reflectors fabricated by bulk micromachining technology for DVD optical pickup head applications. The reflector angles are precisely controlled within 45±1°, and the surface roughness of the micro reflectors are less than 20 nm. Two bare chips of edge-emitting laser diodes (LDs), having wavelengths of 650 nm and 780 nm, with their monitor photo diodes were integrated face-to-face using the local-heating method. These two edge-emitting beams are bent vertically by the double-side micro reflectors, and the effective beam separation can be reduced to 75 μm readily. The reflection efficiency of the micro reflectors was higher than 95%, and the effective numerical aperture of the reflector is 0.3. The patterns of focused spots show that the surfaces of the micro reflectors are optically flat planes, which are suitable for optical recording applications. View full abstract»

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  • Fabrication and parametric study of wafer-level multiple-copper-column interconnect

    Page(s): 1251 - 1255 Vol.2
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    Electronic packaging technology lags behind the rapidly developing semiconductor technology, and as a result the package has become the limiting factor for microsystem performance. A critical aspect of package performance is the reliability of chip-to-next-level interconnects. This paper presents some initial fabrication and simulation results of a compliant interconnect scheme, which features multiple copper columns in a single interconnect and is expected to demonstrate high thermomechanical reliability as predicted by a simplified model. Prototype interconnects with pitch of 40 μm have been realized based on wafer-level processes such as photolithography and electrolytic plating. Simulation tools such as Ansys and Ansoft's Q3D are employed to compare mechanical and electrical performance of multi-copper-column (MCC) and single-copper-column (SCC) interconnect that has been available in the market. Parametric studies are implemented to investigate the geometric effects of MCC interconnects on their performances. View full abstract»

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  • Wetting interaction between Pb-free Sn-Zn series solders and Cu, Ag substrates

    Page(s): 1310 - 1313 Vol.2
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    This study investigated the wetting behavior of Cu and Ag with pure Sn and several Sn-Zn solders, including Sn-9Zn (abbreviated as Sn-Zn), Sn-8.55Zn-0.5Al (abbreviated as Sn-Al), and Sn-8.55Zn-0.5Ag-0.1Al-0.5Ga (abbreviated as Sn-Zn-Ag-Al-Ga). Results show that Sn-Zn solders exhibit better wettability with both Cu and Ag than pure Sn. The primary interfacial intermetallics in Sn-Zn are (Ag,Cu)Zn rather than (Ag,Cu)Sn. By way of alloying modification, the Sn-Zn-Ag-Al-Ga alloy exhibits a greater wetting behavior than other solders. View full abstract»

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  • Materials, processes and reliability of mixed-signal substrates for SOP technology

    Page(s): 1630 - 1635 Vol.2
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    Materials, processes and reliability challenges in mixed-signal (Digital, Optical and RF) microvia substrates for System-on-a-package (SOP) technology are presented. Models and methodologies to thermo-mechanically evaluate the microvia substrate reliability are discussed. Upfront process mechanics models with design of simulations approach are presented to evaluate various dielectrics and substrate materials with respect to warpage, dielectric cracking and microvia reliability in multi-layered microvia boards. Systematic optimization studies are conducted to arrive at appropriate set of material and geometry parameters to minimize the inelastic strain in the microvias, the film stress in the dielectric, and the warpage in the substrate. The test vehicles are subjected to liquid-to-liquid thermal shock cycles between -55°C to 125°C to assess reliability and model validation. Material length scale effects due to reduced feature sizes of microvias (10 microns or less) are addressed through computational algorithms to simulate the increased plastic strain hardening effects due to spatial strain gradients. System-level mixed-signal reliability is also discussed taking into consideration component-level reliability as well as statistical implications. View full abstract»

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  • Demonstration of an MT-compatible connectorisation of a laser-ablated optical interconnection on a printed circuit board

    Page(s): 1552 - 1557 Vol.2
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    Integration of optical interconnections on a Printed Circuit Board (PCB) is very challenging, as compatibility should be maintained with standard PCB manufacturing technology. This paper describes the use of laser ablation, a technique already used in PCB manufacturing for drilling microvia's, as a suitable technique for the fabrication of multimode polymer waveguides, micromirrors, alignment features and microlenses. A frequency tripled Nd-YAG laser and a KrF excimer laser are used, both mounted on the same stage, resulting in a very high alignment accuracy. We demonstrate a parallel optical link over about 5 cm long PCB integrated waveguides, fully connectorised using a standard MT-based connector. This proves that laser ablation can be a key technology in optical board manufacturing to reach the stringent coupling tolerances. View full abstract»

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  • Design of CMOS voltage controlled oscillators using package inductor

    Page(s): 1682 - 1686 Vol.2
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    This paper presents three different types of CMOS Voltage-Controlled-Oscillators (VCO) with the integration of embedded inductors in a multi-layer package. A high quality (Q) inductor, pertinent to creating an efficient VCO, is easily made with a thick wiring line in a multi-layer package, The embedded inductors are designed with two different packaging technologies. One is a Fine Pitch Ball Grid Array Packaging (FBGA) technology and the other is a Wafer Level Packaging (WLP) technology. The FBGA inductor showed a Q-factor about 60 at the frequency of 2GHz and that of a WLP inductor was about 25 while at 2GHz. The performances of VCOs using embedded inductors were compared with the control, a VCO designed with conventional on-chip inductors. The use of FBGA and WLP created numerous advantages. The Total Figure-Of-Merit (FOM) was enhanced due to not only reduced phase-noises, but also to improved efficiency and tuning range. View full abstract»

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  • High-frequency characterization of differential signals in a flip-chip organic package

    Page(s): 1796 - 1801 Vol.2
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    As today's off-chip differential busses operate at a few Gbit/s and move to even higher speeds in the future, the chip package interconnect becomes a critical part of the entire signal transmission path. The package performance could determine the maximum frequency that the data can be transferred. The package interconnects have to be designed properly to maintain a constant characteristic impedance in order to minimize reflection and maximize transmission. To characterize the performance of packages, S-parameter measurement is widely used due to its accuracy and large dynamic range. However, a test fixture is usually required to enable the measurement. This paper describes a different method of characterizing the differential signals in a flip-chip organic package. This measurement technique probes the chip mounting pad side of the signal nets and does not require a test fixture. Both S-parameter and time domain reflectometer (TDR) measurements were compared to models extracted from electromagnetic (EM) simulations with good correlation. This technique is efficient, cost effective and provides a fast turn around time for measurements and models validation. View full abstract»

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  • Design and optimization of 3D RF modules, microsystems and packages using electromagnetic, statistical and genetic tools [mm-wave interdigitated passband filter application]

    Page(s): 1412 - 1415 Vol.2
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    The successful use of the design of experiments (DOE) and response surface modeling (RSM) approaches in an optimization study for a multilayer interdigitated passband filter is presented. The medium of interest is liquid crystal polymer (LCP) and the frequency band is in the 60 GHz range. The two figures of merit chosen are the resonating frequency and the quality factor Q with the optimization goals of fo=60 GHz and maximum Q. The electromagnetic performance of the filter is determined with a method of moments commercial simulator. The results of these simulations are incorporated into DOE and RSM techniques, statistical models are developed for the two output variables, and then applied to optimize the filter. The effectiveness of the method is compared to that of the genetic algorithm (GA) optimization. View full abstract»

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  • High reliability second level interconnects using polymer core BGAs

    Page(s): 1443 - 1448 Vol.2
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    The growing need for shorter interconnects for better electrical performance has shifted package designs more and more towards ball grid arrays (PGAs). This has brought into focus the requirement for a reliable second level interconnect. Due to the thermal mismatch between the package material (e.g. ceramic) and the PWB board the solder interconnects are prone to failure during temperature excursions. Increasing the interconnect height by using a larger diameter ball may increase the mechanical reliability, but would compromise the electrical performance. So there needs to be an interconnect solution to getting good reliability without compromising the electrical properties. This paper compares the mechanical reliability and electrical performance of a novel interconnect material with the conventional solder ball. The new solder ball consists of a core of polymer with a thin layer of copper with additional covering of solder which could be either tin/lead based or lead free. Temperature cycling data was obtained from both conventional and polymer core balls tested on ceramic packages mounted on a FR4 board. Weibull data showing the differences are plotted and failure analysis is done on the failed parts to understand the different failure modes between both the types of BGAs. An electrical simulation was done to compare the polymer-core ball with a conventional solder ball. DC resistance analysis and a full-wave electromagnetic RF simulation were performed to compare the two types. View full abstract»

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  • Nanocrystalline copper and nickel as ultra high-density chip-to-package interconnections

    Page(s): 1647 - 1651 Vol.2
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    Nanocrystalline (nc) copper and nickel are being explored as candidate interconnect materials for nanoscale interconnections to meet the requirements of fine pitch, superior electrical and mechanical performance while also catering to the environmental and cost concerns. Bulk nanocrystalline copper and nickel (99.999% purity) specimens of average grain size of about 50 nm were prepared by equichannel angular extrusion (ECAE). Both micro- and nanohardness measurements showed a significant increase in the hardness of the bulk specimens. The grain size analysis shows that copper is stable up to 100°C and the activation energy for grain growth was calculated to be around 35 KJ/mol. The nickel specimens were found to be stable up to 250°C. The tensile strength of these materials has been found to be 5-6 times of the conventional microcrystalline forms and the fracture toughness, JIC, values for nc- copper and nickel have been found to be 21.66 KJ/m2 and 12.13 KJ/m2, respectively, which are high for these strength levels indicating considerable capacity for plastic deformation in these materials prior to fracture. View full abstract»

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  • Reaching detente in the design and material selection for Hi Rel WLCSP's

    Page(s): 1499 - 1505 Vol.2
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    As WLCSP packaging technology travels the road to ubiquity a transition is unfolding. WLCSP designs and material selection paradigms are moving from a process integration focus to one of product integration. The transition is driven by the application of WLCSP technology to larger die and enabled by the improvement in materials properties and process requirements. Both the driver and the enabler are consequences of the relentless pressure on cost that is the hallmark of the recent industry cycle. Achieving the goal of a low cost, high reliability, product-driven package solution required the balancing a variety of needs and characteristics. Often these are in conflict and detente is needed to ease the tension. The design goals of a Hi Rel WLCSP must provide superior protection, mechanical strength and electrical contact. A successful solution necessitated the need to avoid special tools or processes. The solution also needed to exceed the reliability requirements of the end customer. A key component of the WLCSP structure is the dielectric which is interposed between the solder bumps and the die. It must provide most of the protection functions while supporting the bumps and buffering the bump strains. A negative tone, photosensitive polyimide was ultimately selected. This polymer was designed with the goal of achieving thermal and mechanical cured film properties fully compatible with the stresses and thermal excursions associated with WLP thin-film processing and bumping. Integration of the new polymer require careful characterization and process optimization to assure critical material qualities such adhesion were achieved. Similar optimizations were run for assembly operations. Based on test results described herein, a double-layer polyimide, copper redistributed, eutectic SnPb or Pb-free bumped WLCSP was developed that exceeded all the design goals. Salient differentiators of the WLCSP solution are identified. Improved reliability was achieved, and new design standards were established relative to RF capability and power density. View full abstract»

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  • Flipchip bump integrity with copper/ultra low-k dielectrics for fine pitch flipchip packaging

    Page(s): 1636 - 1641 Vol.2
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    As CMOS transistor scaling proceeds into the deep submicron regime, the number of transistors on high performance, high density ICs is increasing to 45∼60 millions, in accordance with the historical trend of Moore's Law. It is the fundamental motivating factor causing the semiconductor industry to move away from aluminum as interconnect metal with silicon dioxide dielectric between the metal lines, to copper metal and ultra-low-k dielectric materials. Copper reduces the resistance of the metal interconnect lines, while low-k dielectrics reduce the parasitic capacitance between the metal lines: The implementation of copper as an interconnect in conjunction with the ultra low-k materials as interlevel dielectrics (ILDs) or intermetal dielectrics (IMDs) in the fabrication of ULSI circuits has been a main stream especially for high speed devices in the semiconductor community worldwide. The impact of UBM integrity in Cu metallization has been reported and major failure mechanism observed were metal peeling from low-k dielectrics. However investigations reported with different chip ILD/IMD stacking structure and with various UBM metallization and failure analysis of the same particularly with ultra low-k dielectrics are very limited. In this work, two different approaches are studied. One is for chip-side stack structure and another is the application of wafer level packaging technology. The bump failure is found at the chip-side, especially, at the interface of ultra low-k dielectrics materials. To increase the bump adhesion properties, different thickness ILDs were deposited and various adhesion promoter layers were evaluated with several stack structures. In order to achieve the proper solder joint reliability in other approach, wafer level integration techniques were applied. Encapsulation of photosensitive low-k dielectrics and BCB (Benzocyclobutene) were carried out on the Cu/ultra-low-k dielectric wafers. According to the characterization, it gave promising results in view point of adhesion, thus, no more chip-side failure is found. The process, assembly steps, test vehicle design and reliability results, failures and analysis will be reported. View full abstract»

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  • Modeling and hardware correlation of power distribution networks for multi-gigabit designs

    Page(s): 1759 - 1765 Vol.2
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    This paper presents simulation and measurement results for package and board power distribution systems of a low cost multi-gigabit design. A modeling methodology aimed to model the entire power distribution system across three different hierarchies of the system from the PCB to the package and to on-chip circuits in a single model is presented. Using this model system trade-offs are demonstrated in the design of the power distribution system of a high-speed memory interface. View full abstract»

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  • Heat spreader impact on electrical performances of a 4-layer PBGA package

    Page(s): 1772 - 1775 Vol.2
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    Electrical simulations are performed for a 4-layer 388-ball PBGA package to investigate the heat spreader (HS) impact on electrical performances at high frequencies. The results show that a heat spreader, no matter floating or grounded, can help to minimize both the self and mutual inductances in a relatively low frequency range. However, a grounded HS can help to maximize the signal transmission efficiency due to low losses. In addition, grounding the HS mitigates the electromagnetic interference (EMI) issues that may occur in a floating HS case at high frequencies and at the same time helps to push the self-resonant frequency of the package to a higher value, which effectively widens the bandwidth of the package. View full abstract»

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  • Process issues and characterization of LTCC substrates

    Page(s): 1933 - 1937 Vol.2
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    The interconnection for high density multilayer LTCC assembly requires via formation with precise via fill printing. Via formation down to 4 mil was accomplished by mechanical punching followed by via filling using high accuracy stencil printing. The print quality was studied by various manufacturing parameters for screen printing and important material characteristics, to achieve 4 mil line width. The collating process is critical to ensure the alignment of via holes. This can be accomplished by a simple fixture with alignment pins technique. Stacking holes on LTCC tape punched prior to the printing operation was compared with post punching after printing and drying operation. Upon successful stacking, good vacuum sealing was achieved. The sealing process was optimised to enable good lamination. Then firing profiles were investigated using two type of furnaces. A two stage process for debinding and sintering profiles combined with proper setter configuration resulted in defect free final product using a belt-type furnace. Similar results were achieved by using a single debinding profile in a box furnace followed by sintering profile in a belt-type furnace. The importance of using proper setters and setter arrangements is emphasized for the debinding and sintering process. View full abstract»

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  • Conductivity improvement of isotropic conductive adhesives with short-chain dicarboxylic acids

    Page(s): 1959 - 1964 Vol.2
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    With the phasing out of lead-bearing solders, electrically conductive adhesives (ECAs) have been identified as an environmentally friendly alternative to tin/lead (Sn/Pb) solders in electronics packaging applications. Compared to Sn/Pb solders, conductive adhesive technology offers numerous advantages. However, as a new technology, conductive adhesive technology still has many concerns and limitations. In order for conductive adhesive technology to achieve universal acceptance, ECAs with better properties must be developed. The purpose of this study is to increase the conductivity of conductive adhesives by using short chain dicarboxylic acids, since such acids can partially remove or can completely replace the C-18 stearic acid which are commonly used as the surfactant in Ag flakes manufacturing process. Malonic acid and adipic acid, which only have single-bond short chain hydrocarbon between the dicarboxylic groups, increase the conductivity of conductive adhesives greatly. Terephthalic acid, however, deteriorates the conductivity due to the rigid aromatic structure in the molecule. The stabilized contact resistance has also been achieved with the introduction of dicarboxylic acids. Most importantly, the significant improvement of electrical properties is achieved without adversely affecting the physical and mechanical properties of the ICAs. View full abstract»

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  • Circuit partitioning and RF isolation by through-substrate trenches

    Page(s): 1519 - 1523 Vol.2
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    In this work, theoretical and experimental analysis of RF crosstalk suppression by substrate thinning and trenching is performed. Medici (2D solver) simulation results show that high isolation can be achieved by using high resistivity thinned substrate and through-substrate trenches. Measurements on dedicated G-S-G test structures implemented on thinned Si substrates (thickness 20-100 μm) with and without through-substrate trenches (trench width 5-100 μm) show that isolation between two single-ended capacitive substrate contacts can effectively be controlled by these trenches. While the partial trenches provide additional isolation of ∼10 dB at 1 GHz, the full trenches (forming isolated silicon islands) provide additional isolation of ∼30 dB at 1 GHz. View full abstract»

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  • Process and design analysis for ultra fine-pitched wiresweep elimination in advanced copper heat spreader BGA package

    Page(s): 1454 - 1460 Vol.2
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    The semiconductor device trend for increasing functionalities and performances yet with smaller overall feature sizes presents escalating obstacles to the decreasing form factor along with demanding thermal carrying capability required at the package level. To confront this compounding issue, ultra fine pitch wirebond interconnect coupled with thermally enhanced copper heat spreader attached to the package are introduced. But the additional copper heat spreader thickness introduced within the package challenges the design of the package's wire, its loop height, and the molding process control to prevent wire sweeping occurrences. This study investigates the impact of different ultra fine pitched wire types, wire loop designs, copper heat spreader structures, and mold material types on eliminating device short from occurring due to the wire sweeping phenomena. A full factorial experiment is performed using an active silicon device packaged in a thermally enhanced BGA test vehicle. In addition, test characterization is carried out using X-ray and multi-insertions hot/cold continuity tests. Then, a detailed failure analysis is performed by chemical decapsulation to confirm the experimental findings. In conclusion, the study finds that for an ultra fine pitched thermally enhanced BGA package, wire type is insignificant to reduce wire shorting occurrences. However, mold material and copper heat spreader structure using an optimized wire loop design are significant factors in eliminating wiresweep shorting phenomena. This study concludes,with a Wirebond interconnect and heat slug design recommended along with an improved process parameters and assembly material sets found from the experiment. View full abstract»

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  • Active devices and wiring under chip bond pads: stress simulations and modeling methodology

    Page(s): 1784 - 1787 Vol.2
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    In the semiconductor industry, cost competitiveness can be significantly improved by maximizing the use of chip real estate. For wire-bonded chips, vacant space under the bond pads can be populated with active devices and wiring known as structures under pads (SUPs). Although this layout strategy can improve productivity, reliability issues concerning stresses from the wire-bonding loads must be resolved before population can occur. The necessary qualification work, including designing, building, and stressing test sites, can become very costly if it attempts to cover all possible SUP layouts. Mechanical simulations using finite element analysis (FEA) software can play a critical role in reducing the cycle time and qualification cost by predicting the wire-bonding stresses for different SUP layouts. Knowledge gained from FEA models can be used throughout the qualification process: early on to design the test site and later on to interpret the test results and bridge them to other technologies or die configurations. To achieve these time and cost savings, a set of simulations must be properly defined and interpreted. This paper discusses mechanical modeling performed in conjunction with an SUP qualification effort at IBM. We describe the modeling methodology as well as the effects of different layout variables on the stress distribution. View full abstract»

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  • Reliability of large organic flip-chip packages for industrial temperature environments

    Page(s): 1802 - 1806 Vol.2
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    This paper focuses on the thermal fatigue reliability of fine pitch flip-chip BGA packages employing multi-layer organic built-up substrates with an integral heat spreader. For high density FPGA devices, the die size and package footprint are larger than the prevailing industry standard, this poses a significant challenge for meeting component level temperature cycle condition B (-55°C to +125°C) reliability requirements. FEM is a key component for identifying high stress regions and identifying solutions to long term reliability problems. FEM was used to study two different material combinations where the heat spreader/stiffener attach adhesive and thermal interface materials (TIM) were changed. Temperature cycle tests were performed on both material sets. A secondary goal of this study was to evaluate the effects of the substrate land pad geometry and moisture preconditioning. The temperature cycle test lots were built with both solder mask defined (SMD) and non-solder mask defined (NSMD) pads and the test lots were subjected to two different levels of moisture preconditioning (JEDEC levels 3 and 4). Temperature cycle reliability results have been presented and substantiated by the FEM prediction and observed failure modes. View full abstract»

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  • Electroplated Sn-Au structures for fabricating fluxless flip-chip Sn-rich solder joints

    Page(s): 1642 - 1646 Vol.2
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    A fluxless bonding process in hydrogen environment based on newly introduced Sn-Au electroplated multilayer that is highly Sn-rich is presented. Electroplating method is an economical alternative to vacuum deposition method in many soldering applications that require thicker solder joints. Non-eutectic Sn-rich Sn-Au multilayer design with 94 at. % Sn and 6 at. % Au are employed. Microstructure and phase formation of electroplated Sn-Au thin films are investigated using X-ray diffraction method (XRD), Scanning Electron Microscope (SEM), and Energy Dispersive X-ray Spectroscopy (EDX). The joints produced are also examined using these techniques. It is found that the small Sn-Au intermetallic compound (AuSn4) grains are uniformly distributed in Sri matrix. Some voids are identified by a Scanning Acoustic Microscope (SAM). The remelting temperature of the joints ranges in 217 ∼ 222°C. Highly Sn-rich Sn-Au solder bumps are fabricated by plating through thickness photoresist pattern to develop fluxless flip-chip bonding technique. Thicker bumps (over 50 μm) have been produced. This new fluxless bonding process is the first fluxless bonding technology that was successfully achieved by electroplating within author's knowledge. View full abstract»

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