# IEEE Transactions on Very Large Scale Integration (VLSI) Systems

## Issue 3 • March 2018

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## Filter Results

Displaying Results 1 - 22 of 22

Publication Year: 2018, Page(s):C1 - C4
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• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Publication Year: 2018, Page(s): C2
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• ### Approximate Hybrid High Radix Encoding for Energy-Efficient Inexact Multipliers

Publication Year: 2018, Page(s):421 - 430
| |PDF (2163 KB) | HTML

Approximate computing forms a design alternative that exploits the intrinsic error resilience of various applications and produces energy-efficient circuits with small accuracy loss. In this paper, we propose an approximate hybrid high radix encoding for generating the partial products in signed multiplications that encodes the most significant bits with the accurate radix-4 encoding and the least... View full abstract»

• ### Resource-Efficient Object-Recognition Coprocessor With Parallel Processing of Multiple Scan Windows in 65-nm CMOS

Publication Year: 2018, Page(s):431 - 444
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Object recognition offers a more general implementation for vision-based applications. This paper reports a resource-efficient recognition coprocessor with embedded cell-based simplified speeded up robust feature descriptor extraction unit and parallel scan-window (SW) recognition engine, applicable for various mobile scenarios and image sensor types. The feature extraction circuitry with pixel-ba... View full abstract»

• ### Rapid Memory-Aware Selection of Hardware Accelerators in Programmable SoC Design

Publication Year: 2018, Page(s):445 - 456
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Programmable Systems-on-Chips (SoCs) are expected to incorporate a larger number of application-specific hardware accelerators with tightly integrated memories in order to meet stringent performance-power requirements of embedded systems. As data sharing between the accelerator memories and the processor is inevitable, it is of paramount importance that the selection of application segments for ha... View full abstract»

• ### Fine-Grained Energy-Constrained Microprocessor Pipeline Design

Publication Year: 2018, Page(s):457 - 469
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Energy-constrained microprocessor design plays an important role in many emerging Internet of Things platforms operating on harvested or limited energy budget. For this purpose, operating at the supply voltage corresponding to the minimum energy point (MEP) can achieve significant energy savings. However, the MEP voltage is highly dependent on the threshold voltage, the structure, and the activity... View full abstract»

• ### Computing in Memory With Spin-Transfer Torque Magnetic RAM

Publication Year: 2018, Page(s):470 - 483
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In-memory computing is a promising approach to addressing the processor-memory data transfer bottleneck in computing systems. We propose spin-transfer torque compute-in-memory (STT-CiM), a design for in-memory computing with spin-transfer torque magnetic RAM (STT-MRAM). The unique properties of spintronic memory allow multiple wordlines within an array to be simultaneously enabled, opening up the ... View full abstract»

• ### An Adaptive 3T-3MTJ Memory Cell Design for STT-MRAM-Based LLCs

Publication Year: 2018, Page(s):484 - 495
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The STT-MRAM technology is a promising candidate for future on-chip cache memory because of its high density, low standby power, and nonvolatility. As the technology node scales, especially under 40-nm technology node, STT-MRAM cell design becomes a key issue to approach low power consumption, high access performance, and desirable reliability. The conventional 1T-1 magnetic tunnel junction (MTJ) ... View full abstract»

• ### Basic-Set Trellis Min–Max Decoder Architecture for Nonbinary LDPC Codes With High-Order Galois Fields

Publication Year: 2018, Page(s):496 - 507
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Nonbinary low-density parity-check (NB-LDPC) codes outperform their binary counterparts in terms of error-correction performance. However, the drawback of NB-LDPC decoders is high complexity, especially for the check node unit (CNU), and the complexity increases considerably when increasing the Galois-field (GF) order. In this paper, a novel basic-set trellis min–max algorithm is proposed t... View full abstract»

• ### Analysis and Design of Cost-Effective, High-Throughput LDPC Decoders

Publication Year: 2018, Page(s):508 - 521
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This paper introduces a new approach to cost-effective, high-throughput hardware designs for low-density parity-check (LDPC) decoders. The proposed approach, called nonsurjective finite alphabet iterative decoders (NS-FAIDs), exploits the robustness of message-passing LDPC decoders to inaccuracies in the calculation of exchanged messages, and it is shown to provide a unified framework for several ... View full abstract»

• ### A 12.5-Gb/s Near-Ground Transceiver Employing a MaxEye Algorithm-Based Adaptation Technique

Publication Year: 2018, Page(s):522 - 530
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A 12.5-Gb/s complete near-ground transceiver is demonstrated. The output stage of the transmitter (TX) employs 2-tap finite-impulse response equalization (EQ) and also performs ac-coupled EQ for an additional EQ. A continuous-time linear equalizer (CTLE) on the receiver (RX) side compensates for the channel attenuation. Based on the maximum eye algorithm, the peaking gain of CTLE is adaptively con... View full abstract»

• ### Recovery-Aware Proactive TSV Repair for Electromigration Lifetime Enhancement in 3-D ICs

Publication Year: 2018, Page(s):531 - 543
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Electromigration (EM) becomes a major reliability concern in 3-D integrated circuits (3-D ICs). To mitigate this problem, a typical solution is to use through-silicon via (TSV) redundancy in a reactive manner, maintaining the operability of a 3-D chip in the presence of EM failures by detecting and replacing faulty TSVs with spares. In this paper, we explore an alternative, more preferred approach... View full abstract»

• ### Algorithmic Optimization of Thermal and Power Management for Heterogeneous Mobile Platforms

Publication Year: 2018, Page(s):544 - 557
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State-of-the-art mobile platforms are powered by heterogeneous system-on-chips that integrate multiple CPU cores, a GPU, and many specialized processors. Competitive performance on these platforms comes at the expense of increased power density due to their small form factor. Consequently, the skin temperature, which can degrade the experience, becomes a limiting factor. Since using a fan is not a... View full abstract»

• ### A DC-to-1-GHz Continuously Tunable Bandpass ADC

Publication Year: 2018, Page(s):558 - 571
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This paper proposes a dc-to-1-GHz continuously tunable bandpass (BP) analog-to-digital converter (ADC). The tunability is realized by modifying the pipelined ADC-based $f_{S}/4$ BP-ADC. A passive switched capacitor-based error-delaying circuitry is used to delay the quantization noise generated by a pipelined ADC by programma... View full abstract»

• ### A 16-mW 1-GS/s With 49.6-dB SNDR TI-SAR ADC for Software-Defined Radio in 65-nm CMOS

Publication Year: 2018, Page(s):572 - 583
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This paper presents a 10-bit 1-GS/s four-channel time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC). To suppress the time skew, the full rate master clock-based sampling technique is adopted. The effect of sampling switch mismatches on time skew is addressed. The measured time skew spurs caused by the sampling switch mismatches are around −52 to ... View full abstract»

• ### Average 7T1R Nonvolatile SRAM With R/W Margin Enhanced for Low-Power Application

Publication Year: 2018, Page(s):584 - 588
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A new average 7T1R nonvolatile SRAM for low-power application is presented in this brief, which improves the read and write margin (RM/WM), as well as the restore energy, simply by using the source switch transistor. Simulation results demonstrate that the RM and WM will be improved by ~23% and ~73%, respectively, and the energy consumption will be decreased by ~... View full abstract»

• ### Low Phase Noise Ku-Band VCO With Optimal Switched-Capacitor Bank Design

Publication Year: 2018, Page(s):589 - 593
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In this brief, a low phase noise Ku-band voltage-controlled oscillator (VCO) fabricated in a 130-nm BiCMOS process is presented. The phase noise mechanism of the switched-capacitor bank is analyzed, an optimum bank design to reduce phase noise is proposed, and a tradeoff with tuning range is discussed. The prototype 12.2–13.1-GHz VCO achieves a measured phase noise of −120.6 dBc/Hz a... View full abstract»

• ### Analog Layout Retargeting With Process-Variation-Aware Hybrid OPC

Publication Year: 2018, Page(s):594 - 598
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For high-quality analog layout retargeting, in this brief we propose a hybrid optical proximity correction (OPC) methodology, which features special handling against geometry manufacturing deviation caused by process variation (PV). Based on the unique nature of analog layouts, accuracy limitation of the rule-based OPC (RB-OPC) is compensated by geometry preprocessing operations in our proposed la... View full abstract»

• ### A 0.013-mm2 0.53-mW/Gb/s 32-Gb/s Hybrid Analog Equalizer Under 21-dB Channel Loss in 65-nm CMOS

Publication Year: 2018, Page(s):599 - 603
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Low-power and low-jitter equalization techniques become increasingly crucial for the wire-line receivers operating at data rates more than tens of gigabits per second. This brief reports an inductorless and power-efficient 32-Gb/s hybrid analog equalizer. The hybrid analog equalizer utilizes a triple-gate control to achieve equalization over a range of channel loss resulting in an inductorless and... View full abstract»

• ### Temperature Sensitivity and Compensation on a Reconfigurable Platform

Publication Year: 2018, Page(s):604 - 607
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This brief investigates temperature compensation techniques for circuits and systems on a reconfigurable platform. The work demonstrates use of large-scale reconfigurable system-on-chip for reducing the variability of circuits and systems compiled on a floating gate (FG)-based field-programmable analog array (FPAA). The work presents current and voltage reference which could help in reducing the v... View full abstract»

• ### IEEE Access

Publication Year: 2018, Page(s): 608
| |PDF (519 KB)
• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Publication Year: 2018, Page(s): C3
| |PDF (46 KB)

## Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu