# IEEE Transactions on Very Large Scale Integration (VLSI) Systems

## Filter Results

Displaying Results 1 - 25 of 31

Publication Year: 2017, Page(s):C1 - C4
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• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Publication Year: 2017, Page(s): C2
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• ### Guest Editorial Securing IoT Hardware: Threat Models and Reliable, Low-Power Design Solutions

Publication Year: 2017, Page(s):3265 - 3267
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• ### Using Scan Side Channel to Detect IP Theft

Publication Year: 2017, Page(s):3268 - 3280
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In the growing heterogeneous Internet of Things market, which embraces a plurality of vendors and service providers, IP protection plays a central role. This paper proposes a process for the detection of IP theft in VLSI devices that exploits the internal test scan chains, designed for production test automation. The scan chains supply direct access to the internal registers in the device, enablin... View full abstract»

• ### AES Datapath Optimization Strategies for Low-Power Low-Energy Multisecurity-Level Internet-of-Things Applications

Publication Year: 2017, Page(s):3281 - 3290
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Connected devices are getting attention because of the lack of security mechanisms in current Internet-of-Thing (IoT) products. The security can be enhanced by using standardized and proven-secure block ciphers as advanced encryption standard (AES) for data encryption and authentication. However, these security functions take a large amount of processing power and power/energy consumption. In this... View full abstract»

• ### Securing the PRESENT Block Cipher Against Combined Side-Channel Analysis and Fault Attacks

Publication Year: 2017, Page(s):3291 - 3301
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In this paper, we present and evaluate a hardware implementation of the PRESENT block cipher secured against both side-channel analysis and fault attacks (FAs). The side-channel security is provided by the first-order threshold implementation masking scheme of the serialized PRESENT proposed by Poschmann et al. For the FA resistance, we employ the Private Circuits II countermeasur... View full abstract»

• ### A Flexible Wildcard-Pattern Matching Accelerator via Simultaneous Discrete Finite Automata

Publication Year: 2017, Page(s):3302 - 3316
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Regular expression matching becomes indispensable elements of Internet of Things network security. However, traditional ternary content addressable memory (TCAM) search engine is unable to handle patterns with wildcards, as it precisely tracks only one active state with single transition. This paper proposes a promising simultaneous pattern matching methodology for wildcard patterns by two separat... View full abstract»

• ### An On-Chip Technique to Detect Hardware Trojans and Assist Counterfeit Identification

Publication Year: 2017, Page(s):3317 - 3330
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This paper introduces an embedded solution for the detection of hardware trojans (HTs) and counterfeits. The proposed method, which considers that HTs are necessarily inserted on production lots and not on a single device, is based on the fingerprinting of the static distribution of the supply voltage ( $V_{mathrm{ dd}}$ ) over... View full abstract»

• ### Chaotic Encrypted Polar Coding Scheme for General Wiretap Channel

Publication Year: 2017, Page(s):3331 - 3340
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A wiretap channel is an important model for wireless communication. By applying an extended multiblock polar coding scheme, recent literature has achieved the secrecy capacity of a general wiretap channel (not necessary degraded or symmetric). However, this secure polar coding scheme of physical layer also limits the transmission rate of the main channel, which may fail to meet the demand of high ... View full abstract»

• ### ULV-Turbo Cache for an Instantaneous Performance Boost on Asymmetric Architectures

Publication Year: 2017, Page(s):3341 - 3354
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An asymmetric architecture is commonly used in modern embedded systems to reduce energy consumption. The systems tend to execute more applications in the energy-efficient core, which typically employs ultralow voltage (ULV) to save energy. However, caches become a reliability and performance barrier that limits the minimum operating voltage and blocks system performance in the ULV environment. The... View full abstract»

• ### Energy-Efficient Side-Channel Attack Countermeasure With Awareness and Hybrid Configuration Based on It

Publication Year: 2017, Page(s):3355 - 3368
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Energy-efficient countermeasures to side-channel attacks are required for Internet of Things hardware. This paper proposes a special hiding technique for the substitution operation in block ciphers, which equalizes the power consumption of a circuit by appropriate feedforward compensation and is called power-aware hiding (PAH). A hybrid application configuration, in which PAH is applied to the S-b... View full abstract»

• ### A Process-Independent and Highly Linear DCO for Crowded Heterogeneous IoT Devices in 65-nm CMOS

Publication Year: 2017, Page(s):3369 - 3379
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The Internet of Things (IoT) devices are manufactured under different fabrication quality standards, considering the wide variety of vendors. As a result, global process variations in the IoT system-on-chip (SoC) are an enormous concern that can affect reliability of the device. Among the components in a typical SoC, oscillator is the most susceptible element to process variations. This paper prop... View full abstract»

• ### Vulnerability Analysis of Trivium FPGA Implementations

Publication Year: 2017, Page(s):3380 - 3389
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Today, the large amount of information exchanged among various devices as well as the growth of the Internet of Things (IoT) demand the development of devices that ensure secure communications, preventing malicious agents from tapping sensitive data. Indeed, information security is one of the key challenges to address within the IoT field. Due to the strong resource constraints in some IoT applica... View full abstract»

• ### Automatic Code Converter Enhanced PCH Framework for SoC Trust Verification

Publication Year: 2017, Page(s):3390 - 3400
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The wide usage of hardware intellectual property cores from untrusted vendors has raised security concerns for system designers. Existing solutions for functionality testing and verification do not usually consider the presence of malicious logic in hardware. Formal methods provide powerful solutions for detecting malicious behaviors in hardware. However, they suffer from scalability issues and ca... View full abstract»

• ### Multiradix Trivium Implementations for Low-Power IoT Hardware

Publication Year: 2017, Page(s):3401 - 3405
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The integration of lightweight symmetric encryption is becoming increasingly widespread in very low-power Internet of Things applications, with the rapid emergence of very low energy block and stream ciphers in portable and wireless systems. Trivium is one of the lightweight stream ciphers shortlisted for the hardware profile of the eSTREAM project. This paper describes low-power multiradix Triviu... View full abstract»

• ### Are Proximity Attacks a Threat to the Security of Split Manufacturing of Integrated Circuits?

Publication Year: 2017, Page(s):3406 - 3419
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Split manufacturing is a technique that allows manufacturing the transistor-level and lower metal layers of an integrated circuit (IC) at a high-end, untrusted foundry, while manufacturing only the higher metal layers at a smaller, trusted foundry. Using split manufacturing is only viable if the untrusted foundry cannot reverse engineer the higher metal layer connections (and thus the overall IC d... View full abstract»

• ### Security Beyond CMOS: Fundamentals, Applications, and Roadmap

Publication Year: 2017, Page(s):3420 - 3433
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Hardware-oriented security and trust has traditionally relied on the dominant CMOS technology to develop security primitives and provide protection against different attacks and vulnerabilities. With CMOS nearly reaching its fundamental scaling limit and the shortcomings of current solutions, researchers are now looking to exploit emerging nanoelectronic devices for various security applications. ... View full abstract»

• ### An 11-bit 100-MS/s Subranged-SAR ADC in 65-nm CMOS

Publication Year: 2017, Page(s):3434 - 3443
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This paper presents an 11-bit successive approximation register (SAR) analog-to-digital converter (ADC). The subranged-SAR ADC architecture is applied to achieve a sampling rate of 100 MHz. The proposed gain error compensation helps attenuate the gain error between coarse and fine ADCs. An up-then-down digital-to-analog converter (DAC) switching scheme is used to maintain a small common-mode varia... View full abstract»

• ### A 400-MS/s 10-b 2-b/Step SAR ADC With 52-dB SNDR and 5.61-mW Power Dissipation in 65-nm CMOS

Publication Year: 2017, Page(s):3444 - 3454
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We present a single-channel 10-b 400-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) embodying a proposed 2-b/step conversion scheme with single reference voltage for the IEEE 802.11ac. By means of the said scheme, the proposed ADC requires only three capacitor arrays instead of at least four capacitor arrays in other capacitor digital-to-analog converter-based 2-b/s... View full abstract»

• ### A 20-nW 0.25-V Inverter-Based Asynchronous Delta–Sigma Modulator in 130-nm Digital CMOS Process

Publication Year: 2017, Page(s):3455 - 3463
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This paper presents a new inverter-based architecture that implements an asynchronous delta–sigma modulator. Different from the classical architecture, it features an input transconductor that promotes a differential and high input impedance that makes it easier to interface with sensors and other front ends. Furthermore, an inverter-based relaxation oscillator accomplishes the required hys... View full abstract»

• ### Impact and Mitigation of Sense Amplifier Aging Degradation Using Realistic Workloads

Publication Year: 2017, Page(s):3464 - 3472
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Designers typically add design margins to compensate for time-zero variability (due to process variation) and time-dependent (due to, e.g., bias temperature instability) variability. These variabilities become worse with scaling, which leads to larger design margin requirements. As an alternative, mitigation schemes can be applied to counteract the variability. This paper investigates the impact o... View full abstract»

• ### A 32-nm Subthreshold 7T SRAM Bit Cell With Read Assist

Publication Year: 2017, Page(s):3473 - 3483
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The implementation of the six-transistor (6T) static random access memory cell in deep submicrometer region has become difficult due to the compromise between area, power, and performance, with local and global variations only exacerbating the problem further. To impede the read–write conflict of the 6T cell, the seven-transistor (7T) cell with a noise-margin-free read operation has previou... View full abstract»

• ### Embedded DRAM-Based Memory Customization for Low-Cost FFT Processor Design

Publication Year: 2017, Page(s):3484 - 3494
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In this paper, we present embedded dynamic random access memory (eDRAM)-based memory customization techniques for low-cost fast Fourier transform (FFT) processor design. The main idea is based on the observation that the FFT processor has regular and predictable memory access patterns, and it can be efficiently exploited for memory customization using eDRAM. The memory customization approaches are... View full abstract»

• ### Enabling High-Performance SMART NoC Architectures Using On-Chip Wireless Links

Publication Year: 2017, Page(s):3495 - 3508
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Traditional network-on-chip (NoC) interconnects follow conventional packet switching architectures that require multiple cycles to traverse each router hop. In addition, commonly used NoCs lack low-latency multicast replication and acknowledgment aggregation mechanisms that are required to efficiently handle the collective communication requirements exhibited by many modern applications. To addres... View full abstract»

• ### Design of Low-Voltage High-Speed CML D-Latches in Nanometer CMOS Technologies

Publication Year: 2017, Page(s):3509 - 3520
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This paper presents the design of a novel low-voltage high-speed D-latch circuit suitable for nanometer CMOS technologies. The proposed topology is compared against the low-voltage triple-tail D-latch and its advantages are demonstrated both by simulations, under different performance/power consumption tradeoffs with a 40-nm CMOS technology, and theoretically, thanks to a simple model of the propa... View full abstract»

## Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

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## Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu