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[1993] Proceedings IEEE Workshop on FPGAs for Custom Computing Machines

5-7 April 1993

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  • Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines

    Publication Year: 1993
    Cited by:  Papers (1)
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    Freely Available from IEEE
  • Text searching on Splash 2

    Publication Year: 1993, Page(s):172 - 177
    Cited by:  Papers (17)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (476 KB)

    The paper proposes a flexible, reprogrammable hardware solution to the acceleration of text-based keyword search problems. In these problems, a stream of input text is checked against a known list of keywords (a dictionary) for occurrences of those keywords in the text. The authors' solution employs an attached processor called Splash 2, which exploits the speed and reconfigurability of field prog... View full abstract»

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  • The CM-2X: a hybrid CM-2/Xilinx prototype

    Publication Year: 1993, Page(s):121 - 130
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (588 KB)

    This paper describes the CM-2X prototype. This one-of-a-kind machine is the result of a Supercomputing Research Center/Thinking Machines Corporation joint effort to examine the suitability of a hybrid combination of CM-2 architecture and Xilinx programmable gate array technology. In addition to a description of the CM-2X and Xilinx architecture, a simple applications example is provided that illus... View full abstract»

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  • A digit-recurrence square root implementation for field programmable gate arrays

    Publication Year: 1993, Page(s):178 - 183
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (404 KB)

    Creating efficient arithmetic processors requires a pairing of high speed arithmetic algorithms with optimal mapping strategies for a given technology. The authors propose bit reduction as key to an efficient pairing process for lookup table based field programmable gate arrays (FPGAs). Bit reduction simplifies the functions defining the original algorithm, thus permitting a mapping to fewer block... View full abstract»

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  • Architectural tradeoffs in field-programmable-device-based computing systems

    Publication Year: 1993, Page(s):152 - 161
    Cited by:  Papers (30)  |  Patents (39)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (584 KB)

    Reprogrammable Field-Programmable Gate Arrays (FPGAs) have enabled the realization of high-performance and affordable reconfigurable computing engines. The authors examine the architectural tradeoffs involved in designing general purpose FPGA-based computing systems with field-programmable gate arrays and field-programmable interconnects. The fact that FPGAs provide both programmable logic and pro... View full abstract»

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  • Reconfigurable multi-bit processor for DSP applications in statistical physics

    Publication Year: 1993, Page(s):103 - 110
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (536 KB)

    A PC-AT hosted DSP processor architecture implemented in SRAM-based field programmable gate arrays (FPGA) and static memories is described. Despite its simplicity, the processor circuits can be reconfigured under software control to tackle a class of multi-bit `pixel' processing problems of current interest in the statistical physics of disordered materials, thereby offering some of the problem fl... View full abstract»

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  • High performance analysis and control of complex systems using dynamically reconfigurable silicon and optical fiber memory

    Publication Year: 1993, Page(s):132 - 141
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (884 KB)

    M is a highly parallel asynchronous computer for the analysis and control of complex systems. A complex system is a system with many interacting components. Examples of complex systems include applications in molecular biology, economics, and signal processing. M asynchronous computations reproduce the structural dynamics of a system using high fidelity behavioral modeling. Programs are composed o... View full abstract»

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  • Realising massively concurrent systems on the SPACE machine

    Publication Year: 1993, Page(s):26 - 32
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (500 KB)

    Highly concurrent systems occur frequently in the physical world. This paper focuses on a class of systems characterised as being highly concurrent and which are composed out of many simple parts which interact with other parts in their locality. It discusses how to describe these systems and introduces a cellular automata type of architecture which is used to simulate these systems directly in ha... View full abstract»

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  • Virtual computing and the Virtual Computer

    Publication Year: 1993, Page(s):43 - 48
    Cited by:  Papers (38)  |  Patents (62)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB)

    Virtual computing is an entirely new form of supercomputing that allows an algorithm to be implemented in hardware. Based on the Xilinx FPGA and ICube's FPID the Virtual Computer is completely reconfigurable in every respect. Computing machines based on reconfigurable logic are hyper-scalable meaning they scale up better than 1-1 View full abstract»

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  • Fine grain parallelism on a MIMD machine using FPGAs

    Publication Year: 1993, Page(s):2 - 8
    Cited by:  Papers (10)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB)

    The article presents the use of an FPGA chip (Xilinx 3090) to set up a fast systolic communication agent on a linear asynchronous network of transputer processors; the machine is called ArMen. The authors' work relies on the systolic programming environment ReLaCS, a close cousin to the C programming language. ReLaCS provides synchronous communication operators to simplify the programming of data ... View full abstract»

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  • A field programmable accelerator for compiled-code applications

    Publication Year: 1993, Page(s):60 - 67
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (552 KB)

    The paper describes a special purpose application accelerator using field programmable gate arrays to accelerate a range of applications. The accelerator is designed to support applications by allowing the user to implement a processor with an instruction set designed for the specific application being accelerated, using specialized instructions to implement critical fragments of the application. ... View full abstract»

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  • Searching genetic databases on Splash 2

    Publication Year: 1993, Page(s):185 - 191
    Cited by:  Papers (78)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB)

    The author describes two systolic arrays for computing the edit distance between two genetic sequences using a well-known dynamic programming algorithm. The systolic arrays have been implemented for the Splash 2 programmable logic array and are intended to be used for database searching. Simulations indicate that the faster Splash 2 implementation can search a database at a rate of 12 million char... View full abstract»

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  • Data-folding in SRAM configurable FPGAs

    Publication Year: 1993, Page(s):163 - 171
    Cited by:  Papers (15)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (632 KB)

    FPGAs which are configured by static RAM can be rapidly changed from one logic configuration to another. This raises the possibility of configuring the logic to implement a function for a specific set of values, i.e. folding the inputs into the logic design. The paper discusses data folding with respect to Algotronix FPGAs, presenting a text searching circuit as an example. This folded circuit sav... View full abstract»

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  • A reconfigurable computer for embedded control applications

    Publication Year: 1993, Page(s):111 - 120
    Cited by:  Papers (3)  |  Patents (22)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (672 KB)

    The authors present a custom computer together with a software environment for rapid implementation of algorithms on reprogrammable hardware. The custom computer is based on FPGA boards embedded in a programmable interconnection network. The transformation of an algorithmic system specification into a configuration file for the FPGAs is supported through a set of high-level and structural synthesi... View full abstract»

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  • Virtual wires: overcoming pin limitations in FPGA-based logic emulators

    Publication Year: 1993, Page(s):142 - 151
    Cited by:  Papers (64)  |  Patents (47)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (728 KB)

    Existing FPGA-based logic emulators only use a fraction of potential communication bandwidth because they dedicate each FPGA pin (physical wire) to a single emulated signal (logical wire). Virtual wires overcome pin limitations by intelligently multiplexing each physical wire among multiple logical wires and pipelining these connections at the maximum clocking frequency of the FPGA. A virtual wire... View full abstract»

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  • FPGA computing in a data parallel C

    Publication Year: 1993, Page(s):94 - 101
    Cited by:  Papers (25)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (496 KB)

    The authors demonstrate a new technique for automatically synthesizing digital logic from a high level algorithmic description in a data parallel language. The methodology has been implemented using the Splash 2 reconfigurable logic arrays for programs written in Data-parallel Bit-serial C (dbC). The translator generates a VHDL description of a SIMD processor array with one or more processors per ... View full abstract»

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  • Spyder: a reconfigurable VLIW processor using FPGAs

    Publication Year: 1993, Page(s):17 - 24
    Cited by:  Papers (29)  |  Patents (45)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB)

    A processor with multiple reconfigurable execution units has been designed and implemented. The reconfigurable execution units are implemented using reprogrammable field programmable gate array (FPGA) chips. The architecture and implementation of this processor are described in detail. An example shows that this reconfigurable processor is able to compute the new state of 100'000'000 cells of Conw... View full abstract»

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  • WASMII: a data driven computer on a virtual hardware

    Publication Year: 1993, Page(s):33 - 42
    Cited by:  Papers (28)  |  Patents (30)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (652 KB)

    Virtual hardware is a technique to realize a large digital circuit with a small real hardware by using an extended Field Programmable Gate Array (FPGA) technology. Several configuration RAM modules are provided inside the FPGA chip, and the configuration of the gate array can be rapidly changed by replacing the active module. Data for configuration are transferred from an off-chip backup RAM to an... View full abstract»

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  • A self-reconfigurable processor

    Publication Year: 1993, Page(s):50 - 59
    Cited by:  Papers (12)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (796 KB)

    Recent developments in the design and fabrication of field programmable logic devices (FPGAs) may well change the way in which one designs and fabricates conventional microprocessors. The use of uncommitted logic whose function may be modified at run time makes the prospect of dynamic application specific integrated circuits closer to reality than ever before. Much of the work to date on reconfigu... View full abstract»

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  • The Splash 2 software environment

    Publication Year: 1993, Page(s):88 - 93
    Cited by:  Papers (24)  |  Patents (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (436 KB)

    Splash 2 is an attached special purpose parallel processor in which the computing elements are user programmable FPGA devices. The architecture of Splash 2 is designed to accelerate the solution of problems which exhibit at least modest amounts of temporal or data parallelism. Applications are developed by writing behavioral descriptions of algorithms in VHDL, which are then iteratively refined an... View full abstract»

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  • PRISM-II compiler and architecture

    Publication Year: 1993, Page(s):9 - 16
    Cited by:  Papers (47)  |  Patents (21)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (560 KB)

    This paper discusses the architecture and compiler for a general-purpose metamorphic computing platform called PRISM-II. PRISM-II improves the performance of many computationally-intensive tasks by augmenting the functionality of the core processor with new instructions that match the characteristics of targeted applications. In essence, PRISM (processor reconfiguration through instruction set met... View full abstract»

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  • A data-parallel programming model for reconfigurable architectures

    Publication Year: 1993, Page(s):79 - 87
    Cited by:  Papers (9)  |  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (552 KB)

    Recently, several machines have been built using field programmable gate array (FPGA) technology. These reconfigurable architectures have demonstrated very high performance for a variety of problems. The configuration of these machines typically rely on some form of hardware specification. The authors demonstrate that a more traditional software approach may be used. A vector based data-parallel m... View full abstract»

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  • A stochastic neural architecture that exploits dynamically reconfigurable FPGAs

    Publication Year: 1993, Page(s):202 - 211
    Cited by:  Papers (30)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (688 KB)

    The authors present an expandable digital architecture that provides an efficient real time implementation platform for large neural networks. The architecture makes heavy use of the techniques of bit serial stochastic computing to carry out the large number of required parallel synaptic calculations. In this design all real valued quantities are encoded on to stochastic bit streams in which the `... View full abstract»

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  • The AnyBoard: programming and enhancements

    Publication Year: 1993, Page(s):68 - 77
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (540 KB)

    The programming of the AnyBoard is demonstrated by the design of a simple direction finder. The operations needed to enter, simulate, store, map, and debug a design are discussed. The length of time needed to accomplish each of these operations is used to justify some proposed enhancements to the AnyBoard Rapid-Prototyping Environment View full abstract»

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  • Hardware acceleration of divide-and-conquer paradigms: a case study

    Publication Year: 1993, Page(s):192 - 201
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (632 KB)

    The authors describe a method for speeding up divide-and-conquer algorithms with a hardware coprocessor, using sorting as an example. The method employs a conventional processor for the `divide' and `merge' phases, while the `conquer' phase is handled by a purpose-built coprocessor. It is shown how transformation techniques from the Ruby language can be adopted in developing a family of systolic s... View full abstract»

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