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Interaction between Compilers and Computer Architectures, 2004. INTERACT-8 2004. Eighth Workshop on

Date 15 Feb. 2004

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  • Fast indexing for blocked array layouts to improve multi-level cache locality

    Publication Year: 2004, Page(s):107 - 119
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1745 KB) | HTML iconHTML

    One of the key challenges computer architects and compiler writers are facing, is the increasing discrepancy between processor cycle times and main memory access times. To overcome this problem, program transformations that decrease cache misses are used, to reduce average latency for memory accesses. Tiling is a widely used loop iteration reordering technique for improving locality of references.... View full abstract»

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  • Reducing fetch architecture complexity using procedure inlining

    Publication Year: 2004, Page(s):97 - 106
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1366 KB) | HTML iconHTML

    Fetch engine performance is seriously limited by the branch prediction table access latency. This fact has lead to the development of hardware mechanisms, like prediction overriding, aimed to tolerate this latency. However, prediction overriding requires additional support and recovery mechanisms, which increases the fetch architecture complexity. In this paper, we show that this increase in compl... View full abstract»

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  • Dynamic management of nursery space organization in generational collection

    Publication Year: 2004, Page(s):33 - 40
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1518 KB) | HTML iconHTML

    The use of automatic memory management in object-oriented languages like Java is becoming eagerly accepted due to its software engineering benefits, its reduction in programming time and safety aspects. Nevertheless, the complexity of garbage collection results in an important overhead for the virtual machine job. Until now, the strategies in garbage collection have focused in defining and fixing ... View full abstract»

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  • Exploiting procedure level locality to reduce instruction cache misses

    Publication Year: 2004, Page(s):75 - 84
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1329 KB) | HTML iconHTML

    High instruction fetch bandwidth is essential for high performance in today's wide-issue out-of-order processors. Instruction caches must provide a low miss rate as well as low latency. We introduce procedure level relocation, a class of dynamic feedback-directed optimizations that substantially reduce the instruction cache miss rate by exploiting the temporal locality of procedure usage. Based on... View full abstract»

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  • Exploitation of instruction-level parallelism for optimal loop scheduling

    Publication Year: 2004, Page(s):13 - 21
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1350 KB) | HTML iconHTML

    We present a loop scheduling approach which optimally exploits instruction-level parallelism. We develop a flow graph model for the resource constraints allowing a more efficient implementation. The method supports heterogeneous processor architectures and pipelines functional units. Our linear programming implementation produces an optimum loop schedule, making the technique applicable to product... View full abstract»

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  • Data movement optimization for software-controlled on-chip memory

    Publication Year: 2004, Page(s):120 - 127
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1420 KB) | HTML iconHTML

    In order to overcome performance degradation caused by performance disparity between processor and main memory, there have been proposed several new VLSI architectures which have software controlled on-chip memory in addition to the conventional cache. However, users must specify data allocation/replacement on software controlled on-chip memory and data transfer between the on-chip and off-chip me... View full abstract»

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  • Cool-Fetch: a compiler-enabled IPC estimation based framework for energy reduction

    Publication Year: 2004, Page(s):43 - 52
    Cited by:  Papers (2)  |  Patents (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1380 KB) | HTML iconHTML

    With power consumption becoming an increasingly important factor, it is necessary to reevaluate traditional, power-intensive, architectural techniques and their relative performance benefits. We believe that combined architecture-compiler efforts open up new and efficient ways to retain the performance benefits of modern architectures while addressing their power impact. In this paper, we present ... View full abstract»

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  • Link-time optimization techniques for eliminating conditional branch redundancies

    Publication Year: 2004, Page(s):87 - 96
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1387 KB) | HTML iconHTML

    Optimizations performed at link time or directly applied to final program executables have received increased attention in recent years. This work discusses the discovery and elimination of redundant conditional branches in the context of a link-time optimizer, an optimization that we call conditional branch redundancy elimination (CBRE). Our experiments show that around 20% of conditional branche... View full abstract»

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  • Garbage collector refinement for new dynamic multimedia applications on embedded systems

    Publication Year: 2004, Page(s):25 - 32
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1425 KB) | HTML iconHTML

    Consumer embedded devices must execute concurrently multiple services (e.g. multimedia applications) that are dynamically triggered by the user. For these new embedded multimedia applications, the dynamic memory subsystem is currently one of the main sources of power consumption and its inattentive management can severely affect the performance and power consumption and its attentive management ca... View full abstract»

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  • Energy-efficiency potential of a phase-based cache resizing scheme for embedded systems

    Publication Year: 2004, Page(s):53 - 62
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2178 KB) | HTML iconHTML

    Managing the energy-performance tradeoff has become a major challenge with embedded systems. The cache hierarchy is a typical example where this tradeoff plays a central role. With the increasing level of integration density, a cache can feature millions of transistors, consuming a significant portion of the energy. At the same time however, a cache also permits to significantly improve performanc... View full abstract»

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  • SimSnap: fast-forwarding via native execution and application-level checkpointing

    Publication Year: 2004, Page(s):65 - 74
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1355 KB) | HTML iconHTML

    As systems become more complex, conducting cycle-accurate simulation experiments becomes more time consuming. Most approaches to accelerating simulations attempt to choose simulation points, such that the performance of the program portions modeled in detail are representative of whole-program behavior. To maintain or build the correct architectural state, "fast-forwarding" models a series of inst... View full abstract»

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  • Continuous trip count profiling for loop optimization in two-phase dynamic binary translators

    Publication Year: 2004, Page(s):3 - 12
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1359 KB) | HTML iconHTML

    Most dynamic binary translators use a two-phase approach to identify and optimize frequently executed code dynamically. In the profiling phase, blocks of code are interpreted or translated without optimization to collect execution frequency information for the blocks. In the optimization phase, frequently executed blocks are grouped into regions and advanced optimizations are applied on them. This... View full abstract»

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  • Proceedings. Eighth Workshop on Interaction Between Compilers and Computer Architectures - INTERACT-8 2004

    Publication Year: 2004
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  • [Blank page]

    Publication Year: 2004, Page(s): i
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  • Proceedings Eighth Workshop on Interaction Between Compilers and Computer Architectures [cover]

    Publication Year: 2004, Page(s): ii
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  • Proceedings Eighth Workshop on Interaction Between Compilers and Computer Architectures Copyright Page

    Publication Year: 2004, Page(s): iii
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  • Proceedings Eighth Workshop on Interaction Between Compilers and Computer Architectures

    Publication Year: 2004, Page(s): iv
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  • Proceedings - Eighth Workshop on Interaction Between Compilers and Computer Architectures Table of Contents

    Publication Year: 2004, Page(s):v - vi
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  • Message From The Program Chair

    Publication Year: 2004, Page(s): vii
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  • Program Committee

    Publication Year: 2004, Page(s): viii
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  • Author index

    Publication Year: 2004, Page(s): 129
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