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Microelectronics and Electron Devices, 2004 IEEE Workshop on

Date 2004

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Displaying Results 1 - 25 of 56
  • 2.4 GHz high gain low power narrowband low-noise amplifier (LNA) in 0.18 μm TSMC CMOS

    Publication Year: 2004 , Page(s): 52 - 54
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1380 KB) |  | HTML iconHTML  

    A 2.4 GHz low-noise amplifier has been designed in a standard CMOS 0.18 TSMC process. The measured noise factor and gain are 1.65dB and 51dB, respectively, at 2.4 GHz. The LNA draws 1.75 mA from a 1.8 V supply voltage. The detailed design process and simulations are detailed in this paper. View full abstract»

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  • Design of a pipelined adder using skew tolerant domino logic in a 0.35 μm TSMC process

    Publication Year: 2004 , Page(s): 55 - 59
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1453 KB) |  | HTML iconHTML  

    Over the years, there has been an increased growth in wireless electronics and distributed computer architectures. This has pushed the need for developing innovative designs for realizing fast multi-bit adders such as the carry propagate adder (CPA). To increase the frequency of operation, pipelining is considered. As the frequency of operation is increased, the cycle time measured in gate delays continues to shrink. As such, the overhead becomes more important for the design of high performance systems. This paper discusses overlapping clocks to eliminate possible sources of overhead by using the concept of time borrowing. The relationship between overlapping clock frequency and the amount of total computation time will be explored in detail. Simulation results will show output profiles for various input data patterns. View full abstract»

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  • Pattern alignment effects in through-wafer bulk micromachining of (100) silicon

    Publication Year: 2004 , Page(s): 89 - 92
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3834 KB) |  | HTML iconHTML  

    Precise alignment of the mask patterns relative to wafer crystallographic orientation is critical in the fabrication of many MEMS devices. Slight misalignment between the two can create striations and other defects in the etched sidewalls using an orientation dependent etchant such as potassium hydroxide (KOH). This paper focuses on the characterization of the resultant geometries due to the deliberate misalignment of photolithographically defined patterns relative to the [110] plane in (100) orientation silicon. The surface roughness of the etched (111) sidewall are characterized using optical microscopy, scanning electron microscopy and profilometry. View full abstract»

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  • A review of RF ESD protection design [RF IC applications]

    Publication Year: 2004 , Page(s): 20 - 23
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1498 KB) |  | HTML iconHTML  

    This paper reviews design and analysis of on-chip ESD (electrostatic discharge) protection circuits for RF ICs. ESD protection basics, key issues in RF ESD protection, design methods, RF ESD protection evaluation techniques and RF ESD protection solutions are discussed. View full abstract»

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  • Comparing rapid thermal process and low-temperature furnace annealed poly test wafers by SIMS and FTIR

    Publication Year: 2004 , Page(s): 111 - 113
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1551 KB) |  | HTML iconHTML  

    As the poly deposition process monitor, poly test wafers (TWS) run with production wafers are generally annealed using the rapid thermal process (RTP) to achieve fast, stable results. But real production wafers often receive an extended, low-temperature furnace thermal process after poly deposition. For this reason, there is always a question about whether or not RTP effectively simulates the thermal budget the device wafers receive during the whole process. During this study, the same processed poly films, both n-type and p-type, go through the RTP furnace for 8 hours at 600°C. Comparing the secondary ion mass spectrometry (SIMS) profile and Fourier transform infrared spectroscopy (FTIR) of the Si-H bond led us to question whether the RTP process is reliable enough to be used as the poly deposition process monitor. View full abstract»

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  • Atomically controlled processing for future Si-based devices

    Publication Year: 2004 , Page(s): 31 - 34
    Cited by:  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2425 KB) |  | HTML iconHTML  

    One of the main requirements for Si-based ultrasmall devices is atomic-order control of process technology. Here we show the concept of atomically controlled processing, based on atomic-order surface reaction control. Self-limiting formation of 1-3 atomic layers of group IV or related atoms in the thermal adsorption and reaction of hydride gases (SiH4, GeH4, NH3, PH3, CH4 and SiH3CH3) on Si(100) and Ge(100) are generalized, based on the Langmuir-type model. Si epitaxial growth over the N and P layer already-formed on the Si(100) surface is achieved. It is found that a higher level of electrical P atoms exist in such films, compared with doping under thermal equilibrium conditions. These results open the way to atomically controlled technology for ultralarge-scale integrations. View full abstract»

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  • Through wafer interconnects on active pMOS devices

    Publication Year: 2004 , Page(s): 82 - 84
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1375 KB) |  | HTML iconHTML  

    The objective of this research is to demonstrate the ability to create through-wafer interconnects (TWIs) on wafers with active devices. TWIs have previously been demonstrated on blank Si wafers. The application of TWIs in an industrial setting requires no damage or yield loss to the existing devices during additional processing steps. The test vehicle chosen is a simple pMOS test chip, which includes different structures such as transistors and invertors. The processing steps and sequence required to integrate TWIs into wafers with active devices is demonstrated. View full abstract»

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  • A low-power low-noise sensor IC

    Publication Year: 2004 , Page(s): 60 - 63
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1493 KB) |  | HTML iconHTML  

    An IC for acquisition of 16 electrophysiology signals in mice is described. Each channel includes programmable gains from 10 to 1000, a 7 kHz low-pass 4th-order Butterworth filter and a sample and hold. Simulations predict 14-bit accuracy up to 7 kHz. The integrated noise from 1 Hz to 7 kHz is 1.9 μV/Hz12 /. The +/-0.3V dc input offset of each channel is cancelled with 7-bit DACs controlling the bulk of the first opamp input transistors and 6-bit DACs on the 2nd stage. Total power dissipation is 13.5 mW using a 3V supply. Die area is 6 mm2 in a 0.25 μ process. View full abstract»

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  • An asynchronous GALS interface with applications

    Publication Year: 2004 , Page(s): 41 - 44
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1382 KB) |  | HTML iconHTML  

    A low-latency asynchronous interface for use in globally-asynchronous locally-synchronous (GALS) integrated circuits is presented. The interface is compact and does not alter the local clocks of the interfaced local clock domains in any way (unlike many existing GALS interfaces). Two applications of the interface to GALS systems are shown. The first is a single-chip shared-memory multiprocessor for generic supercomputing use. The second is an application-specific coprocessor for hardware acceleration of the Smith-Waterman algorithm. This is a bioinformatics algorithm used for sequence alignment (similarity searching) between DNA or amino acid (protein) sequences and sequence databases such as the recently completed human genome database. View full abstract»

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  • CMOS technology for MS/RF SoC

    Publication Year: 2004 , Page(s): 24 - 27
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1479 KB) |  | HTML iconHTML  

    The development of short-range wireless communication has become exceedingly important due to the emerging market of WLAN and Bluetooth. CMOS technology has emerged as the top solution due to its cost advantage, performance improvement and ease of integration for high-performance digital circuits and high-speed analog/RF circuits. Accelerated scaling of CMOS technology has contributed to remove otherwise fundamental barriers preempting its widespread application to mixed-signal/radio-frequency (MS/RF) segments. Improvements in device speed, matching, and minimum noise figure are all consistent with fundamental scaling trends. Other figures-of-merit such as linearity and 1/f noise do not scale favorably but are not considered roadblocks when viewed from a circuit design perspective. Furthermore, interconnect architectural scaling trends in logic technology have facilitated improvements in passive-component performance metrics. These improvements compounded with innovations in circuit design have made CMOS technology the primary choice for cost driven MS/RF applications. This paper reviews active and passive elements of CMOS MS/RF SoC technology from a scaling perspective. View full abstract»

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  • Packaging effect on reliability of Cu/low k interconnects

    Publication Year: 2004 , Page(s): 28 - 30
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1450 KB) |  | HTML iconHTML  

    In a plastic flip-chip package, the thermal deformation of the package can be directly coupled into the Cu/low k interconnect structure inducing large local deformation to drive interfacial crack formation. In this paper, we summarize experimental and modeling results to investigate the chip-package interaction and its impact on low k interconnect reliability. We first review the experimental techniques for measuring thermal deformation in a flip-chip package and interfacial fracture energy for low k interfaces. Then results from 3D FEA, based on a multilevel sub-modeling approach in combination with high-resolution moire interferometry, to investigate the chip-package interaction for SiLK and MSQ low k interconnects are discussed. Packaging induced crack driving forces for relevant interfaces in Cu/low k structures are deduced and compared with corresponding interfaces in Cu/TEOS and Al/TEOS structures to assess the effect of ILD on packaging reliability. Our results indicate that packaging assembly can significantly impact wafer-level reliability causing interfacial delamination to become a serious reliability concern for Cu/low k structures. View full abstract»

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  • Leakage power reduction using self-bias transistor in VLSI circuits [digital circuits]

    Publication Year: 2004 , Page(s): 71 - 74
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1428 KB) |  | HTML iconHTML  

    Recent trends in CMOS technology and scaling of devices clearly indicate that leakage power in digital circuits would be crucial and largely depend on the sub-threshold currents. Minimizing leakage, by power gating logic circuits using sleep transistors gives considerable power savings. However, this technique cannot be used in sequential circuits and memory cells, as it would result in loss of stored data. In this paper, we propose a novel circuit by applying a self-bias transistor (SBT) to minimize sub-threshold leakage currents in static and dynamic circuits. This circuit with SBTs, acts as a smart switch by virtually power gating either pull-up or pull-down logic, and causes a considerable reduction in leakage currents in both active and standby modes. A benchmark is simulated with 0.18 μm CMOS technology in the Cadence Spectre circuit simulator. Results show significant reduction in leakage power, of up to 50% on average, for all possible states simulated in static and dynamic circuits by applying this proposed self-bias transistor. View full abstract»

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  • Effects of hydrogen in passivation PECVD nitride film on DRAM refresh performance

    Publication Year: 2004 , Page(s): 114 - 116
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1377 KB) |  | HTML iconHTML  

    It was found that passivation nitride significantly affects DRAM refresh performance. To determine the factors in the nitride film that contributed to improved refresh performance, several analyses, such as Fourier-transform infrared spectrum (FTIR), thermal desorption spectrum (TDS), and x-ray photon spectroscopy (XPS), were performed on plasma enhanced chemical vapor deposition (PECVD) nitride film. The data revealed that the film with high Si-H bond in PECVD nitride film release more hydrogen in subsequent thermal process, in turn, to improved refresh performance. View full abstract»

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  • Beyond nanoscale DRAM and flash challenges and opportunities for research in emerging memory devices

    Publication Year: 2004 , Page(s): 35 - 38
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1583 KB) |  | HTML iconHTML  

    As dynamic random access memory (DRAM) and flash nonvolatile memory (NVM) technologies are entering their 4th decade of continuing growth and progress, difficulties in scaling these respective devices have surfaced both in processing and device miniaturization. This paper addresses these challenges and presents emerging device alternatives with their perspective challenges and opportunities for research and development in this field. View full abstract»

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  • Adjusting poly texture to reduce TiSi2 agglomeration [semiconductor manufacturing]

    Publication Year: 2004 , Page(s): 93 - 94
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    With its low resistivity and relatively high thermal stability, TiSi2 is a promising gate material for use in semiconductor manufacturing. It can survive the oxidization and backend thermal steps without a spacer; however, it sometimes agglomerates into the gate poly. This paper outlines a possible solution that entails replacing the normal amorphous gate poly with a different type of as-deposited poly to reduce the gate short caused by agglomeration. Scanning electron microscopy (SEM) inspections of cross sections of blank test wafers reveal the potential of this method. View full abstract»

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  • Experimental investigation of bare silicon wafer warp

    Publication Year: 2004 , Page(s): 120 - 123
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1673 KB) |  | HTML iconHTML  

    IC packaging trends demand smaller packaging, which translates to thinner silicon; in some cases as thin as 50 μm. Thinning below 305 μm induces significant warp in product/metal wafers, which continues to increases as wafers are thinned further. Increased wafer warp results in handling/processing issues. Studies have been performed on product/metal wafers to characterize warp. These studies have shown a linear relationship between wafer warp and 1/thickness├č2. Several factors, in combination, have been shown to contribute to warp in product/metal wafers such as: metal layers, polyimide layers, BCB layers, metal density, thermal stress, tilt direction, front side tension, backside tension, and gravity. The wafer warp phenomenon observed in product/metal wafers is also observed in bare silicon wafers. The difference between bare silicon test wafers and product wafers is the layering of the circuitry side on product/metal wafers, which has shown to be a large contributor to wafer warp. Damage to the wafer backside during conventional grinding can induce a large amount of warp in both product/metal and bare silicon wafers. View full abstract»

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  • Evaluation of solder-to-passivation attachment as a wafer bumping architecture: I. Insulating properties

    Publication Year: 2004 , Page(s): 103 - 107
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1481 KB) |  | HTML iconHTML  

    This paper describes the concept of direct mechanical attachment of a solder bump to the base IC passivation, in what has been called "wide via" design - a low-cost design option rejected for use by Bourns. In general use over an ASIC or other active device, this architecture relies upon the oxide/nitride passivation stack for complete conformal coverage of IC routing metalization, and assumes an absence of pinholes. We have created a test chip to evaluate the validity of these assumptions under BHT testing, as well as to enable comparative thermomechanical performance and induced parasitic effects. In this paper, we describe the BHT and failure analysis results indicating that passivation processes need to be optimized in order for this architecture to work. This result has implications in "over-the-fence" design in which a bump supplier makes assumptions regarding the quality of passivation from an IC manufacturer, and how passivation stacks which were good enough for peripheral wire bonding applications may need to be re-thought for area-array bumping. View full abstract»

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  • A statistical model based ASIC skew selection method

    Publication Year: 2004 , Page(s): 64 - 66
    Cited by:  Papers (4)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1396 KB) |  | HTML iconHTML  

    Cross wafer speed variations in the 0.13 μm process and beyond are significant enough to be considered in ASIC skew selection. Traditional Idsat and Vt measurements on a few sites of the wafer to gauge wafer speed simply does not work. Multiple skew lot runs to get proper skew wafers is financially prohibitive and part skew uncertainty makes it impossible to qualify product with a reasonable number of skew parts. Typical design practice for high-speed ASICs is to add a PVT monitor on the die. For area critical applications, scribe PVT monitors can be used. The PVT circuitry can be as simple as an inverter ring oscillator chain. We present a methodology based on on-chip or on-scribe ring oscillator data to bin the ASIC skew parts. Statistical modeling, PVT monitor sensitivity and actual experiment data are discussed. Based on the proposed methodology, proper skew parts can be selected for product testing so that products are validated cross all process corners. View full abstract»

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  • Analysis of jitter in clock distribution networks

    Publication Year: 2004 , Page(s): 45 - 47
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1384 KB) |  | HTML iconHTML  

    A technique for the simulation of jitter in clock distribution networks will be demonstrated. Noise is injected as a time domain signal into each driver stage in the clock distribution network and large signal non-linear transient simulations are performed to obtain the distribution of clock periods and the subsequent jitter in the clock signal. In the simplest case the noise is the thermal channel noise of the CMOS driver transistors, and the results can be compared to the simple analytical estimate given by Gray et al.[1994]. It will be shown that there is a good agreement between the simulation results and analytical estimates if a modified analytical formula is used where the simple estimate for delay by Gray et al. is replaced by the observed delay from simulations. The technique can be extended and is directly applicable to other types of noise such as power supply noise. View full abstract»

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  • Clock and data recovery circuits with fast acquisition and low jitter

    Publication Year: 2004 , Page(s): 48 - 51
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1757 KB) |  | HTML iconHTML  

    This paper presents a half-rate clock and data recovery circuit (CDR) that combines the best features, fast acquisition and low jitter, of digital phase selection and phase-lock-loop (PLL) CDR circuits. This CDR circuit consists of a phase selector, which can lock to the data in just a few clock cycles but has high jitter, and a PLL, which requires a much longer lock time but provides a low-jitter clock after locking. Fabricated in a 0.5 μm CMOS process, the combined CDR achieves operation up to 750 Mbps. Measurements show at least a 6% acquisition range, an initial acquisition time of 8 bit times with jitter of 30% bit time, and jitter of 16 ps at 688 Mbps after a PLL lock time of 700 ns. Power dissipation is 300 mW and die area is 1.4 × 1.4 mm2. View full abstract»

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  • A compact 5.6 GHz low noise amplifier with new on-chip gain controllable active balun

    Publication Year: 2004 , Page(s): 131 - 132
    Cited by:  Papers (10)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1420 KB) |  | HTML iconHTML  

    A dual gain low noise amplifier for a 5.6 GHz ISM band direct conversion receiver, has been designed using a TSMC 0.25 μm CMOS process and features a gain controllable on-chip active balun. The LNA provides gains of 19.5 dB and 12 dB in the two modes with 50% power savings in the low gain mode, while a noise figure of 3.1 dB and an IIP3 of -11.5 dBm have been achieved. A simple and novel gain control technique has been adopted and the gain control circuitry has been integrated with the balun. View full abstract»

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  • A 5.6-GHz CMOS doubly balanced sub-harmonic mixer for direct conversion -zero IF receiver

    Publication Year: 2004 , Page(s): 129 - 130
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1462 KB) |  | HTML iconHTML  

    A new low power 5.6 GHz doubly balanced sub-harmonic mixer for industrial scientific medical (ISM) band direct conversion - zero IF receiver in 0.25-μm CMOS is presented. The mixer uses a power efficient LO frequency generation scheme to overcome the LO self-mixing problems common in conventional direct conversion receivers (DCR). Simulated with 1% gm mismatch, 0.5% load mismatch and 2° LO phase error, the mixer is able to achieve 55 dBm of IIP2, -6.5 dBm of IIP3 and voltage conversion gain of 8 dB while consuming less than 1.75 mA from a single 3 V supply. The mixer also achieves input compression of -12 dBm and an overall double side band noise figure of 5.96 dB. The proposed mixer takes up less than 1 mm2 of silicon real estate. View full abstract»

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  • Scaling trends in DRAM technology

    Publication Year: 2004
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1273 KB)  

    Summary form only given. Trends in scaling DRAM to 0.11 μm and below are reviewed. Scaling techniques used in earlier generations for the array access transistor and the storage capacitor are running into limitations, necessitating changes in electrical operating mode, cell structure, and processing innovations. Although a variety of options exist for advancing the technology, including low-voltage operation, non-planar array transistor MOSFETs, and novel capacitor structures and materials, uncertainties exist over the which of these will prove workable in manufacturing. This paper discusses the interrelationships among the DRAM scaling requirements and solutions. View full abstract»

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  • Simulation of the exclusion/extraction InSb MOSFETs

    Publication Year: 2004 , Page(s): 67 - 70
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1449 KB) |  | HTML iconHTML  

    A methodology for simulation of InSb MOSFETs in standard drift-diffusion simulators is presented. Due to its low bandgap and high mobility, InSb shows promise as a material for extremely high frequency active devices operating at very low voltages. Material complexities, such as non-parabolicity, degeneracy, mobility and Auger recombination/generation are explained, and physics based models are developed. This methodology is then applied to the examination of the leakage current, transconductance and maximum unity current gain frequency of the exclusion/extraction MOSFET. Its scaling properties down to 0.15 μm are also analyzed. View full abstract»

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  • Electrical characterization of through-wafer interconnects

    Publication Year: 2004 , Page(s): 99 - 102
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1582 KB) |  | HTML iconHTML  

    Through-wafer interconnects (TWI) allows 3-D chip stacking enabling integration of multiple chip functions (i.e. opto-electronic, analog or digital) with reduced power and space requirements. To date, non-destructive characterization techniques for determining interconnect integrity and reliability have not been developed. This work examines a specially modified electrical four-point probe for non-destructive characterization of TWI's. Technical challenges and measurement optimization methods are reported. View full abstract»

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