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Microelectronics and Electron Devices, 2004 IEEE Workshop on

Date 2004

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Displaying Results 1 - 25 of 56
  • Elimination of body effects in SOI CMOS devices

    Page(s): 126 - 128
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1421 KB) |  | HTML iconHTML  

    Tremendous research is going on in using silicon-on-insulator (SOI) devices for commercial purposes. Many advantages, like low junction capacitance, complete isolation of devices, smaller layout area, low power consuming circuits and lesser delays have enhanced the possibility of faster circuits. Still, problems with the parasitic floating body effects in partially depleted SOI (PDSOI) devices exist. The effects of the floating body are studied through the DC characteristics of PDSOI device structures. Effects like the kink effect, loss of gate control, self-heating effect and impact ionization are investigated. The impact ionization and the bipolar latch up effects tend to dominate in partially depleted (PDSOI) devices. DC characteristics of body tied to source, dynamic threshold MOS (DTMOS), and PDSOI devices are presented. View full abstract»

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  • CMOS imager technology shrinks and image performance

    Page(s): 7 - 18
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1790 KB) |  | HTML iconHTML  

    In this paper, we present a performance summary of CMOS imager pixels from 5.2 μm to 4.2 μm using 0.18 μm imager design rules, then to 3.2 μm using 0.15 μm imager design rules. These pixels support 1.3-megapixel, 2.0-megapixel, and 3.1-megapixel CMOS image sensors for digital still cameral (DSC) applications at 3.3 V, respectively. The 4TC pixels are all based on technology shrinks of Micron's 2P3M imager process, and each of the technology nodes report excellent CMOS imager low-noise, high-sensitivity, low-lag, and low-light performance, matching that of state-of-the-art charged-coupled device (CCD) imagers. We have put a model in place to provide the predictive performance of smaller pixels, and then use that model to discuss performance expectations down to 2.0 μm pixels. With the combination of imager design rules, pixel architecture, and process technology tailored for CMOS imagers, we see no fundamental reason that CMOS imagers should not be able to continue matching CCD performance as pixel sizes shrink. View full abstract»

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  • Packaging effect on reliability of Cu/low k interconnects

    Page(s): 28 - 30
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1450 KB) |  | HTML iconHTML  

    In a plastic flip-chip package, the thermal deformation of the package can be directly coupled into the Cu/low k interconnect structure inducing large local deformation to drive interfacial crack formation. In this paper, we summarize experimental and modeling results to investigate the chip-package interaction and its impact on low k interconnect reliability. We first review the experimental techniques for measuring thermal deformation in a flip-chip package and interfacial fracture energy for low k interfaces. Then results from 3D FEA, based on a multilevel sub-modeling approach in combination with high-resolution moire interferometry, to investigate the chip-package interaction for SiLK and MSQ low k interconnects are discussed. Packaging induced crack driving forces for relevant interfaces in Cu/low k structures are deduced and compared with corresponding interfaces in Cu/TEOS and Al/TEOS structures to assess the effect of ILD on packaging reliability. Our results indicate that packaging assembly can significantly impact wafer-level reliability causing interfacial delamination to become a serious reliability concern for Cu/low k structures. View full abstract»

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  • Evaluation of solder-to-passivation attachment as a wafer bumping architecture: I. Insulating properties

    Page(s): 103 - 107
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1481 KB) |  | HTML iconHTML  

    This paper describes the concept of direct mechanical attachment of a solder bump to the base IC passivation, in what has been called "wide via" design - a low-cost design option rejected for use by Bourns. In general use over an ASIC or other active device, this architecture relies upon the oxide/nitride passivation stack for complete conformal coverage of IC routing metalization, and assumes an absence of pinholes. We have created a test chip to evaluate the validity of these assumptions under BHT testing, as well as to enable comparative thermomechanical performance and induced parasitic effects. In this paper, we describe the BHT and failure analysis results indicating that passivation processes need to be optimized in order for this architecture to work. This result has implications in "over-the-fence" design in which a bump supplier makes assumptions regarding the quality of passivation from an IC manufacturer, and how passivation stacks which were good enough for peripheral wire bonding applications may need to be re-thought for area-array bumping. View full abstract»

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  • Process development of electron beam lithography in an academic environment

    Page(s): 117 - 119
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    This paper compares the processes of photolithography and electron beam lithography (EBL). In addition, we discuss the procedure used to implement EBL in a university laboratory, specifically Boise State University's (BSU) Idaho Microfabrication Laboratory (IML). View full abstract»

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  • Scaling trends in DRAM technology

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    Summary form only given. Trends in scaling DRAM to 0.11 μm and below are reviewed. Scaling techniques used in earlier generations for the array access transistor and the storage capacitor are running into limitations, necessitating changes in electrical operating mode, cell structure, and processing innovations. Although a variety of options exist for advancing the technology, including low-voltage operation, non-planar array transistor MOSFETs, and novel capacitor structures and materials, uncertainties exist over the which of these will prove workable in manufacturing. This paper discusses the interrelationships among the DRAM scaling requirements and solutions. View full abstract»

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  • Experimental investigation of bare silicon wafer warp

    Page(s): 120 - 123
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1673 KB) |  | HTML iconHTML  

    IC packaging trends demand smaller packaging, which translates to thinner silicon; in some cases as thin as 50 μm. Thinning below 305 μm induces significant warp in product/metal wafers, which continues to increases as wafers are thinned further. Increased wafer warp results in handling/processing issues. Studies have been performed on product/metal wafers to characterize warp. These studies have shown a linear relationship between wafer warp and 1/thickness├č2. Several factors, in combination, have been shown to contribute to warp in product/metal wafers such as: metal layers, polyimide layers, BCB layers, metal density, thermal stress, tilt direction, front side tension, backside tension, and gravity. The wafer warp phenomenon observed in product/metal wafers is also observed in bare silicon wafers. The difference between bare silicon test wafers and product wafers is the layering of the circuitry side on product/metal wafers, which has shown to be a large contributor to wafer warp. Damage to the wafer backside during conventional grinding can induce a large amount of warp in both product/metal and bare silicon wafers. View full abstract»

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  • A 5.6-GHz CMOS doubly balanced sub-harmonic mixer for direct conversion -zero IF receiver

    Page(s): 129 - 130
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1462 KB) |  | HTML iconHTML  

    A new low power 5.6 GHz doubly balanced sub-harmonic mixer for industrial scientific medical (ISM) band direct conversion - zero IF receiver in 0.25-μm CMOS is presented. The mixer uses a power efficient LO frequency generation scheme to overcome the LO self-mixing problems common in conventional direct conversion receivers (DCR). Simulated with 1% gm mismatch, 0.5% load mismatch and 2° LO phase error, the mixer is able to achieve 55 dBm of IIP2, -6.5 dBm of IIP3 and voltage conversion gain of 8 dB while consuming less than 1.75 mA from a single 3 V supply. The mixer also achieves input compression of -12 dBm and an overall double side band noise figure of 5.96 dB. The proposed mixer takes up less than 1 mm2 of silicon real estate. View full abstract»

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  • Pattern alignment effects in through-wafer bulk micromachining of (100) silicon

    Page(s): 89 - 92
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3834 KB) |  | HTML iconHTML  

    Precise alignment of the mask patterns relative to wafer crystallographic orientation is critical in the fabrication of many MEMS devices. Slight misalignment between the two can create striations and other defects in the etched sidewalls using an orientation dependent etchant such as potassium hydroxide (KOH). This paper focuses on the characterization of the resultant geometries due to the deliberate misalignment of photolithographically defined patterns relative to the [110] plane in (100) orientation silicon. The surface roughness of the etched (111) sidewall are characterized using optical microscopy, scanning electron microscopy and profilometry. View full abstract»

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  • Interaction effects of slurry chemistry on chemical mechanical planarization of electroplated copper

    Page(s): 85 - 88
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1386 KB) |  | HTML iconHTML  

    Recent studies have been conducted investigating the effects of slurry chemistry on the copper CMP process. Slurry pH and hydrogen peroxide concentration are two important variables that must be carefully formulated in order to achieve desired removal rates and uniformity. In applications such as through-wafer vertical interconnects, slurry chemistry effects must be thoroughly understood when copper plating thicknesses can measure up to 20 μm thick. The species of copper present on the surface of the wafer can be controlled through formulation of the slurry chemistry resulting in minimizing non-uniformity while aggressively removing copper. Using a design of experiments (DOE) approach, this study was performed, investigating the interaction between the two variables during CMP. Using statistical analysis techniques, a better understanding of the interaction behavior between the two variables and the effect on removal rate and uniformity is achieved. View full abstract»

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  • Development of a micro-nozzle and ion mobility spectrometer in LTCC

    Page(s): 95 - 98
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2600 KB) |  | HTML iconHTML  

    Multilayer ceramic packaging materials provide a versatile platform to fabricate a wide variety of devices from sensors to micro-nozzles. Our research is focused on developing robust sensors for underground deployment and monopropellant micro nozzles for satellite attitude adjustment applications. An LTCC monopropellant micro-nozzle is being developed and tested to provide small thrust vectors for satellite attitude adjustments. High purity hydrogen peroxide undergoes a strong exothermic decomposition reaction in the presence of a silver catalyst. A micro-nozzle and catalyst chamber has been designed to convert hydrogen peroxide liquid to functional thrust. The device uses internal fluidic channels to direct the propellant to a silver lined catalyst chamber. The catalyst decomposes the propellant into water vapor and oxygen at temperatures near 1029 K. The hot gases are then expelled through a contoured nozzle to provide thrust. Complex internal geometric features are created using a CNC milling machine. An ion mobility spectrometer (IMS) is being developed for permanent deployment below ground to continuously analyze groundwater pollutants. Each segment was constructed of multiple layers of green tape. Five Kovar inserts were embedded in the device to function as ion gates. Reduction in size, hermeticity and system integration was made possible by the novel use of LTCC packaging technology. View full abstract»

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  • Leakage power reduction using self-bias transistor in VLSI circuits [digital circuits]

    Page(s): 71 - 74
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1428 KB) |  | HTML iconHTML  

    Recent trends in CMOS technology and scaling of devices clearly indicate that leakage power in digital circuits would be crucial and largely depend on the sub-threshold currents. Minimizing leakage, by power gating logic circuits using sleep transistors gives considerable power savings. However, this technique cannot be used in sequential circuits and memory cells, as it would result in loss of stored data. In this paper, we propose a novel circuit by applying a self-bias transistor (SBT) to minimize sub-threshold leakage currents in static and dynamic circuits. This circuit with SBTs, acts as a smart switch by virtually power gating either pull-up or pull-down logic, and causes a considerable reduction in leakage currents in both active and standby modes. A benchmark is simulated with 0.18 μm CMOS technology in the Cadence Spectre circuit simulator. Results show significant reduction in leakage power, of up to 50% on average, for all possible states simulated in static and dynamic circuits by applying this proposed self-bias transistor. View full abstract»

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  • Metal-insulator-Si (MIS) structure for advanced DRAM cell capacitor

    Page(s): 75 - 78
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1389 KB) |  | HTML iconHTML  

    The conventional DRAM cell capacitor with silicon-insulator-silicon (SIS) structure limits the scaling of capacitor cell size because the depletion layer of the polycrystalline-Si electrode becomes more severe as the cell dielectrics (ONO) thickness reaches the sub-50 Å region. This paper demonstrates that capacitance can be significantly increased by using a metal-insulator-Si (MIS) structure where the top electrode is metal TiN and the bottom electrode is semi-hemisphere Si grain (HSG). Capacitance can be further enhanced with PH3/NH3 anneal to the HSG. The effects of post high-temperature anneal on the stability of the MIS structure are also discussed. View full abstract»

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  • A review of RF ESD protection design [RF IC applications]

    Page(s): 20 - 23
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    This paper reviews design and analysis of on-chip ESD (electrostatic discharge) protection circuits for RF ICs. ESD protection basics, key issues in RF ESD protection, design methods, RF ESD protection evaluation techniques and RF ESD protection solutions are discussed. View full abstract»

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  • A compact 5.6 GHz low noise amplifier with new on-chip gain controllable active balun

    Page(s): 131 - 132
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1420 KB) |  | HTML iconHTML  

    A dual gain low noise amplifier for a 5.6 GHz ISM band direct conversion receiver, has been designed using a TSMC 0.25 μm CMOS process and features a gain controllable on-chip active balun. The LNA provides gains of 19.5 dB and 12 dB in the two modes with 50% power savings in the low gain mode, while a noise figure of 3.1 dB and an IIP3 of -11.5 dBm have been achieved. A simple and novel gain control technique has been adopted and the gain control circuitry has been integrated with the balun. View full abstract»

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  • 2.4 GHz high gain low power narrowband low-noise amplifier (LNA) in 0.18 μm TSMC CMOS

    Page(s): 52 - 54
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1380 KB) |  | HTML iconHTML  

    A 2.4 GHz low-noise amplifier has been designed in a standard CMOS 0.18 TSMC process. The measured noise factor and gain are 1.65dB and 51dB, respectively, at 2.4 GHz. The LNA draws 1.75 mA from a 1.8 V supply voltage. The detailed design process and simulations are detailed in this paper. View full abstract»

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  • Non-linear DAC implementations in DDFS

    Page(s): 124 - 125
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1374 KB) |  | HTML iconHTML  

    A technique to reduce ROM size and therefore power dissipation in direct digital frequency synthesizers (DDFS) is to use a non-linear DAC to approximate the sine function. Piecewise-linear and piecewise-quadratic approximations were investigated for a 12, 14 and 16-bit non-linear DAC in terms of the required ROM size, achievable spurious-free dynamic range (SFDR) and implementation complexity. Results show that 94 dB SFDR can be achieved using a 16-segment quadratic approximation, DAC resolution of 14-bits and a 5-bit squaring circuit. The required ROM size is only 256 bits. View full abstract»

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  • Effects of hydrogen in passivation PECVD nitride film on DRAM refresh performance

    Page(s): 114 - 116
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1377 KB) |  | HTML iconHTML  

    It was found that passivation nitride significantly affects DRAM refresh performance. To determine the factors in the nitride film that contributed to improved refresh performance, several analyses, such as Fourier-transform infrared spectrum (FTIR), thermal desorption spectrum (TDS), and x-ray photon spectroscopy (XPS), were performed on plasma enhanced chemical vapor deposition (PECVD) nitride film. The data revealed that the film with high Si-H bond in PECVD nitride film release more hydrogen in subsequent thermal process, in turn, to improved refresh performance. View full abstract»

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  • Adjusting poly texture to reduce TiSi2 agglomeration [semiconductor manufacturing]

    Page(s): 93 - 94
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1560 KB) |  | HTML iconHTML  

    With its low resistivity and relatively high thermal stability, TiSi2 is a promising gate material for use in semiconductor manufacturing. It can survive the oxidization and backend thermal steps without a spacer; however, it sometimes agglomerates into the gate poly. This paper outlines a possible solution that entails replacing the normal amorphous gate poly with a different type of as-deposited poly to reduce the gate short caused by agglomeration. Scanning electron microscopy (SEM) inspections of cross sections of blank test wafers reveal the potential of this method. View full abstract»

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  • A statistical model based ASIC skew selection method

    Page(s): 64 - 66
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1396 KB) |  | HTML iconHTML  

    Cross wafer speed variations in the 0.13 μm process and beyond are significant enough to be considered in ASIC skew selection. Traditional Idsat and Vt measurements on a few sites of the wafer to gauge wafer speed simply does not work. Multiple skew lot runs to get proper skew wafers is financially prohibitive and part skew uncertainty makes it impossible to qualify product with a reasonable number of skew parts. Typical design practice for high-speed ASICs is to add a PVT monitor on the die. For area critical applications, scribe PVT monitors can be used. The PVT circuitry can be as simple as an inverter ring oscillator chain. We present a methodology based on on-chip or on-scribe ring oscillator data to bin the ASIC skew parts. Statistical modeling, PVT monitor sensitivity and actual experiment data are discussed. Based on the proposed methodology, proper skew parts can be selected for product testing so that products are validated cross all process corners. View full abstract»

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  • Analysis of jitter in clock distribution networks

    Page(s): 45 - 47
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1384 KB) |  | HTML iconHTML  

    A technique for the simulation of jitter in clock distribution networks will be demonstrated. Noise is injected as a time domain signal into each driver stage in the clock distribution network and large signal non-linear transient simulations are performed to obtain the distribution of clock periods and the subsequent jitter in the clock signal. In the simplest case the noise is the thermal channel noise of the CMOS driver transistors, and the results can be compared to the simple analytical estimate given by Gray et al.[1994]. It will be shown that there is a good agreement between the simulation results and analytical estimates if a modified analytical formula is used where the simple estimate for delay by Gray et al. is replaced by the observed delay from simulations. The technique can be extended and is directly applicable to other types of noise such as power supply noise. View full abstract»

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  • Electrical characterization of through-wafer interconnects

    Page(s): 99 - 102
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1582 KB) |  | HTML iconHTML  

    Through-wafer interconnects (TWI) allows 3-D chip stacking enabling integration of multiple chip functions (i.e. opto-electronic, analog or digital) with reduced power and space requirements. To date, non-destructive characterization techniques for determining interconnect integrity and reliability have not been developed. This work examines a specially modified electrical four-point probe for non-destructive characterization of TWI's. Technical challenges and measurement optimization methods are reported. View full abstract»

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  • The future of silicon microelectronics

    Page(s): 3 - 4
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    The silicon microelectronic industry has gone through exponential growth in applications, complexity, density, and cost of manufacturing over the last several decades. The challenges in device physics for scaling transistors as well as the design challenges and economic challenges are reviewed and described in the context of how these forces are shaping the way we do business. View full abstract»

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  • Clock and data recovery circuits with fast acquisition and low jitter

    Page(s): 48 - 51
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1757 KB) |  | HTML iconHTML  

    This paper presents a half-rate clock and data recovery circuit (CDR) that combines the best features, fast acquisition and low jitter, of digital phase selection and phase-lock-loop (PLL) CDR circuits. This CDR circuit consists of a phase selector, which can lock to the data in just a few clock cycles but has high jitter, and a PLL, which requires a much longer lock time but provides a low-jitter clock after locking. Fabricated in a 0.5 μm CMOS process, the combined CDR achieves operation up to 750 Mbps. Measurements show at least a 6% acquisition range, an initial acquisition time of 8 bit times with jitter of 30% bit time, and jitter of 16 ps at 688 Mbps after a PLL lock time of 700 ns. Power dissipation is 300 mW and die area is 1.4 × 1.4 mm2. View full abstract»

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  • Through wafer interconnects on active pMOS devices

    Page(s): 82 - 84
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1375 KB) |  | HTML iconHTML  

    The objective of this research is to demonstrate the ability to create through-wafer interconnects (TWIs) on wafers with active devices. TWIs have previously been demonstrated on blank Si wafers. The application of TWIs in an industrial setting requires no damage or yield loss to the existing devices during additional processing steps. The test vehicle chosen is a simple pMOS test chip, which includes different structures such as transistors and invertors. The processing steps and sequence required to integrate TWIs into wafers with active devices is demonstrated. View full abstract»

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