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Compcon Spring '93, Digest of Papers.

Date 22-26 Feb. 1993

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Displaying Results 1 - 25 of 82
  • Continuous media: a paradigm shift in distributed systems

    Publication Year: 1993
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (73 KB)

    Summary form only given. The integration of digital audio and video (continuous media) in general-purpose distributed computer systems should eventually lead to the merger of computing, telecommunications, publishing, and broadcast media into a seamless global information environment. It is noted that the software prevalent in today's distributed systems cannot provide the performance properties n... View full abstract»

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  • StarWorks-a video applications server

    Publication Year: 1993, Page(s):4 - 11
    Cited by:  Papers (22)  |  Patents (28)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (660 KB)

    The authors describe StarWorks, a video applications server software designed to support a wide range of digital video applications. The StarWorks system will allow existing network applications, such as databases and groupware applications, to add video support. These applications can take advantage of the video application services to support the real-time demands of streaming data. Attention is... View full abstract»

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  • The Shark continuous-media file server

    Publication Year: 1993, Page(s):12 - 15
    Cited by:  Papers (22)  |  Patents (22)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (326 KB)

    Shark, a network file server for digital video and other continuous media data being developed at the IBM Almaden Research Center, is described. The high data rate and stringent time constraints of real-time video place heavy demands on a file server, and Shark implements a variety of novel features that enable it to efficiently handle video data. The Shark server runs on an RS/6000 workstation; i... View full abstract»

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  • The evolution of campus networks towards multimedia

    Publication Year: 1993, Page(s):49 - 58
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (750 KB)

    The authors consider the problem of providing bandwidth for multimedia services in a campus network. The campus network is composed of a number of subnetworks, interconnected by a backbone. The authors study each subnetwork in isolation, indicating what kinds of topologies should be used as a function of the bandwidth requirement, and then discuss the connection of the subnetwork to the backbone. ... View full abstract»

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  • Efficient query by image content for very large image databases

    Publication Year: 1993, Page(s):17 - 19
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (218 KB)

    The QBIC (query by image content) project in the IBM Almaden Research Center in San Jose, CA, is conducting a theoretical, experimental, and prototyping study of the problem of querying large still image databases efficiently based on image content. Since the problem is difficult, the aim is to discover general principles, but at the same time to identify target application(s) for which concrete p... View full abstract»

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  • Enabling multimedia-based collaboration

    Publication Year: 1993, Page(s):20 - 22
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (280 KB)

    The author describes some of the features available in Hewlett-Packard's media-enriched workstations, some of the challenges involved in creating an integrated multimedia environment, and some of the advances that the industry can expect in the next few years. Particular attention is given to the client-server architecture and the user model.<> View full abstract»

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  • When to use partitioned signature files for retrieving information in multimedia systems

    Publication Year: 1993, Page(s):23 - 28
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (543 KB)

    Some techniques based upon the partitioning of the signature file have been considered for improving the performance of the basic signature file access method. The authors discuss the performance issues of this approach. They identify the systems that can take advantage of this extended scheme. The following problems associated with the existing signature file partitioning methods based on the sup... View full abstract»

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  • Enhancement of token bus protocols for multimedia applications

    Publication Year: 1993, Page(s):30 - 36
    Cited by:  Papers (2)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (602 KB)

    The authors describe a method to enhance the medium access control (MAC) function of shared resource networks, such as buses. A new addressing field is introduced in the transmitted frames that allows multiple token visits in the same node within a single token rotation cycle. This method provides the capability to efficiently support dynamic bandwidth allocation and, thus, implement isochronous c... View full abstract»

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  • Transmission of compressed motion video over computer networks

    Publication Year: 1993, Page(s):37 - 46
    Cited by:  Papers (5)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (858 KB)

    The authors present an enhanced version of the real-time channel protocol for the transmission of compressed digital motion video over computer networks. This protocol can guarantee the timely delivery of video frames without wasting network bandwidth. Extensive simulation results have shown the protocol's superiority over the ordinary circuit/packet switching protocols.<> View full abstract»

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  • Real-time dissemination of continuous media in packet-switched networks

    Publication Year: 1993, Page(s):47 - 48
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (211 KB)

    The authors present a model of communication in a packet-switched network called continuous-media (CM) dissemination, which is the distribution of digital audio, video, and other periodic time-correlated data streams, from a source to multiple receivers. This model is similar to that of a cable TV system. The authors discuss an important design principle, the principle of loose coupling between a ... View full abstract»

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  • An overview of the Intel Pentium processor

    Publication Year: 1993, Page(s):60 - 62
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (180 KB)

    The Intel Pentium processor is the next generation high-performance processor, fully compatible with the i386/i486 CPUs. It is a Superscalar implementation of the x86 instruction set. The Pentium processor has 2-5*higher performance than the i486 CPU at the same frequency. Techniques used to achieve this level of performance are described. Attention is given to data integrity and functional redund... View full abstract»

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  • Optimizing systems performance based on Pentium processors

    Publication Year: 1993, Page(s):63 - 72
    Cited by:  Papers (4)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (701 KB)

    The Pentium processor is a new high-performance, i386/i486 compatible microprocessor. The authors describe targets of likely configurations of personal computers and servers based on the Pentium processor and provide simulation data which aid in the analysis of performance and price tradeoffs. Specific performance tradeoff data are provided for the processor-cache-memory interface.<> View full abstract»

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  • The Motorola 68060 microprocessor

    Publication Year: 1993, Page(s):73 - 78
    Cited by:  Papers (5)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (514 KB)

    The Motorola 68060, the fourth-generation microprocessor of the M68000 family, is described. Using object code compatible with previous family members, it delivers 3 to 3.5 times the performance of the previous generation processor in this family, the 68040. Performance features include a superscalar integer unit, a high-performance floating point unit, dual 8-kbyte on-chip caches, a branch cache,... View full abstract»

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  • ARM6: a high performance low power consumption macrocell

    Publication Year: 1993, Page(s):80 - 87
    Cited by:  Papers (1)  |  Patents (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (678 KB)

    A description is given of the ARM6, an ASIC (application-specific integrated circuit) CPU macrocell of 35530 transistors which offers high performance (28 K Dhrystones at 20 MHz) from an extremely small die size (3.1 mm*$1.9 mm on a 0.8- mu m CMOS process) and consumes very low levels of power (54 mW at 20 MHz at 3 V). The device has been designed to allow it to be easily incorporated into larger ... View full abstract»

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  • Hobbit: a high-performance, low-power microprocessor

    Publication Year: 1993, Page(s):88 - 95
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (583 KB)

    The class of portable hybrid computer/communication devices called personal communicators requires a microprocessor that simultaneously maximizes performance and minimizes power dissipation and silicon real estate. AT&T's 92010 Hobbit microprocessor combines reduced instruction set computer (RISC) architectural features, some non-RISC features, and an innovative electrical implementation to exactl... View full abstract»

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  • The low power Intel486 SL microprocessor

    Publication Year: 1993, Page(s):96 - 102
    Cited by:  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (526 KB)

    The author describes the Intel486 SL microprocessor and how the features are used to create robust, power managed portable computers. System performance was raised to the 25- and 33-MHz Intel486 DX microprocessor level. The system power consumption was significantly reduced with 3.3-V operation and power management refinements. The core system logic is reduced to at least half that of Intel386 SL ... View full abstract»

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  • PowerPC: a performance architecture

    Publication Year: 1993, Page(s):104 - 108
    Cited by:  Papers (10)  |  Patents (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (483 KB)

    The authors provide an overview of the PowerPC architecture. Some of the issues and decisions that helped shape this architecture are discussed. This architecture has incorporated the needs and ideas of leading software, system, and microprocessor design engineers. With input from this broad spectrum, the designers of PowerPC emerged with an architecture built for high-performance first-generation... View full abstract»

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  • The PowerPC 601 microprocessor

    Publication Year: 1993, Page(s):109 - 116
    Cited by:  Papers (12)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (837 KB)

    A highly integrated, single-chip microprocessor is described that combines a powerful reduced instruction set computer (RISC) architecture with a superscalar machine organization and a versatile, high-performance bus interface. The PowerPC 601 microprocessor contains a 32-kbyte cache and is capable of dispatching, executing, and completing up to three instructions per cycle. The bus interface can ... View full abstract»

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  • Multiprocessing aspects of the PowerPC 601

    Publication Year: 1993, Page(s):117 - 126
    Cited by:  Papers (6)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1012 KB)

    The authors describe the multiprocessing capabilities of the PowerPC architecture and the first implementation of that architecture, the 601 microprocessor. The architected multiprocessing (MP) facilities of PowerPC are presented, and the 601 microarchitecture and system interface are discussed in the context of multiprocessing support. It is pointed out that the PowerPC architecture and the 601 s... View full abstract»

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  • Overview of the Fujitsu VPP500 supercomputer

    Publication Year: 1993, Page(s):128 - 130
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (226 KB)

    The authors present an overview of the Fujitsu VPP500 vector parallel processor. The VPP500 is a high-performance, highly parallel distributed memory system. A crossbar network interconnects 4 to 222 processing elements, which gives a maximum system performance of up to 355 GFLOPS and an aggregate memory capacity of at most 55 Gbyte. The UNIX SVR4-based operating system, modified for the VPP500's ... View full abstract»

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  • High performance Fortran: an overview

    Publication Year: 1993, Page(s):132 - 136
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (444 KB)

    The author gives an overview of the work of the High Performance Fortran Forum (HPFF). This group of industry, academic, and user representatives has been meeting to define a set of extensions for Fortran dedicated to the special problems posed by very high performance computers, especially the new generation of parallel computers. The author describes the HPFF effort and its goals and gives a bri... View full abstract»

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  • Retargetable high performance Fortran compiler challenges

    Publication Year: 1993, Page(s):137 - 146
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (983 KB)

    The authors establish the need for a retargetable high performance Fortran (HPF) compilation system, discuss the various parallel systems, describe some of the technical compiler requirements needed to create a retargetable HPF compiler, and touch upon some of the issues related to compiler development such as tools and debugging. It is noted that HPF brings with it the promise of the first widely... View full abstract»

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  • Overview of the START(*T) multithreaded computer

    Publication Year: 1993, Page(s):148 - 156
    Cited by:  Papers (1)  |  Patents (27)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (730 KB)

    The author provides an overview of the START(*T) computer system being implemented by MIT and Motorola. *T is a scalable computer architecture designed to support a broad variety of parallel programming styles, including those which use multithreading to tolerate the increases in memory latency which occur as the machine size is scaled up. The hardware uses a customized reduced instruction set com... View full abstract»

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  • The synergistic effect of thread scheduling and caching in multithreaded computers

    Publication Year: 1993, Page(s):157 - 164
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (578 KB)

    The author investigates combining two techniques-thread scheduling and context switching on cache misses-in a multithreaded computer. By means of a simple simulation model for an eight-stage pipeline, it is demonstrated that these two techniques act together to allow higher overall processor performance with fewer running threads than the number of pipeline stages. Thus, two of the problems with m... View full abstract»

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  • Supporting a dynamic SPMD in a multi-threaded architecture

    Publication Year: 1993, Page(s):165 - 174
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (878 KB)

    The authors present a multithreaded architecture model which can efficiently support a single-program multiple-data (SPMD) computation of programs with dynamic data structures. It is based on a dynamic SPMD model where the access delay due to a remote reference of a dynamic data structure can be tolerated by having multiple threads of control concurrently in execution within each processor. Howeve... View full abstract»

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