Date 2427 May 1993
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Proceedings of 1993 IEEE International Symposium on Multiple Valued Logic (ISMVL '93)

Dreams for newdevicebased superchips: from transistors to enzymes
Page(s): 140  149The concept of multiplex computing is proposed to realize superchips free from interconnection problems. Parallel processing with multiplexable information carriers makes it possible to construct largescale, highly parallel systems with reduced interconnections. Possible implementation approaches based on frequencymode electronics, multiwave optoelectronics and bioelectronics are presented, and their advantages and disadvantages are discussed View full abstract»

Currentmode CMOS Galois field circuits
Page(s): 245  250The use of currentmode CMOS circuits for implementation of multiplevalued logic (MVL) functions is dealt with. In particular, an application of these circuits for realizing Galois field operation is presented. An algorithm for determining polynomial representations for arbitrary functions over a class of Galois fields implementable with presently available MVL circuits is given View full abstract»

EXORCISMMV2: minimization of exclusive sum of products expressions for multiplevalued input incompletely specified functions
Page(s): 132  137A cube operation, EXORLINK, and its application to the minimization of multiplevalued input, multioutput exclusive sums of products (ESOPs) for incompletely specified Boolean functions, are presented. EXORLINK generalizes all cube operations, such as crosslink, unlink, and Xmerge. The authors' program, EXORCISMMV2, gives efficient results for functions that are incompletely specified and have an arbitrary number of values for each of the input variables. This allows realization of a wider class of circuits that implement the multiplevalued input ESOP expressions. Evaluation on benchmark functions is also given and proves the superiority of the program to those known from the literature View full abstract»

Calculation of ternary mixed polarity function vector
Page(s): 236  238A onestep method for finding the ternary function vector
d is proposed. The heavy computational burden of previous approaches can be decreased by using the Kronecker product of function vectors. The result shows that the method is not only much more convenient but well suited to programming View full abstract» 
Semirigid sets of quasilinear clones
Page(s): 105  110Let
k be a prime andG a Galois field onk :={0,1,. . .,k 1}. The set of all quasilinear (or affine with respect toG )k valued logic functions is a maximal clone called quasilinear. A family of quasilinear clones onk is semirigid if the clones of the family share exactly the constant functions and the projections. Semirigid sets of quasilinear clones are needed for the classification of bases ofk valued logic, which is unknown fork >3. The authors characterize all semirigid sets of quasilinear clones. In particular, fork =5 they describe all semirigid triples of quasilinear clones and show that no such pair exists. For every primek >5 they exhibit a semirigid pair of quasilinear clones. The techniques used are based on elementary number theory and on polynomials overG View full abstract» 
Fast synthesis for ternary ReedMuller expansion
Page(s): 14  16A direct algorithm for calculating ReedMuller coefficients under each fixed polarity is derived. This algorithm has not only a simple procedure but also much lower computational cost than the stepbystep flow graph algorithm with the polarities in Gray code order of D.H. Green (1989). Therefore, it lends itself to fast parallel computation View full abstract»

Synthesis and design automation of analog fuzzy logic VLSI circuits
Page(s): 74  79A mathematical synthesis of currentmirrorbased VLSI circuits suitable for design automation is proposed. In particular, a unified approach to synthesizing analog, currentmode CMOS fuzzy logic circuits is presented. The mathematical approach used for the fuzzy logic function synthesis is suitable for synthesis and design automation purposes. The approach is implemented in a prototype framework for automated synthesis and layout generation. By utilizing the existing software packages, VEETest and GDT Designer, efficiency, portability and compatibility are obtained. The advantage of the system over the classic design approach is demonstrated by the design of the fuzzy membership function circuit and the fuzzy logic controller circuit View full abstract»

An algebra for currentmode CMOS multivalued circuits
Page(s): 239  244Based on the transmission function theory for voltagemode CMOS circuits, an algebra for currentmode CMOS multivalued circuits is proposed. In this algebra, the switching state of MOS transistor and the current signal are represented by two kinds of variables, respectively. Some operations are introduced, their properties are discussed, and the synthesis of currentmode CMOS multivalued circuits by algebraic means is presented. A design example shows that this theory not only can explain currentmode CMOS multivalued circuits proposed previously, but also develops new designs with simpler construction View full abstract»

A multiplevalued contentaddressable memory using logicvalue conversion and threshold functions
Page(s): 170  175A highdensity multiplevalued contentaddressable memory (MVCAM) for applications such as database systems and pattern recognition is presented. The basic search operations executed in an MVCAM are both the threshold operations in each cell and logicvalue conversion against multiplevalued input data. Various multiplevalued operations for data retrieval can be easily performed by programming logicvalue conversion. Moreover, the cell circuit can be implemented using two transistors and one capacitor. The cell circuit is used not only to store multilevel charge but also to execute sum calculation by the capacitive coupling technique. As a result, the cell circuit is very simple and the chip area of the cell circuit can be reduced by 54% of that of the equivalent binary implementation View full abstract»

CMOS implementation and fabrication of the pseudo analog neuron
Page(s): 266  270The pseudoanalog neuron (PAN) uses a transresistance amplifier and multivalued logic design techniques to implement the basic building blocks of artificial neural networks. The performance characteristics of PAN building blocks that were implemented in a standard 2μm CMOS process are described. A twolayer network of PANs is used to implement various Boolean functions. The twolayer circuit computes ten weighted sum of inputs plus four thresholds in the first layer, and a four weighted sum plus one threshold in the second layer. All thresholding and weighted sums are propagated in 10 ns through both layers. This circuit dissipates 250 μW of average power, and occupies 288 μm×136 μm of silicon area View full abstract»

Lukasiewicz' insect: the role of continuousvalued logic in a mobile robot's sensors, control, and locomotion
Page(s): 258  263The ability to physically realize a colony of insectlike robots presents numerous problems. A hexapod robot controlled by a computational sensor is proposed as a solution to some of these problems. Stiquito is a small nitinolpropelled robot. It is controlled by a computational sensor implemented with Lukasiewicz logic arrays (LLAs). The computational sensor includes an electronic retina, an implicit controller, and a gait generator. Measured and simulated results illustrate the unifying effect of Lukasiewicz logic on the design of the robotic system View full abstract»

Novel CMOS scan design for VLSI testability
Page(s): 82  86A CMOS scan design that uses a ternary clock signal is presented. The routing of the long modecontrol input signal is thus eliminated. Unlike previous efforts to eliminate the modecontrol input, no additional MOS transistors are required in this design. Moreover, it has the same CMOS network as the traditional design; only the thresholds of the MOS transistors are varied. Computer simulations with SPICE2G5 show that it can realize the expected logic functions and it has the desirable transfer characteristics View full abstract»

A fast algorithm for the disjunctive decomposition of
Page(s): 126  131m valued functions. II. Time complexity analysisFor part I see ibid., p.11825. The time complexity of the fast algorithm for the disjunctive decomposition of
m valued functions, proposed in part I is studied. A probabilistic approach is used to estimate the time complexity for randomm valued functions, where several statistical properties of such functions are obtained and used in the analysis. It is shown that the time complexity for random functions is of the order of (nm )^{3}. In the case in which a random function has a single disjunctive decomposition, the time complexity becomes of the ordern ^{3 }m ^{n}. The algorithm was simulated on a digital computer. The experimental results are in agreement with the theoretical predictions View full abstract» 
Design and examination of a multiplevalued flipflop circuit with stair shaped IV curved device as a coupling element
Page(s): 152  157A stairtype multiplevalued flipflop (MVFF) in which a device with the stairshaped
I V curve is used for coupling the inverter is described. A pair of the quantizing inverters whose input and output are crosscoupled has many stable states. The MVFF designs are verified by actual circuits in which the coupling circuits consist of constantcurrent diodes and Zener diodes. A compact device with the stairshapedI V curve is obtained by inserting a stairshaped gap between gate and drain in an ordinary MOSFET. Using this device as the coupling element for the inverter, the quantized MVFF circuit is examined View full abstract» 
Decimal addition and subtraction units using the
Page(s): 228  233p valued decimal signeddigit number representationParallel addition and subtraction of two numbers with signeddigit number representation can be performed in constant time. A signeddigit representation for radix
r =10 (SD10R) is presented, and the usefulness of asymmetrical SD10R is considered. The authors proposep (qk . . .q 1)valued SD10Rs in whichp is represented as a combination ofqk toq 1. They also describe ap (q 2q 1)valued SD10R addition and subtraction unit in whichp is large. Simulation data for typical SD10Rs are compared View full abstract» 
On functional entropy
Page(s): 100  104A numerical characteristic of functions between finite sets that satisfies certain properties related to common operations applied to functions is defined. Unlike the notion of entropy of a probability distribution, the entropy of a function has an algebraic rather than a probabilistic character, although the two notions are clearly related. Applications of this notion to the study of finite functions are indicated View full abstract»

Algorithm and implementation of a learning multiplevalued logic network
Page(s): 202  207A learning technique and implementation for multiplevalued logic (MVL) networks are described. The learning problem is formulated as a minimization of an error function that represents a measure of distortion between actual and desired output. A gradientbased leastsquareerror minimization algorithm is used to minimize the error function, which in contrast to the backpropagation algorithm, does not involve a sigmoid function and requires only a simple sgn function in the learning rule. The algorithm trains the networks using examples and appears to be available in practice for most multiplevalued problems of interest. Circuit implementations of the learning MVL networks using CMOS currentmode circuits are described View full abstract»

On the definition of modal operators in fuzzy logic
Page(s): 62  67The classical modal logic with Kripke semantics is generalized in two ways. First, the set {0,1} consisting of the logical values 0 (false) and 1 (true) is replaced by the set [0,1] of all real numbers
x with 0⩽x ⩽1. The concept of Kripke semantics is generalized to this logic, but the accessibility relationR is still assumed as crisp, i.e.,R WS×WS, where WS is the set of worlds considered. The accessibility relation is generalized by taking it as a soft relationS :WS×WS→[0,1]. Several problems of interpreting two of the modal operators on the basis of this concept are discussed View full abstract» 
Singlechip realization of a fuzzy logic controller with neural network structure (NNFLC)
Page(s): 68  73An NNFLC has been studied and designed employing the technology of currentmode multivalued CMOS and analog E^{2}PROM. The NNFLC uses a neural network for knowledge memory instead of an ifthen knowledge. This NNFLC behaves more intelligently than any traditional fuzzy logic control system. A singlechip applicationspecific integrated circuit (ASIC) realization of such NNFL has been designed. The circuit has a systolic mesh structure with single clock control, bidirectional data flow, and an analogtodigital/digitaltoanalog converting interface View full abstract»

Multiplevalued logic functions represented by TSUM, TPRODUCT, NOT and variables
Page(s): 222  227A class of multiplevalued logic functions (TOfunctions, for short) expressed by TSUM, TPRODUCT, NOT, and variables is introduced, where TSUM is defined as min (
x +y ,p 1) and TPRODUCT is redefined as the product that is derived by applying De Morgan's laws to TSUM. It is shown that a set of TOfunctions is not a lattice, and that in ternary logic TSUM can be expressed by Lukasiewicz implication, and NOT and its converse holds. It is known that a set of ternary TOfunctions is not complete but complete with constants. Moreover, the set is equivalent to ternary functions satisfying normality and includes a set of Bternary logic functions. For any radix, it is shown that a set of TOfunctions is not complete but compete with constants and that the set includes Bmultiplevalued logic functions. Moreover, some speculations of the number of TOfunctions for less than ten radixes are derived View full abstract» 
Multiplevalued logic computation circuits using micro and nanoelectronic devices
Page(s): 164  169The advantages of the negative transconductance of the resonant tunneling transistor (RTT) for implementing very efficient multivaluedlogic (MVL) arithmetic building blocks are examined. Full adders are described for both the positivedigit 2.4 redundant number system and the signeddigit 4.3 minimumredundant number system. The outlook for nanoelectronic MVL is considered View full abstract»

Multiplevalued PLA minimization by concurrent multiple and mixed simulated annealing
Page(s): 17  23Simulated annealing applied to multiplevalued programmable logic array (MVL PLA) design is analyzed. Of specific interest is the use of parallel processors. The use of loosely coupled, coarsegrained parallel systems is considered, and the relationship between the quality of the solution and computation time, on the one hand and simulated annealing parameters (start temperature, cooling rate, etc.) on the other is studied. Simulated annealing is also investigated in the case in which there is a mixture of move types. The mixedmove approach provides improvement in both the number of product terms and computation time View full abstract»

A canonical disjunctive form of extended KleeneStone logic functions
Page(s): 36  41The authors define αKS logic functions as infinite multiplevalued logic functions, adding a unary operation to fuzzy logic functions. The unary operation introduced is an extension of a unary operation of KleeneStone logic functions. Any αKS logic function can be expanded into a disjunctive form, but the form is not determined uniquely. A special disjunctive form that can be determined uniquely for a given αKS logic function is shown View full abstract»

Some results on the decision and construction for Sheffer functions in partial
Page(s): 111  116k valued logicDecisions and construction for Sheffer functions in
P _{k} andP _{k}* in partialk valued logic are considered. The solution of these problems depends on the solution of the decision problem of completeness inP _{k} andP _{k}* and is reduced to determining the minimal coverings of precomplete classes inP _{k} andP _{k}*, respectively. The pseudolinear function set denoted byL _{p} is proved here to be the component part of the minimal covering of precomplete classes inP _{k}* View full abstract»