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# [1993] Proceedings of the Twenty-Third International Symposium on Multiple-Valued Logic

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Displaying Results 1 - 25 of 45
• ### Proceedings of 1993 IEEE International Symposium on Multiple Valued Logic (ISMVL '93)

Publication Year: 1993
| PDF (187 KB)
• ### Multiple valued logic: current-mode CMOS circuits

Publication Year: 1993, Page(s):176 - 181
Cited by:  Papers (4)
| | PDF (652 KB)

Several of the current-mode CMOS multiple-valued-logic (MVL) circuits that the author has studied over the past decade are reviewed. These circuits include a simple current threshold comparator, MVL encoders and decoders, quaternary threshold logic full adders (QFAs), MVL latches, latched QFA circuits, and analog-to-quaternary converter circuits View full abstract»

• ### Functional completeness and weak completeness in set logic

Publication Year: 1993, Page(s):251 - 256
Cited by:  Papers (7)
| | PDF (488 KB)

The functional completeness problems in r-valued set logic, which is the logic of functions mapping n-tuples of subsets into subset over r values, is discussed. It is shown that r-valued set logic is isomorphic to 2r-valued logic, meaning that the well-known completeness criteria in multiple-valued Post algebras apply to set-valued logic. Since Boolea... View full abstract»

• ### Design of set-valued logic networks for wave-parallel computing

Publication Year: 1993, Page(s):277 - 282
Cited by:  Papers (5)
| | PDF (524 KB)

A design for set-valued logic (SVL) networks that provides a solution to interconnection problems in highly parallel VLSI systems is presented. The basic concept is frequency multiplexing of logic values, which enables the parallelism of electrical (or optical) waves to be used for parallel processing. This wave-parallel computing concept is capable of performing several independent binary functio... View full abstract»

• ### A method of test pattern generation for multiple-valued PLAs

Publication Year: 1993, Page(s):87 - 91
Cited by:  Papers (1)
| | PDF (300 KB)

An easy test pattern generation (ETPG) method is developed for multiple-valued programmable logic arrays (MV PLAs). The ETPG so generated can detect crosspoint faults, weight faults, and their fault positions. In comparison with binary ETPG, it is shown that the number of test vectors does not increase as fast as the radix number of multiple-valued functions increases. The ETPG method for a produc... View full abstract»

• ### A representation of approximate reasoning with analogy

Publication Year: 1993, Page(s):184 - 189
Cited by:  Papers (1)
| | PDF (436 KB)

A scheme of approximate reasoning with analogical inference is proposed for purpose of flexible inference. This method uses truth value [0,1] based on possibility and assigns a truth value called certainty factor (cf) ∈[0,1] to the implication A→B. This inference conclusion is derived as a product of the truth value T(A) of the fact A and cert... View full abstract»

• ### Series resonant tunneling diodes as a two-dimensional memory cell

Publication Year: 1993, Page(s):158 - 163
Cited by:  Papers (7)  |  Patents (1)
| | PDF (300 KB)

A state-of-the-art multiple-variable memory cell that can provide many-quanta stable states is proposed. The basic cell is composed of two resonant tunneling diodes (RTDs) connected in series with a load. Access lines are connected to every joint between any two devices. When properly biased, the cell can have (N+1)2 or more stable quantized operating states that are defined by... View full abstract»

• ### Lukasiewicz' insect: the role of continuous-valued logic in a mobile robot's sensors, control, and locomotion

Publication Year: 1993, Page(s):258 - 263
Cited by:  Papers (2)  |  Patents (7)
| | PDF (496 KB)

The ability to physically realize a colony of insect-like robots presents numerous problems. A hexapod robot controlled by a computational sensor is proposed as a solution to some of these problems. Stiquito is a small nitinol-propelled robot. It is controlled by a computational sensor implemented with Lukasiewicz logic arrays (LLAs). The computational sensor includes an electronic retina, an impl... View full abstract»

• ### Design of multiple-valued linear digital circuits for highly parallel unary operations

Publication Year: 1993, Page(s):283 - 288
Cited by:  Papers (6)
| | PDF (304 KB)

A design method for highly parallel multiple-valued linear digital circuits for unary operations using the concept of a cycle and a tree is proposed. In the circuit design, an analytical approach using a representation matrix is possible, so that the search procedure for optimal locally computable circuits becomes very simple. Some examples are shown to demonstrate the usefulness of the design alg... View full abstract»

• ### A repairable and diagnosable cellular array on multiple-valued logic

Publication Year: 1993, Page(s):92 - 97
Cited by:  Papers (1)  |  Patents (13)
| | PDF (408 KB)

A diagnosable and repairable k-valued cellular array is proposed, assuming a single fault, i.e., either a stuck-at-0 fault or a stuck-at-(k-1) fault of switches, occurs in the array. By building in a duplicate column iteratively, a fault-tolerant array can be constructed for the stuck-at-(k-1) fault, therefore, since the stuck-at-(k-1) fault need not be diagnose... View full abstract»

• ### An inexact reasoning technique using linguistic rule matrix transformations

Publication Year: 1993, Page(s):190 - 195
Cited by:  Papers (1)
| | PDF (324 KB)

A technique for dealing with inexact reasoning using linguistic rule matrix transformations is presented. It is assumed that the linguistic terms are represented by trapezoidal fuzzy numbers. However, the linguistic terms can also be represented by other membership functions, such as the S-function, the π function, and the close to' function. In this case, the fuzzy numbers plausible... View full abstract»

• ### Multiple-valued logic computation circuits using micro- and nanoelectronic devices

Publication Year: 1993, Page(s):164 - 169
Cited by:  Papers (24)  |  Patents (4)
| | PDF (352 KB)

The advantages of the negative transconductance of the resonant tunneling transistor (RTT) for implementing very efficient multivalued-logic (MVL) arithmetic building blocks are examined. Full adders are described for both the positive-digit 2.4 redundant number system and the signed-digit 4.3 minimum-redundant number system. The outlook for nanoelectronic MVL is considered View full abstract»

• ### An algebra for current-mode CMOS multivalued circuits

Publication Year: 1993, Page(s):239 - 244
Cited by:  Papers (2)
| | PDF (252 KB)

Based on the transmission function theory for voltage-mode CMOS circuits, an algebra for current-mode CMOS multivalued circuits is proposed. In this algebra, the switching state of MOS transistor and the current signal are represented by two kinds of variables, respectively. Some operations are introduced, their properties are discussed, and the synthesis of current-mode CMOS multivalued circuits ... View full abstract»

• ### CMOS implementation and fabrication of the pseudo analog neuron

Publication Year: 1993, Page(s):266 - 270
Cited by:  Patents (6)
| | PDF (296 KB)

The pseudo-analog neuron (PAN) uses a transresistance amplifier and multivalued logic design techniques to implement the basic building blocks of artificial neural networks. The performance characteristics of PAN building blocks that were implemented in a standard 2-μm CMOS process are described. A two-layer network of PANs is used to implement various Boolean functions. The two-layer circuit c... View full abstract»

• ### EXORCISM-MV-2: minimization of exclusive sum of products expressions for multiple-valued input incompletely specified functions

Publication Year: 1993, Page(s):132 - 137
Cited by:  Papers (11)
| | PDF (448 KB)

A cube operation, EXORLINK, and its application to the minimization of multiple-valued input, multi-output exclusive sums of products (ESOPs) for incompletely specified Boolean functions, are presented. EXORLINK generalizes all cube operations, such as crosslink, unlink, and X-merge. The authors' program, EXORCISM-MV-2, gives efficient results for functions that are incompletely specified and have... View full abstract»

• ### Fast synthesis for ternary Reed-Muller expansion

Publication Year: 1993, Page(s):14 - 16
Cited by:  Papers (8)
| | PDF (148 KB)

A direct algorithm for calculating Reed-Muller coefficients under each fixed polarity is derived. This algorithm has not only a simple procedure but also much lower computational cost than the step-by-step flow graph algorithm with the polarities in Gray code order of D.H. Green (1989). Therefore, it lends itself to fast parallel computation View full abstract»

• ### On functional entropy

Publication Year: 1993, Page(s):100 - 104
Cited by:  Papers (6)
| | PDF (272 KB)

A numerical characteristic of functions between finite sets that satisfies certain properties related to common operations applied to functions is defined. Unlike the notion of entropy of a probability distribution, the entropy of a function has an algebraic rather than a probabilistic character, although the two notions are clearly related. Applications of this notion to the study of finite funct... View full abstract»

• ### Algebraic properties of a learning multiple-valued logic network

Publication Year: 1993, Page(s):196 - 201
Cited by:  Papers (5)
| | PDF (304 KB)

A simple arithmetic piecewise linear operator that can be used as a basic element to construct a large multiple-valued network is defined. The algebra is proved to be a functionally complete set and capable of constructing any multiple-valued logic functions. The layered piecewise linear node networks provide a natural and general architecture for backpropagation, thus making a learning multiple-v... View full abstract»

• ### A canonical disjunctive form of extended Kleene-Stone logic functions

Publication Year: 1993, Page(s):36 - 41
Cited by:  Patents (1)
| | PDF (412 KB)

The authors define α-KS logic functions as infinite multiple-valued logic functions, adding a unary operation to fuzzy logic functions. The unary operation introduced is an extension of a unary operation of Kleene-Stone logic functions. Any α-KS logic function can be expanded into a disjunctive form, but the form is not determined uniquely. A special disjunctive form that can be determ... View full abstract»

• ### A multiple-valued content-addressable memory using logic-value conversion and threshold functions

Publication Year: 1993, Page(s):170 - 175
Cited by:  Papers (1)
| | PDF (396 KB)

A high-density multiple-valued content-addressable memory (MVCAM) for applications such as database systems and pattern recognition is presented. The basic search operations executed in an MVCAM are both the threshold operations in each cell and logic-value conversion against multiple-valued input data. Various multiple-valued operations for data retrieval can be easily performed by programming lo... View full abstract»

• ### Current-mode CMOS Galois field circuits

Publication Year: 1993, Page(s):245 - 250
Cited by:  Papers (16)
| | PDF (396 KB)

The use of current-mode CMOS circuits for implementation of multiple-valued logic (MVL) functions is dealt with. In particular, an application of these circuits for realizing Galois field operation is presented. An algorithm for determining polynomial representations for arbitrary functions over a class of Galois fields implementable with presently available MVL circuits is given View full abstract»

• ### Impact of interconnection-free biomolecular computing

Publication Year: 1993, Page(s):271 - 276
Cited by:  Papers (7)
| | PDF (472 KB)

A model of an interconnection-free computing system using biodevices is presented. The fundamental concept is the interconnection-free logic operation based on parallel distribution of logical information represented by varieties of molecules, and parallel selection using specificity of enzymes. The impact of interconnection-free computing on highly parallel processing architectures is analyzed th... View full abstract»

• ### Novel CMOS scan design for VLSI testability

Publication Year: 1993, Page(s):82 - 86
| | PDF (228 KB)

A CMOS scan design that uses a ternary clock signal is presented. The routing of the long mode-control input signal is thus eliminated. Unlike previous efforts to eliminate the mode-control input, no additional MOS transistors are required in this design. Moreover, it has the same CMOS network as the traditional design; only the thresholds of the MOS transistors are varied. Computer simulations wi... View full abstract»

• ### Design and examination of a multiple-valued flip-flop circuit with stair shaped I-V curved device as a coupling element

Publication Year: 1993, Page(s):152 - 157
Cited by:  Papers (1)  |  Patents (1)
| | PDF (368 KB)

A stair-type multiple-valued flip-flop (MVFF) in which a device with the stair-shaped I-V curve is used for coupling the inverter is described. A pair of the quantizing inverters whose input and output are cross-coupled has many stable states. The MVFF designs are verified by actual circuits in which the coupling circuits consist of constant-current diodes and Zener diodes. A com... View full abstract»

• ### Calculation of ternary mixed polarity function vector

Publication Year: 1993, Page(s):236 - 238
| | PDF (160 KB)

A one-step method for finding the ternary function vector d is proposed. The heavy computational burden of previous approaches can be decreased by using the Kronecker product of function vectors. The result shows that the method is not only much more convenient but well suited to programming View full abstract»