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Multiple-Valued Logic, 1993., Proceedings of The Twenty-Third International Symposium on

Date 24-27 May 1993

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  • Proceedings of 1993 IEEE International Symposium on Multiple Valued Logic (ISMVL '93)

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    Freely Available from IEEE
  • Dreams for new-device-based superchips: from transistors to enzymes

    Page(s): 140 - 149
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    The concept of multiplex computing is proposed to realize superchips free from interconnection problems. Parallel processing with multiplexable information carriers makes it possible to construct large-scale, highly parallel systems with reduced interconnections. Possible implementation approaches based on frequency-mode electronics, multiwave optoelectronics and bioelectronics are presented, and their advantages and disadvantages are discussed View full abstract»

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  • Current-mode CMOS Galois field circuits

    Page(s): 245 - 250
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    The use of current-mode CMOS circuits for implementation of multiple-valued logic (MVL) functions is dealt with. In particular, an application of these circuits for realizing Galois field operation is presented. An algorithm for determining polynomial representations for arbitrary functions over a class of Galois fields implementable with presently available MVL circuits is given View full abstract»

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  • EXORCISM-MV-2: minimization of exclusive sum of products expressions for multiple-valued input incompletely specified functions

    Page(s): 132 - 137
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    A cube operation, EXORLINK, and its application to the minimization of multiple-valued input, multi-output exclusive sums of products (ESOPs) for incompletely specified Boolean functions, are presented. EXORLINK generalizes all cube operations, such as crosslink, unlink, and X-merge. The authors' program, EXORCISM-MV-2, gives efficient results for functions that are incompletely specified and have an arbitrary number of values for each of the input variables. This allows realization of a wider class of circuits that implement the multiple-valued input ESOP expressions. Evaluation on benchmark functions is also given and proves the superiority of the program to those known from the literature View full abstract»

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  • Calculation of ternary mixed polarity function vector

    Page(s): 236 - 238
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    A one-step method for finding the ternary function vector d is proposed. The heavy computational burden of previous approaches can be decreased by using the Kronecker product of function vectors. The result shows that the method is not only much more convenient but well suited to programming View full abstract»

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  • Semirigid sets of quasilinear clones

    Page(s): 105 - 110
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    Let k be a prime and G a Galois field on k :={0,1,. . .,k-1}. The set of all quasilinear (or affine with respect to G) k-valued logic functions is a maximal clone called quasilinear. A family of quasilinear clones on k is semirigid if the clones of the family share exactly the constant functions and the projections. Semirigid sets of quasilinear clones are needed for the classification of bases of k-valued logic, which is unknown for k>3. The authors characterize all semirigid sets of quasilinear clones. In particular, for k=5 they describe all semirigid triples of quasilinear clones and show that no such pair exists. For every prime k>5 they exhibit a semirigid pair of quasi-linear clones. The techniques used are based on elementary number theory and on polynomials over G View full abstract»

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  • Fast synthesis for ternary Reed-Muller expansion

    Page(s): 14 - 16
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    A direct algorithm for calculating Reed-Muller coefficients under each fixed polarity is derived. This algorithm has not only a simple procedure but also much lower computational cost than the step-by-step flow graph algorithm with the polarities in Gray code order of D.H. Green (1989). Therefore, it lends itself to fast parallel computation View full abstract»

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  • Synthesis and design automation of analog fuzzy logic VLSI circuits

    Page(s): 74 - 79
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    A mathematical synthesis of current-mirror-based VLSI circuits suitable for design automation is proposed. In particular, a unified approach to synthesizing analog, current-mode CMOS fuzzy logic circuits is presented. The mathematical approach used for the fuzzy logic function synthesis is suitable for synthesis and design automation purposes. The approach is implemented in a prototype framework for automated synthesis and layout generation. By utilizing the existing software packages, VEE-Test and GDT Designer, efficiency, portability and compatibility are obtained. The advantage of the system over the classic design approach is demonstrated by the design of the fuzzy membership function circuit and the fuzzy logic controller circuit View full abstract»

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  • An algebra for current-mode CMOS multivalued circuits

    Page(s): 239 - 244
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    Based on the transmission function theory for voltage-mode CMOS circuits, an algebra for current-mode CMOS multivalued circuits is proposed. In this algebra, the switching state of MOS transistor and the current signal are represented by two kinds of variables, respectively. Some operations are introduced, their properties are discussed, and the synthesis of current-mode CMOS multivalued circuits by algebraic means is presented. A design example shows that this theory not only can explain current-mode CMOS multivalued circuits proposed previously, but also develops new designs with simpler construction View full abstract»

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  • A multiple-valued content-addressable memory using logic-value conversion and threshold functions

    Page(s): 170 - 175
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    A high-density multiple-valued content-addressable memory (MVCAM) for applications such as database systems and pattern recognition is presented. The basic search operations executed in an MVCAM are both the threshold operations in each cell and logic-value conversion against multiple-valued input data. Various multiple-valued operations for data retrieval can be easily performed by programming logic-value conversion. Moreover, the cell circuit can be implemented using two transistors and one capacitor. The cell circuit is used not only to store multilevel charge but also to execute sum calculation by the capacitive coupling technique. As a result, the cell circuit is very simple and the chip area of the cell circuit can be reduced by 54% of that of the equivalent binary implementation View full abstract»

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  • CMOS implementation and fabrication of the pseudo analog neuron

    Page(s): 266 - 270
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    The pseudo-analog neuron (PAN) uses a transresistance amplifier and multivalued logic design techniques to implement the basic building blocks of artificial neural networks. The performance characteristics of PAN building blocks that were implemented in a standard 2-μm CMOS process are described. A two-layer network of PANs is used to implement various Boolean functions. The two-layer circuit computes ten weighted sum of inputs plus four thresholds in the first layer, and a four weighted sum plus one threshold in the second layer. All thresholding and weighted sums are propagated in 10 ns through both layers. This circuit dissipates 250 μW of average power, and occupies 288 μm×136 μm of silicon area View full abstract»

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  • Lukasiewicz' insect: the role of continuous-valued logic in a mobile robot's sensors, control, and locomotion

    Page(s): 258 - 263
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    The ability to physically realize a colony of insect-like robots presents numerous problems. A hexapod robot controlled by a computational sensor is proposed as a solution to some of these problems. Stiquito is a small nitinol-propelled robot. It is controlled by a computational sensor implemented with Lukasiewicz logic arrays (LLAs). The computational sensor includes an electronic retina, an implicit controller, and a gait generator. Measured and simulated results illustrate the unifying effect of Lukasiewicz logic on the design of the robotic system View full abstract»

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  • Novel CMOS scan design for VLSI testability

    Page(s): 82 - 86
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    A CMOS scan design that uses a ternary clock signal is presented. The routing of the long mode-control input signal is thus eliminated. Unlike previous efforts to eliminate the mode-control input, no additional MOS transistors are required in this design. Moreover, it has the same CMOS network as the traditional design; only the thresholds of the MOS transistors are varied. Computer simulations with SPICE2G5 show that it can realize the expected logic functions and it has the desirable transfer characteristics View full abstract»

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  • A fast algorithm for the disjunctive decomposition of m-valued functions. II. Time complexity analysis

    Page(s): 126 - 131
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    For part I see ibid., p.118-25. The time complexity of the fast algorithm for the disjunctive decomposition of m-valued functions, proposed in part I is studied. A probabilistic approach is used to estimate the time complexity for random m-valued functions, where several statistical properties of such functions are obtained and used in the analysis. It is shown that the time complexity for random functions is of the order of (nm)3. In the case in which a random function has a single disjunctive decomposition, the time complexity becomes of the order n3 mn. The algorithm was simulated on a digital computer. The experimental results are in agreement with the theoretical predictions View full abstract»

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  • Design and examination of a multiple-valued flip-flop circuit with stair shaped I-V curved device as a coupling element

    Page(s): 152 - 157
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    A stair-type multiple-valued flip-flop (MVFF) in which a device with the stair-shaped I-V curve is used for coupling the inverter is described. A pair of the quantizing inverters whose input and output are cross-coupled has many stable states. The MVFF designs are verified by actual circuits in which the coupling circuits consist of constant-current diodes and Zener diodes. A compact device with the stair-shaped I-V curve is obtained by inserting a stair-shaped gap between gate and drain in an ordinary MOSFET. Using this device as the coupling element for the inverter, the quantized MVFF circuit is examined View full abstract»

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  • Decimal addition and subtraction units using the p-valued decimal signed-digit number representation

    Page(s): 228 - 233
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    Parallel addition and subtraction of two numbers with signed-digit number representation can be performed in constant time. A signed-digit representation for radix r=10 (SD10R) is presented, and the usefulness of asymmetrical SD10R is considered. The authors propose p(qk. . .q1)-valued SD10Rs in which p is represented as a combination of qk to q1. They also describe a p(q2q1)-valued SD10R addition and subtraction unit in which p is large. Simulation data for typical SD10Rs are compared View full abstract»

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  • On functional entropy

    Page(s): 100 - 104
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    A numerical characteristic of functions between finite sets that satisfies certain properties related to common operations applied to functions is defined. Unlike the notion of entropy of a probability distribution, the entropy of a function has an algebraic rather than a probabilistic character, although the two notions are clearly related. Applications of this notion to the study of finite functions are indicated View full abstract»

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  • Algorithm and implementation of a learning multiple-valued logic network

    Page(s): 202 - 207
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    A learning technique and implementation for multiple-valued logic (MVL) networks are described. The learning problem is formulated as a minimization of an error function that represents a measure of distortion between actual and desired output. A gradient-based least-square-error minimization algorithm is used to minimize the error function, which in contrast to the backpropagation algorithm, does not involve a sigmoid function and requires only a simple sgn function in the learning rule. The algorithm trains the networks using examples and appears to be available in practice for most multiple-valued problems of interest. Circuit implementations of the learning MVL networks using CMOS current-mode circuits are described View full abstract»

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  • On the definition of modal operators in fuzzy logic

    Page(s): 62 - 67
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    The classical modal logic with Kripke semantics is generalized in two ways. First, the set {0,1} consisting of the logical values 0 (false) and 1 (true) is replaced by the set [0,1] of all real numbers x with 0⩽x⩽1. The concept of Kripke semantics is generalized to this logic, but the accessibility relation R is still assumed as crisp, i.e., RWS×WS, where WS is the set of worlds considered. The accessibility relation is generalized by taking it as a soft relation S:WS×WS→[0,1]. Several problems of interpreting two of the modal operators on the basis of this concept are discussed View full abstract»

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  • Single-chip realization of a fuzzy logic controller with neural network structure (NNFLC)

    Page(s): 68 - 73
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    An NNFLC has been studied and designed employing the technology of current-mode multivalued CMOS and analog E2PROM. The NNFLC uses a neural network for knowledge memory instead of an if-then knowledge. This NNFLC behaves more intelligently than any traditional fuzzy logic control system. A single-chip application-specific integrated circuit (ASIC) realization of such NNFL has been designed. The circuit has a systolic mesh structure with single clock control, bidirectional data flow, and an analog-to-digital/digital-to-analog converting interface View full abstract»

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  • Multiple-valued logic functions represented by TSUM, TPRODUCT, NOT and variables

    Page(s): 222 - 227
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    A class of multiple-valued logic functions (TO-functions, for short) expressed by TSUM, TPRODUCT, NOT, and variables is introduced, where TSUM is defined as min (x+y, p-1) and TPRODUCT is redefined as the product that is derived by applying De Morgan's laws to TSUM. It is shown that a set of TO-functions is not a lattice, and that in ternary logic TSUM can be expressed by Lukasiewicz implication, and NOT and its converse holds. It is known that a set of ternary TO-functions is not complete but complete with constants. Moreover, the set is equivalent to ternary functions satisfying normality and includes a set of B-ternary logic functions. For any radix, it is shown that a set of TO-functions is not complete but compete with constants and that the set includes B-multiple-valued logic functions. Moreover, some speculations of the number of TO-functions for less than ten radixes are derived View full abstract»

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  • Multiple-valued logic computation circuits using micro- and nanoelectronic devices

    Page(s): 164 - 169
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    The advantages of the negative transconductance of the resonant tunneling transistor (RTT) for implementing very efficient multivalued-logic (MVL) arithmetic building blocks are examined. Full adders are described for both the positive-digit 2.4 redundant number system and the signed-digit 4.3 minimum-redundant number system. The outlook for nanoelectronic MVL is considered View full abstract»

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  • Multiple-valued PLA minimization by concurrent multiple and mixed simulated annealing

    Page(s): 17 - 23
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    Simulated annealing applied to multiple-valued programmable logic array (MVL PLA) design is analyzed. Of specific interest is the use of parallel processors. The use of loosely coupled, coarse-grained parallel systems is considered, and the relationship between the quality of the solution and computation time, on the one hand and simulated annealing parameters (start temperature, cooling rate, etc.) on the other is studied. Simulated annealing is also investigated in the case in which there is a mixture of move types. The mixed-move approach provides improvement in both the number of product terms and computation time View full abstract»

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  • A canonical disjunctive form of extended Kleene-Stone logic functions

    Page(s): 36 - 41
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    The authors define α-KS logic functions as infinite multiple-valued logic functions, adding a unary operation to fuzzy logic functions. The unary operation introduced is an extension of a unary operation of Kleene-Stone logic functions. Any α-KS logic function can be expanded into a disjunctive form, but the form is not determined uniquely. A special disjunctive form that can be determined uniquely for a given α-KS logic function is shown View full abstract»

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  • Some results on the decision and construction for Sheffer functions in partial k-valued logic

    Page(s): 111 - 116
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    Decisions and construction for Sheffer functions in Pk and Pk* in partial k-valued logic are considered. The solution of these problems depends on the solution of the decision problem of completeness in P k and Pk* and is reduced to determining the minimal coverings of precomplete classes in P k and Pk*, respectively. The pseudo-linear function set denoted by Lp is proved here to be the component part of the minimal covering of precomplete classes in Pk* View full abstract»

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