[1993] Proceedings of the Twenty-Third International Symposium on Multiple-Valued Logic

24-27 May 1993

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  • Proceedings of 1993 IEEE International Symposium on Multiple Valued Logic (ISMVL '93)

    Publication Year: 1993
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    Freely Available from IEEE
  • Multiple-valued logic design tools

    Publication Year: 1993, Page(s):2 - 11
    Cited by:  Papers (52)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (828 KB)

    A brief overview of past progress in multiple-valued logic design is presented. The methods are considered with respect to the likely development of multiple-valued field programmable gate arrays. Look-up table based arrays are considered in some detail and an algorithm for mapping multiple-valued functions to such an array is presented. This algorithm uses reduced order multiple-valued decision d... View full abstract»

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  • Series resonant tunneling diodes as a two-dimensional memory cell

    Publication Year: 1993, Page(s):158 - 163
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (300 KB)

    A state-of-the-art multiple-variable memory cell that can provide many-quanta stable states is proposed. The basic cell is composed of two resonant tunneling diodes (RTDs) connected in series with a load. Access lines are connected to every joint between any two devices. When properly biased, the cell can have (N+1)2 or more stable quantized operating states that are defined by... View full abstract»

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  • On the definition of modal operators in fuzzy logic

    Publication Year: 1993, Page(s):62 - 67
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB)

    The classical modal logic with Kripke semantics is generalized in two ways. First, the set {0,1} consisting of the logical values 0 (false) and 1 (true) is replaced by the set [0,1] of all real numbers x with 0⩽x⩽1. The concept of Kripke semantics is generalized to this logic, but the accessibility relation R is still assumed as crisp, i.e., RWS×WS... View full abstract»

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  • Fast synthesis for ternary Reed-Muller expansion

    Publication Year: 1993, Page(s):14 - 16
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (148 KB)

    A direct algorithm for calculating Reed-Muller coefficients under each fixed polarity is derived. This algorithm has not only a simple procedure but also much lower computational cost than the step-by-step flow graph algorithm with the polarities in Gray code order of D.H. Green (1989). Therefore, it lends itself to fast parallel computation View full abstract»

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  • Multiple-valued logic computation circuits using micro- and nanoelectronic devices

    Publication Year: 1993, Page(s):164 - 169
    Cited by:  Papers (23)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB)

    The advantages of the negative transconductance of the resonant tunneling transistor (RTT) for implementing very efficient multivalued-logic (MVL) arithmetic building blocks are examined. Full adders are described for both the positive-digit 2.4 redundant number system and the signed-digit 4.3 minimum-redundant number system. The outlook for nanoelectronic MVL is considered View full abstract»

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  • Single-chip realization of a fuzzy logic controller with neural network structure (NNFLC)

    Publication Year: 1993, Page(s):68 - 73
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (372 KB)

    An NNFLC has been studied and designed employing the technology of current-mode multivalued CMOS and analog E2PROM. The NNFLC uses a neural network for knowledge memory instead of an if-then knowledge. This NNFLC behaves more intelligently than any traditional fuzzy logic control system. A single-chip application-specific integrated circuit (ASIC) realization of such NNFL has been desig... View full abstract»

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  • Multiple-valued logic functions represented by TSUM, TPRODUCT, NOT and variables

    Publication Year: 1993, Page(s):222 - 227
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (400 KB)

    A class of multiple-valued logic functions (TO-functions, for short) expressed by TSUM, TPRODUCT, NOT, and variables is introduced, where TSUM is defined as min (x+y, p-1) and TPRODUCT is redefined as the product that is derived by applying De Morgan's laws to TSUM. It is shown that a set of TO-functions is not a lattice, and that in ternary logic TSUM can be expressed b... View full abstract»

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  • A fast algorithm for the disjunctive decomposition of m-valued functions. II. Time complexity analysis

    Publication Year: 1993, Page(s):126 - 131
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB)

    For part I see ibid., p.118-25. The time complexity of the fast algorithm for the disjunctive decomposition of m-valued functions, proposed in part I is studied. A probabilistic approach is used to estimate the time complexity for random m-valued functions, where several statistical properties of such functions are obtained and used in the analysis. It is shown that the time comp... View full abstract»

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  • Multiple-valued PLA minimization by concurrent multiple and mixed simulated annealing

    Publication Year: 1993, Page(s):17 - 23
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (560 KB)

    Simulated annealing applied to multiple-valued programmable logic array (MVL PLA) design is analyzed. Of specific interest is the use of parallel processors. The use of loosely coupled, coarse-grained parallel systems is considered, and the relationship between the quality of the solution and computation time, on the one hand and simulated annealing parameters (start temperature, cooling rate, etc... View full abstract»

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  • A multiple-valued content-addressable memory using logic-value conversion and threshold functions

    Publication Year: 1993, Page(s):170 - 175
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (396 KB)

    A high-density multiple-valued content-addressable memory (MVCAM) for applications such as database systems and pattern recognition is presented. The basic search operations executed in an MVCAM are both the threshold operations in each cell and logic-value conversion against multiple-valued input data. Various multiple-valued operations for data retrieval can be easily performed by programming lo... View full abstract»

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  • Synthesis and design automation of analog fuzzy logic VLSI circuits

    Publication Year: 1993, Page(s):74 - 79
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (540 KB)

    A mathematical synthesis of current-mirror-based VLSI circuits suitable for design automation is proposed. In particular, a unified approach to synthesizing analog, current-mode CMOS fuzzy logic circuits is presented. The mathematical approach used for the fuzzy logic function synthesis is suitable for synthesis and design automation purposes. The approach is implemented in a prototype framework f... View full abstract»

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  • Decimal addition and subtraction units using the p-valued decimal signed-digit number representation

    Publication Year: 1993, Page(s):228 - 233
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (484 KB)

    Parallel addition and subtraction of two numbers with signed-digit number representation can be performed in constant time. A signed-digit representation for radix r=10 (SD10R) is presented, and the usefulness of asymmetrical SD10R is considered. The authors propose p(qk. . .q1)-valued SD10Rs in which p is represented as a combination of qk to ... View full abstract»

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  • EXORCISM-MV-2: minimization of exclusive sum of products expressions for multiple-valued input incompletely specified functions

    Publication Year: 1993, Page(s):132 - 137
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (448 KB)

    A cube operation, EXORLINK, and its application to the minimization of multiple-valued input, multi-output exclusive sums of products (ESOPs) for incompletely specified Boolean functions, are presented. EXORLINK generalizes all cube operations, such as crosslink, unlink, and X-merge. The authors' program, EXORCISM-MV-2, gives efficient results for functions that are incompletely specified and have... View full abstract»

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  • Three-valued nonmonotonic logic

    Publication Year: 1993, Page(s):42 - 47
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (496 KB)

    The three-valued formulation of nonmonotonic logics is established. It is shown how to extend standard nonmonotonic logics to the three-valued case. It is also shown that a three-valued nonmonotonic logic called maximally ignorant (MI) logic can capture various major standard nonmonotonic logics as its special cases. It is argued that the three-valued nonmonotonic logic is closely related to modal... View full abstract»

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  • Design of multiple-valued linear digital circuits for highly parallel unary operations

    Publication Year: 1993, Page(s):283 - 288
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB)

    A design method for highly parallel multiple-valued linear digital circuits for unary operations using the concept of a cycle and a tree is proposed. In the circuit design, an analytical approach using a representation matrix is possible, so that the search procedure for optimal locally computable circuits becomes very simple. Some examples are shown to demonstrate the usefulness of the design alg... View full abstract»

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  • Entropic minimization of multiple-valued functions

    Publication Year: 1993, Page(s):24 - 28
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (300 KB)

    An information-theoretic procedure for minimizing multiple-valued switching function is outlined. The procedure has been developed as an extension of previous works about heuristic decision making and binary switching function minimization for the sum of products expansion of the function to be minimized. To show how the proposed procedure works, a complete example for a three-variable, four-value... View full abstract»

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  • CMOS implementation and fabrication of the pseudo analog neuron

    Publication Year: 1993, Page(s):266 - 270
    Cited by:  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (296 KB)

    The pseudo-analog neuron (PAN) uses a transresistance amplifier and multivalued logic design techniques to implement the basic building blocks of artificial neural networks. The performance characteristics of PAN building blocks that were implemented in a standard 2-μm CMOS process are described. A two-layer network of PANs is used to implement various Boolean functions. The two-layer circuit c... View full abstract»

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  • Multiple valued logic: current-mode CMOS circuits

    Publication Year: 1993, Page(s):176 - 181
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (652 KB)

    Several of the current-mode CMOS multiple-valued-logic (MVL) circuits that the author has studied over the past decade are reviewed. These circuits include a simple current threshold comparator, MVL encoders and decoders, quaternary threshold logic full adders (QFAs), MVL latches, latched QFA circuits, and analog-to-quaternary converter circuits View full abstract»

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  • Algebraic properties of a learning multiple-valued logic network

    Publication Year: 1993, Page(s):196 - 201
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB)

    A simple arithmetic piecewise linear operator that can be used as a basic element to construct a large multiple-valued network is defined. The algebra is proved to be a functionally complete set and capable of constructing any multiple-valued logic functions. The layered piecewise linear node networks provide a natural and general architecture for backpropagation, thus making a learning multiple-v... View full abstract»

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  • Novel CMOS scan design for VLSI testability

    Publication Year: 1993, Page(s):82 - 86
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (228 KB)

    A CMOS scan design that uses a ternary clock signal is presented. The routing of the long mode-control input signal is thus eliminated. Unlike previous efforts to eliminate the mode-control input, no additional MOS transistors are required in this design. Moreover, it has the same CMOS network as the traditional design; only the thresholds of the MOS transistors are varied. Computer simulations wi... View full abstract»

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  • Calculation of ternary mixed polarity function vector

    Publication Year: 1993, Page(s):236 - 238
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (160 KB)

    A one-step method for finding the ternary function vector d is proposed. The heavy computational burden of previous approaches can be decreased by using the Kronecker product of function vectors. The result shows that the method is not only much more convenient but well suited to programming View full abstract»

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  • Dreams for new-device-based superchips: from transistors to enzymes

    Publication Year: 1993, Page(s):140 - 149
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (712 KB)

    The concept of multiplex computing is proposed to realize superchips free from interconnection problems. Parallel processing with multiplexable information carriers makes it possible to construct large-scale, highly parallel systems with reduced interconnections. Possible implementation approaches based on frequency-mode electronics, multiwave optoelectronics and bioelectronics are presented, and ... View full abstract»

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  • Signed formulas and annotated logics

    Publication Year: 1993, Page(s):48 - 53
    Cited by:  Papers (9)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB)

    The relationship between signed formulas and annotated logics, two approaches that some authors have used to analyze multiple-valued logics (MVLs), is explored. A special case of the signed resolution rule is shown to be equivalent to, and thus to unify, the two inference rules, resolution and reduction, of annotated logic, raising the possibility of an SLD-style resolution rule for annotated logi... View full abstract»

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  • Gate model networks for minimization of multiple-valued logic functions

    Publication Year: 1993, Page(s):29 - 34
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (420 KB)

    The use of gate model networks as a logic minimization method for multiple-valued logic functions is proposed. The gate model network is a kind of neural network constructed like and AND-OR two-level circuits using two gate models: an AND type gate model and an OR type gate model. The backpropagation (BP) method is used to train the network until it realizes the minimal solution. A solution is der... View full abstract»

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