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ASIC, 2003. Proceedings. 5th International Conference on

21-24 Oct. 2003

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  • Physical implementation and test of energy recovery circuit

    Publication Year: 2003, Page(s):1205 - 1208 Vol.2
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (291 KB)

    This paper presents a new structure of energy recovery logic named improved energy recovery logic (IERL) and discusses the physical implementation issues. A feasible test schemes for function verification and power measurement of energy recovery logic circuit is proposed and put in practice. The test results verified the proper function of IERL 2-bit full adder (FA) circuit and the low power perfo... View full abstract»

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  • SEA: fast power estimation for micro-architectures

    Publication Year: 2003
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (316 KB)

    As dimensions in silicon technology continue to shrink and hence enable to design complete system-on-chip (SOC) with several million transistors on a single piece of silicon, power consumption of SOCs becomes a major design challenge. The reasons are manifold: 1) the increasing integration imposes cooling problems since the power density (Watts/mm2) on a micro chip reaches levels equal ... View full abstract»

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  • Low power circuits and microarchitectures for gigascale integration

    Publication Year: 2003, Page(s):1194 - 1199 Vol.2
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (477 KB)

    Technology scaling continues providing integration capacity of billions of transistor; however, power delivery and dissipation are the barriers. Supply voltage scaling - which provides relief in active power reduction - has to slow down to limit subthreshold leakage. A variation in process, temperature, and supply voltage forces a major change in the design paradigm, from deterministic to probabil... View full abstract»

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  • Boundary-scan test circuit designed for FPGA

    Publication Year: 2003, Page(s):1190 - 1193 Vol.2
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (356 KB)

    Boundary scan is a widely adopted DFT (design for test). According to the characteristic of FPGA application, this paper presents a boundary scan circuit designed for FDEGA (field-programmable datapath enhanced gate array), an FPGA new architecture of our group. The design emphasizes the function of PCB level test while considering chip level test function as well. We also integrate device-program... View full abstract»

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  • Investigation of silicon substrate thickness effects on inductor

    Publication Year: 2003, Page(s):1120 - 1123 Vol.2
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB)

    In this paper, the thickness of silicon substrate with backside metallization effects on the inductor performance were investigated, the experimental results showed that thinner substrate with backside metallization resulted in smaller inductance and slightly higher resonant frequency. For circular spiral inductor with substrate thickness of 50μm, the inductance L with eight turns would be degr... View full abstract»

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  • A DFT and test pattern generation methodology for an ARM powered® SoC design

    Publication Year: 2003, Page(s):1186 - 1189 Vol.2
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB)

    This paper describes the design-for-testability (DFT) methodology for an ARM powered SoC (system-on-a-chip) design which is named by Garfield and used for hand-held computing. Various test methods, including scan insertion, memory BIST (built-in self-test), boundary scan and functional test, and the strategies merging the above methods in SoC design are discussed in detail. View full abstract»

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  • Influence of metal layer thickness of spiral inductors on the quality factor by 3-D EM simulation

    Publication Year: 2003, Page(s):1117 - 1119 Vol.2
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (298 KB)

    The influence of the inductor thickness on the Q factor has been analyzed in detail by the 3-D electromagnetic simulator HFSS. For spiral inductors based on the CMOS compatible Cu/SiO2 interconnect technology, the improvement of the Q factor can be realized by increasing the metal layer thickness due to the decrease of the series resistance. However, such improvement of the Q factor bec... View full abstract»

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  • Authors' index

    Publication Year: 2003, Page(s):1385 - 1392
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (315 KB)

    First Page of the Article
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  • A new BIST structure for low power testing

    Publication Year: 2003, Page(s):1183 - 1185 Vol.2
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (258 KB)

    A new simple built-in-self-test (BIST) structure for low power testing is presented in this paper. The principle of the proposed method is to reconstruct the LFSR circuit to reduce the WSA of the circuit under test (CUT) by choosing the CUT's heavy inputs. Experimental results shows that it can efficiently reduce the number of transitions in the CUT; hence decrease the total power consumption duri... View full abstract»

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  • A transponder IC for wireless auto identification system

    Publication Year: 2003, Page(s):1114 - 1116 Vol.2
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (242 KB)

    A batteryless, self-powered transponder used in the wireless auto identification system is proposed in this paper. The paper works in a frequency of 915MHz. The transponder extracts energy from the RF field from the RFID station, and stores it for the following working phases. The transponder works in three phases. First, the transponder decodes the data bit from the RFID station. Most of the digi... View full abstract»

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  • Analysis and computer simulation of BJMOSFET frequency characteristics

    Publication Year: 2003, Page(s):1381 - 1384 Vol.2
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (306 KB)

    The high frequency equivalent model of new semiconductor device - bipolar junction MOS field effect transistor (BJMOSFET) was proposed. Various kinds of parasitic electric capacity of BJMOSFET and its influences were qualitative analyzed. By utilizing the existing components and parts in PSPICE9 device storehouse, the BJMOSFET frequency characteristic equivalent circuit that was used to analogue a... View full abstract»

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  • Scalable elliptic curve encryption processor for portable application

    Publication Year: 2003, Page(s):1312 - 1316 Vol.2
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (363 KB)

    This paper presents the design and implementation of an energy efficient, scalable elliptic curve encryption processor over GF(2m) for portable application. The proposed processor contains three hierarchical controllers and one reconfigurable datapath to operate various finite field arithmetic. Scalable register is used to fit different elliptic curves and alterable field degree m (from... View full abstract»

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  • A 1.2V, 1.8 GHz CMOS two-stage LNA with common-gate amplifier as an input stage

    Publication Year: 2003, Page(s):1042 - 1045 Vol.2
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (307 KB)

    This paper presents a 1.2V CMOS 2-stage low-noise amplifier (LNA) operating at 1.8 GHz. The amplifier can provide a power gain of 17.4 dB with a low noise figure of about 1 dB. The input and output reflection coefficient (S11 and S22) are -6.4 and -31.8 dB, respectively. In this circuit, common-gate amplifier with noise matching is employed as the input stage to achieve this ... View full abstract»

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  • Advanced topics of DFT technologies in a general purposed CPU chip

    Publication Year: 2003, Page(s):1179 - 1182 Vol.2
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (386 KB)

    Design-for-testability (DFT) is widely used in current integrated circuit design to enhance the controllability and observability of signals. The technologies insert extra logics into an original design, running in test mode without any functional influence. How to make all the test logics work harmoniously and obtain high fault coverage with low area and performance overhead are the two main issu... View full abstract»

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  • A 2.5-V 2.45/5.25 GHz dual-band CMOS LNA

    Publication Year: 2003, Page(s):1110 - 1113 Vol.2
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (268 KB)

    The design of a 2.45/5.25 GHz dual-band CMOS LNA is presented. S21 at 2.45/5.25 GHz are 13.2 and 10.5 dB, respectively. NF at 2.45/5.25 GHz is 1.7 and 2.4 dB, respectively. Dual-band input matching id derived in detail. In-band and cross-band linearity performances are also discussed. The LNA takes 12.5 mA from 2.5 V. View full abstract»

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  • A VLSI chip of SCLA based 2-D DWT/IDWT

    Publication Year: 2003, Page(s):898 - 901 Vol.2
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (324 KB)

    We have designed a VLSI chip of spatial combinative lifting algorithm (SCLA) based 2-D biorthogonal DWT/IDWT. This DWT/IDWT processor is implemented with 9/7, 5/3 Daubechies filters and 5-level Mallat decomposition method, which can possess 30 frames per second with image resolution up to 1280 × 1024 × 24 bits under 50 MHz system clock. This processor is fabricated with DONGBU 0.25 &mu... View full abstract»

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  • A FPGA-based voltage regulation control unit for optical phased array beam deflector

    Publication Year: 2003, Page(s):1377 - 1380 Vol.2
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (266 KB)

    The hardware design and FPGA implementation of a voltage regulation control unit for optical phased array beam deflector is described. With the control unit used for a 16-channel waveguide phased array beam deflector, a beam scan rate above 500 kHz can be achieved, which is far higher than that obtained with other implementation methods based on microcontrollers. View full abstract»

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  • Design and implementation of a high-speed programmable polyphase FIR filter

    Publication Year: 2003, Page(s):783 - 787 Vol.2
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (311 KB)

    FIR filters that provide linear phases are frequently used in digital signal processing, voice and data transmission. Polyphase FIR filters are applied in many practical applications of DSPs that require the sampling rate of a signal to be changed. This paper describes the design and implementation of a high-speed programmable polyphase FIR filter. The FIR is designed to run automatically under al... View full abstract»

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  • Design of an RSA module against power analysis attacks

    Publication Year: 2003, Page(s):1308 - 1311 Vol.2
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (284 KB)

    Power analysis attacks could be used to analyze the key information according to leakage information depending on the operation of cryptography algorithm and its hardware. They are highly effective with low cost. In this paper, an improved RSA algorithm against power analysis was proposed based on its basic theory. DPA attack for RSA specially, is discussed in details. In order to maximize the cap... View full abstract»

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  • New design of RF interface circuits for PICC complying with ISO/IEC14443-2 type B

    Publication Year: 2003, Page(s):1037 - 1041 Vol.2
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (339 KB)

    This paper demonstrates a new set of RF circuits design proposal for PICC complying with ISO/IEC 14443-2 Type B, expatiates on the topology of typical modules and addresses its advantage over former design. The simulation data by Hspice, with the corresponding test of this chip is also given in the following thesis. The design has been implemented upon 0.8 μm CMOS technology successfully. The p... View full abstract»

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  • Verification and auto test for LCD driver/controller

    Publication Year: 2003, Page(s):1175 - 1178 Vol.2
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (305 KB)

    Along with the requirements of application, the mixed-signal circuit - LCD driver/controller has more output pins and gradation voltage levels, which makes the verification and test difficult. This paper builds a system-level verification platform for LCD driver/controller circuit, in this module we convert the simulation file for behavioral simulation to test patterns for auto test machine, and w... View full abstract»

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  • The design of CMOS RF low noise amplifiers

    Publication Year: 2003, Page(s):1106 - 1109 Vol.2
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (272 KB)

    A design approach of CMOS radio frequency (RF) low noise amplifiers (LNAs) is presented in this paper. With short-channel MOSFET model, analytical model of the source degenerated amplifiers is derived and verified by simulation at 2.4GHz with 0.18μm technology. It is shown that low noise and low power may probably be achieved simultaneously. With the help of these models, the designer can not o... View full abstract»

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  • Power performance with gated clocks of a pipelined Cordic core

    Publication Year: 2003, Page(s):1226 - 1230 Vol.2
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (391 KB)

    This paper presents the evaluation in power consumption of gated clocks pipelined circuits with different register configurations in Virtex-based FPGA devices. Power impact of a gated clock circuitry aimed at reducing flip-flops output rate at the bit level is studied. Power performance is also given for pipeline stages based on the implementation of a double edge-triggered flip-flop. Using a pipe... View full abstract»

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  • A 1V, 2.4GHz fully integrated LNA using 0.18μm CMOS technology

    Publication Year: 2003, Page(s):1062 - 1065 Vol.2
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (318 KB)

    A 1V, 2.4GHz fully integrated CMOS low noise amplifier (LNA) including the 50 Ω referenced input output matching networks is implemented using 0.18μm technology within a chip area of 4.1mm2. The amplifier has the noise figure (NF) of 3.8dB and forward gain of more than 20dB. The details of the LNA analysis and design procedure are presented in this paper. View full abstract»

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  • Low power architecture of digital IF receiver for CDMA mobile stations

    Publication Year: 2003, Page(s):804 - 807 Vol.2
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (286 KB)

    This paper presents a low-power digital IF (Intermediate Frequency) receiver using IIR (Infinite Impulse Response) filters for CDMA (Code Division Multiple Access) system. The proposed digital IF receiver is based on a conventional multi-stage decimation FIR (Finite Impulse Response) filter. In the proposed digital IF receiver, we change a FIR filter to a simple IIR filter and optimize the operati... View full abstract»

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