ASIC, 2003. Proceedings. 5th International Conference on

21-24 Oct. 2003

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  • A direct digital frequency synthesizer based on CORDIC algorithm implemented with FPGA

    Publication Year: 2003, Page(s):832 - 835 Vol.2
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (285 KB)

    A direct digital frequency synthesizer (DDFS) applied to digital modulation is presented, which can synthesize a 16-bit output sine and cosine wave with a spectrum density of -100 dB at 50 MHz. The synthesizer covers a bandwidth from dc to 25 MHz in steps of 0.18 Hz with latency of 11 clock cycles. The structure is based on CORDIC algorithm. The whole digital system is implemented with FPGA. View full abstract»

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  • A pipelined low power architectural MPEG-4 video codec chip with deblocking filter for mobile wireless multimedia applications

    Publication Year: 2003, Page(s):934 - 937 Vol.2
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB)

    We present a low-power MPEG-4 video codec chip capable of delivering high-quality video data in mobile wireless multimedia applications. The discussions focus on the architectural design techniques for implementing a high-performance and low power consumption video compression/decompression chip. By introducing partitioning of HW/SW modules, the efficiently optimized frame memory interface archite... View full abstract»

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  • Low power architecture of digital IF receiver for CDMA mobile stations

    Publication Year: 2003, Page(s):804 - 807 Vol.2
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (286 KB)

    This paper presents a low-power digital IF (Intermediate Frequency) receiver using IIR (Infinite Impulse Response) filters for CDMA (Code Division Multiple Access) system. The proposed digital IF receiver is based on a conventional multi-stage decimation FIR (Finite Impulse Response) filter. In the proposed digital IF receiver, we change a FIR filter to a simple IIR filter and optimize the operati... View full abstract»

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  • A new ROMless twiddle factor generator for radix-2 1024-point FFT

    Publication Year: 2003, Page(s):828 - 831 Vol.2
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (322 KB)

    A low power 16-bit ROMless twiddle factor generator for radix-2 1024-point FFT is designed. This twiddle factor generator consists of several simple logic units and each of them is used to regenerate one group of the twiddle factors that is summed together by a bus. The power analysis with Synopsys power compiler shows that the power consumed by this twiddle factor generator is less than the power... View full abstract»

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  • A novel built-in CMOS sensor for on-line thermal monitoring of VLSI circuits

    Publication Year: 2003, Page(s):1345 - 1348 Vol.2
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (275 KB)

    Built-in temperature sensors increase the system reliability by predicting eventual faults caused by excessive chip temperatures. In this paper, a novel temperature sensor is presented, developed by the authors especially for the purpose of thermal monitoring of VLSI chips. This proposed sensor require very small silicon area and power consumption and the accuracy is in the order of 0.8°C. View full abstract»

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  • System level design of radio frequency receivers for wireless communications

    Publication Year: 2003, Page(s):930 - 933 Vol.2
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (329 KB)

    In this paper, we present some basic concepts and techniques used in system level design of radio frequency (RF) receivers. For the first time in the literature, a systematic design methodology to distribute the receiver overall radio specifications into individual building blocks and lead to the minimum power consumption design is introduced. The proposed methodology has been demonstrated by a lo... View full abstract»

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  • A new architecture of matched-filter employing coefficient recode technique for spread spectrum communication systems

    Publication Year: 2003, Page(s):800 - 803 Vol.2
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (278 KB)

    The digital matched-filter (DMF) has been widely used in direct sequence spread spectrum (DSSS) communications systems. In this paper, we present a new architecture of DMF for DSSS communication systems by employing the coefficient recode technique. According to the new architecture, the complexity of DMF is approximately reduced more than 50% of that of conventional digital matched filter (CDMF) ... View full abstract»

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  • A high-performance 32-bit parallel multiplier using modified Booth's algorithm and sign-deduction algorithm

    Publication Year: 2003, Page(s):1281 - 1284 Vol.2
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (286 KB)

    A high-performance 32-bit parallel multiplier is proposed in this paper. A modified Booth's algorithm is used to unify signed/unsigned numbers operation and a new sign-deduction algorithm is used to eliminate the sign bits array of partial products. This multiplier is used in a 400MHz high performance and full-custom designed 32-bit embedded microprocessor compatible with MIPS 32 4 KC developed by... View full abstract»

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  • CINRAD C-band design based on Altera CPLD and LVDS technology

    Publication Year: 2003, Page(s):824 - 827 Vol.2
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (308 KB)

    Building on its NEXRAD (Next Radar) heritage, CINRAD (Chinese Next Generation Radar) incorporates many technological advances to further enhance performance, reliability and can be easily upgraded. These include an open system workstation platforms, VLSI DSP signal processor, network communications, real-time display, fibre-optical transfer, and new scan modes. The CINRAD signal processor hardware... View full abstract»

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  • A new modeling and parameter extraction technique for uni-directional high-voltage MOS devices

    Publication Year: 2003, Page(s):984 - 987 Vol.2
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (263 KB)

    In this paper, a new method of modeling uni-directional HV MOS device based on the common BSIM3V3 model is presented. We propose to assign physical meanings and values of three model parameters different from the original BSIM3V model based on BSIM3V3 user manual (1995) but not change any equation of it to model the characteristics of uni-directional HV MOS devices. The way of accurate parameters ... View full abstract»

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  • Fabrication of Si and SiGe vertical dual carrier field effect transistor and its SOI resistor load switching ASIC with effective channel length of 30nm

    Publication Year: 2003, Page(s):1341 - 1344 Vol.2
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (254 KB)

    Fabrication of Si and SiGe vertical dual carrier field effect transistor (VDCFET) with effective channel length of 30nm, using lithographic equipment for linewidths greater than 180nm, is presented. The main process of fabrication used is ion implantation for Si VDCFET. The main process of fabrication used is molecular beam epitaxy for SiGe VDCFET. Fabrication of SOI switching VDCFET flip flop wit... View full abstract»

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  • A real-time Chinese speech recognition IC with double mixtures

    Publication Year: 2003, Page(s):926 - 929 Vol.2
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (321 KB)

    A hidden Markov model (HMM) based isolated word recognizer IC is presented in this paper. The test chip was fabricated with a 0.35 μm CMOS technology. In this design double-mixture probability density and table look-up method are employed. The chip can operate at 20MHz at 3.3V and at this frequency the recognition time is 0.5 sec for a 50-word speech library. Tested with 353 speech data from AU... View full abstract»

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  • Possibility of combined use of neuron-MOS and RTD in multi-valued logic circuits

    Publication Year: 2003, Page(s):1357 - 1360 Vol.2
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (252 KB)

    In this paper, the possibility of combined use of neuron-MOS and resonant tunnelling diode is investigated. Two application examples in MVL circuits are described. Three basic forms of combined use are proposed. The advantages and disadvantages are analyzed. View full abstract»

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  • A VLSI architecture of EBCOT encoder for JPEG2000

    Publication Year: 2003, Page(s):882 - 885 Vol.2
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (347 KB)

    Embedded block coding with optimized truncation (EBCOT) algorithm plays a basic and crucial part in JPEG2000 still image compression system. This paper proposes VLSI architecture of EBCOT, in which a dynamic memory control (DMC) strategy is used to reduce 60% of the on-chip wavelet coefficients storage. A parallel architecture is proposed to speed-up the coding process. This architecture can be us... View full abstract»

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  • Maximum power-up current estimation of power-gated circuits

    Publication Year: 2003, Page(s):1243 - 1246 Vol.2
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (382 KB)

    Power gating is an effective technology to reduce both dynamic power and static power. To design low leakage and high performance systems, it's very needed to predict the maximum current of power-gated circuits, which is determined by the maximum of all possible power-up and normal switching currents. In this paper, hazards are found to consume a significant portion of total power during powering ... View full abstract»

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  • An improved CMOS RF low noise amplifier

    Publication Year: 2003, Page(s):1102 - 1105 Vol.2
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (228 KB)

    In this paper, a CMOS RF low noise amplifier (LNA) with an improved input matching architecture is given. It is proved both in theory and by simulation that the noise figure and the gain of the amplifier are only very slightly affected by such an input network. View full abstract»

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  • A 2.4GHz CMOS LNA with full ESD protection

    Publication Year: 2003, Page(s):1058 - 1061 Vol.2
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (377 KB)

    This paper proposed a CMOS LNA with full ESD protection, which means that all pads of this circuit can sustain a HBM stress up to 2kV under various zapping modes. Using all standard devices provided by the foundry with their parasitic included, the verification of the ESD performance in the circuit design process can be executed very easily and the results are reliable. Besides of the remarkable E... View full abstract»

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  • Downlink joint detection in TD-SCDMA for hardware implementation

    Publication Year: 2003, Page(s):796 - 799 Vol.2
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (248 KB)

    Time division synchronous code division multiple access (TD-SCDMA) is the time division duplex (TDD) mode in the 3rd generation mobile radio system. Typical joint detection techniques can only be used in uplink due to its high computational complexity in TD-SCDMA system. A novel joint detection designed for hardware implementation is introduced in this paper. By dividing the matrix into smaller su... View full abstract»

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  • Implementation of video format conversion

    Publication Year: 2003, Page(s):958 - 961 Vol.2
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (297 KB)

    In this paper we present an implementation of video format converter (VFC). The VFC can be used to transform one video format to another video format. The input and output video formats could be PAL, NTSC, SECAM, SDTV, HDTV etc. The architecture of VFC is software reconfigurable. That means pixel number per line, period of line, frequency of frame and scan format (interlaced/progressive) can be ch... View full abstract»

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  • An asynchronous add-compare-select design in CMOS VLSI

    Publication Year: 2003, Page(s):1277 - 1280 Vol.2
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (266 KB)

    A novel asynchronous ACS (Add-Compare-Select) is described. The circuit of a novel asynchronous comparator unit is proposed. The performance of ACS is analyzed with the novel method based on multi-delay model. The results of performance analysis of asynchronous ACS show that the average case response time 3.66ns is only 45% the worst-case response time 8.1ns. It reveals that the asynchronous ACS h... View full abstract»

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  • Design of reusable test platform for microprocessor

    Publication Year: 2003, Page(s):1132 - 1135 Vol.2
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (257 KB)

    In this paper we present a design of a reusable test platform for microprocessors. This platform could automatically adapt to different set of microprocessors under test. It could be configured to various functional test environments as required, and also it integrates a CMDL (code mapping description language) assembler which gains general-purpose assemble capability to enhance the instructional-... View full abstract»

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  • Design of an asynchronous ACS for Viterbi decoder

    Publication Year: 2003, Page(s):820 - 823 Vol.2
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (279 KB)

    In this paper, we present a new asynchronous ACS (adder-compare-select) unit, which is a key building block in the Viterbi decoder. Asynchronous self-timed control and DCVSL (Differential Cascade Voltage Switch Logic) have been used in the ACS unit. The simulation results show that the average case response time 3.51ns is only 42.6% the worst case response time 8.23ns. This explains that the async... View full abstract»

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  • A novel scheme to measure the power of AC system with FPGA

    Publication Year: 2003, Page(s):1151 - 1154 Vol.2
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB)

    Nowadays, most digital power measurement is based on DSP. This paper proposed a field programmable gate array (FPGA) implemented digital elements in the power measurement of AC system. The main difference is that FPGA allow concurrent operation, enabling high performance which levels achieved are orders of magnitude greater than those obtained with traditional digital signal processor. The design ... View full abstract»

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  • Test scheduling for system-on-a-chip using test resource grouping

    Publication Year: 2003, Page(s):1167 - 1170 Vol.2
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (303 KB)

    Test scheduling has been known to be one of the efficient techniques for reducing testing time of system-on-a-chip (SoC). In this paper, a heuristic algorithm, in which test resources are grouped and arranged, based on the size of product of power dissipation and test time of each core together with total power consumption in core-based SoC is proposed. We select test resource groups which have ma... View full abstract»

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  • A parallel FSM design method and its application in ten gigabit Ethernet access chip

    Publication Year: 2003, Page(s):870 - 873 Vol.2
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (310 KB)

    The data flow rate in ten gigabit Ethernet access chip is so high that the chip uses a 64-bit data channel. But the interface between the host and the access chip is 32-bit in width. So the chip needs a parallel interface and a parallel FSM that controls the interface. This paper presents a block diagram for the ten gigabit Ethernet access system and a solution for the parallel FSM design problem. View full abstract»

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