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ASIC, 2003. Proceedings. 5th International Conference on

Date 21-24 Oct. 2003

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  • Symmetrical spiral inductor design and optimization for VCO design in 0.35μm CMOS technology

    Publication Year: 2003, Page(s):1066 - 1069 Vol.2
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (354 KB)

    Optimizing the quality factor for VCO (voltage control oscillator) application has the added advantages of reducing power consumption and improving the phase noise performance. This work conducts a comprehensive study on a family of symmetrical spiral inductors in standard digital 0.35μm CMOS process. In addition to quality factor, inductor characteristics of interest include inductor value, pe... View full abstract»

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  • A computational method in predicting distributed oscillator phase noise

    Publication Year: 2003, Page(s):1025 - 1028 Vol.2
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (289 KB)

    Distributed oscillator as a new type of oscillator for the integrated circuit design has emerged. In this paper, a frequency-domain analytical method is employed for the purpose of predicting phase noise in distributed oscillators. The method is founded upon a linear model, and then nonlinear effects are taken into consideration. The computational formulae are obtained for predicting distributed o... View full abstract»

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  • An asynchronous add-compare-select design in CMOS VLSI

    Publication Year: 2003, Page(s):1277 - 1280 Vol.2
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (266 KB)

    A novel asynchronous ACS (Add-Compare-Select) is described. The circuit of a novel asynchronous comparator unit is proposed. The performance of ACS is analyzed with the novel method based on multi-delay model. The results of performance analysis of asynchronous ACS show that the average case response time 3.66ns is only 45% the worst-case response time 8.1ns. It reveals that the asynchronous ACS h... View full abstract»

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  • A 1V, 2.4GHz fully integrated LNA using 0.18μm CMOS technology

    Publication Year: 2003, Page(s):1062 - 1065 Vol.2
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (318 KB)

    A 1V, 2.4GHz fully integrated CMOS low noise amplifier (LNA) including the 50 Ω referenced input output matching networks is implemented using 0.18μm technology within a chip area of 4.1mm2. The amplifier has the noise figure (NF) of 3.8dB and forward gain of more than 20dB. The details of the LNA analysis and design procedure are presented in this paper. View full abstract»

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  • A low-voltage, low-power direct-conversion CMOS receiver for 5GHz wireless LAN

    Publication Year: 2003, Page(s):1021 - 1024 Vol.2
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (294 KB)

    This paper presents a fully integrated low-power direct-conversion receiver for 5GHz wireless application. The IC was fabricated in a 0.18-μm CMOS technology. It combines LNA, mixer, integer-N frequency synthesizer, AGC loop, and low-pass channel-select filter. A newly proposed operational amplifier that can boost 35dB in voltage gain without consuming extra power is used in the channel-select ... View full abstract»

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  • Design of application specific chip for EPON

    Publication Year: 2003, Page(s):865 - 869 Vol.2
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (310 KB)

    Ethernet passive optical networks (EPONs), which converges low-cost Ethernet equipment and low-cost fiber infrastructure, appear to be the best candidate for the next-generation access network. One of the key technologies of EPON is the realization of transmission convergence, including the synchronization of burst, ranging, allocation of bandwidth, frame synchronization, control of BER (Bit Error... View full abstract»

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  • Research on computing IP core for the digital signature algorithm

    Publication Year: 2003, Page(s):1329 - 1331 Vol.2
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (221 KB)

    Polynomial multiplication with big integer coefficients over finite field is frequently used in some digital signature algorithms, in which this kind of calculation is the most time consuming part realized by software. This paper presents a new method (FFT/IFFT) and tries to solve it using FPGA. With the reduced calculation amount compared with normal algorithm and realized in hardware, it will gr... View full abstract»

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  • An area efficient modular arithmetic processor

    Publication Year: 2003, Page(s):1273 - 1276 Vol.2
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (287 KB)

    RSA public-key cryptography and some other algorithms require various modular arithmetic operations. This paper presents an area efficient modular arithmetic processor. The operands can vary in size from 256 to 2048 bits. Optimized CIOS algorithm is introduced to speed up modular multiplication. At a maximum clock rate of 60 MHz, it takes 57 ms to complete a 1024-bit modular exponentiation. The co... View full abstract»

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  • A 2.4GHz CMOS LNA with full ESD protection

    Publication Year: 2003, Page(s):1058 - 1061 Vol.2
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (377 KB)

    This paper proposed a CMOS LNA with full ESD protection, which means that all pads of this circuit can sustain a HBM stress up to 2kV under various zapping modes. Using all standard devices provided by the foundry with their parasitic included, the verification of the ESD performance in the circuit design process can be executed very easily and the results are reliable. Besides of the remarkable E... View full abstract»

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  • A 1.4-GHz LC-VCO in 0.35μm digital CMOS technology

    Publication Year: 2003, Page(s):1018 - 1020 Vol.2
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (237 KB)

    A 1.4GHz LC-tank voltage oscillator (VCO) is implemented with TSMC 0.35μm 1P4M digital CMOS technology. The VCO has a tuning range of 150MHz and a power consumption of 20mW. Spiral inductor and varactors are also on-chip and no off-chip components are needed. View full abstract»

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  • Key aspects on ESD protection design for ICs: mixed-mode simulation and RF/mixed-signal ESD

    Publication Year: 2003, Page(s):1000 - 1005 Vol.2
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (485 KB)

    This paper reviews the key aspects in on-chip ESD (electrostatic discharge) protection circuitry design. The mixed-mode ESD simulation-design methodology is discussed to address the design prediction task. New challenges in ESD protection design for RF/mixed-signal ICs are discussed that include the complex ESD-circuit interactions. RF ESD protection characterization and full-chip ESD protection s... View full abstract»

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  • Multi-loops phase locked system

    Publication Year: 2003, Page(s):736 - 739 Vol.2
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (273 KB)

    This paper describes the design of a system used to derive high-speed time signals for SONET/SDH based equipment. This system was combined of three phase-locked loops. After optimized separately, the parameters of the loops were combined together. These three phase-locked loops share the same filter and voltage-controlled oscillator, so the size of the chip is reduced. View full abstract»

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  • A novel transmitter for 10/100MHz Base-TX Ethernet

    Publication Year: 2003, Page(s):861 - 864 Vol.2
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (258 KB)

    A novel architecture of transmitter for 10/100MHz Base TX Ethernet is proposed in the paper. Two modes of 10MHz Base TX and 100MHz Base TX is compatible in the circuit. The circuit uses techniques of waveform shaping, slew rate control, and reused line driver etc. to perform transmit and all parameters meet the specs in the IEEE 802.3 standard. The chip is implemented in the 0.18μm technology o... View full abstract»

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  • A FPGA-based voltage regulation control unit for optical phased array beam deflector

    Publication Year: 2003, Page(s):1377 - 1380 Vol.2
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (266 KB)

    The hardware design and FPGA implementation of a voltage regulation control unit for optical phased array beam deflector is described. With the control unit used for a 16-channel waveguide phased array beam deflector, a beam scan rate above 500 kHz can be achieved, which is far higher than that obtained with other implementation methods based on microcontrollers. View full abstract»

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  • A novel image rotating algorithm tailored for embedded AFIS

    Publication Year: 2003, Page(s):1325 - 1328 Vol.2
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (270 KB)

    In recent years, the importance of information security in wide spread embedded applications increases a lot, promoting the study on fingerprint recognition, which is an effective biometric technique used in personal identification. In this paper, we study the effect of fingerprint image rotation on the correct recognition rate of automatic fingerprint identification system (AFIS), proving it a ne... View full abstract»

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  • A design of regularized multiplier generator

    Publication Year: 2003, Page(s):1269 - 1272 Vol.2
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (302 KB)

    Multiplier is an essential part in processors. Designing it in good performance always costs a long time. A regularized multiplier generator is proposed, which can produce the source codes in VHDL automatically. It can meet the need to shorten the design time. The generator chooses the 4-2 trees, which achieve the same speed performance as equivalent Wallace trees in many cases, but require a simp... View full abstract»

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  • A new modeling and parameter extraction technique for uni-directional high-voltage MOS devices

    Publication Year: 2003, Page(s):984 - 987 Vol.2
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (263 KB)

    In this paper, a new method of modeling uni-directional HV MOS device based on the common BSIM3V3 model is presented. We propose to assign physical meanings and values of three model parameters different from the original BSIM3V model based on BSIM3V3 user manual (1995) but not change any equation of it to model the characteristics of uni-directional HV MOS devices. The way of accurate parameters ... View full abstract»

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  • An efficient bit loading algorithm for OFDM-based wireless LAN systems and hardware implementation results

    Publication Year: 2003, Page(s):1054 - 1057 Vol.2
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (268 KB)

    In this paper, we propose an efficient bit loading algorithm for IEEE 802.11A wireless LAN systems. A conventional bit loading algorithm uses the SNR value of each subcarrier. However, it is very difficult to estimate the exact SNR value in wireless LAN systems due to the randomness of AWGN. Therefore, the proposed algorithm uses the channel frequency response instead of the SNR value of each subc... View full abstract»

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  • Preamplifier for ultra-wide band system in 0.18μm CMOS process

    Publication Year: 2003, Page(s):1078 - 1081 Vol.2
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (278 KB)

    A preamplifier is presented for single band ultra-wide band systems. A feed-back configuration is employed with a bandpass filter. The process is in CSM 0.18μm standard CMOS process. The preamplifier is with bandwidth of 6GHz (3GHz∼9GHz), noise figure of less than 8.5dB. The bandwidth and noise figure are comparable to the results from other designs done in 0.13μm CMOS process. The desig... View full abstract»

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  • Theory of cross-coupled RF oscillator for multi- and quadrature-phase signal generation

    Publication Year: 2003, Page(s):1014 - 1017 Vol.2
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB)

    We proved in this paper that, a system composed of identical sub-systems that are cross-coupled in certain manner is capable of generating multi- or quadrature-phase oscillation signals under specified conditions. Based on the theory, an RC multi-phase oscillator is proposed as an example, for which the condition for maintaining stable oscillation is also deduced. Moreover, a detailed numerical re... View full abstract»

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  • A weighted average formula for efficient inductance and resistance extraction

    Publication Year: 2003, Page(s):996 - 999 Vol.2
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (279 KB)

    In this paper a weighted formula method is used to compute the 3-D frequency-dependent inductance and resistance. Every conductor is partitioned into a set of filaments, and the inductance between conductors can be computed through computing the weighted average inductance between filaments. Theory analysis and numerical results show that this method can greatly decrease computing time compared wi... View full abstract»

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  • The programmable logic implementation of GPS/GLONASS clock synchronization

    Publication Year: 2003, Page(s):732 - 735 Vol.2
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (268 KB)

    A GPS/GLONASS clock synchronization implementation based on programmable logic is presented. The GPS/GLONASS PPS (standard 1 second signal) is regarded as a reference of the whole clock synchronization system that consists of two levels PLL. Both the GPS/GLONASS PPS and OCXO assure the long-term stability and short-term stability of clock signals. All the digital circuit, including digital phase e... View full abstract»

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  • Design and implementation of motion compensation for MPEG-4 AS profile streaming video decoding

    Publication Year: 2003, Page(s):942 - 945 Vol.2
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB)

    This paper presents an efficient motion compensation architecture for MPEG-4 advanced simple profile at level 5 (ASP@L5) streaming video standard. A novel local memory storage scheme for motion vector prediction is proposed in the paper. In this scheme, local memory for storing differential data of motion information in video packet layer is avoided, and total memory access bandwidth is reduced 1/... View full abstract»

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  • MAC implementation with embedded system

    Publication Year: 2003, Page(s):757 - 760 Vol.2
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (290 KB)

    This paper presents the design flow of a SoC (System on a Chip). An IEEE802.11b Medium Access Controller (MAC) is implemented with a 32bit RISC controller and verified with FPGA chip. The architecture of the system includes hardware and software. The software part includes real time operation system (RTOS), which is realized in μC/OS-II and MAC application program. The MAC application is descri... View full abstract»

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  • On designing of an EOS chip with SDP

    Publication Year: 2003, Page(s):856 - 860 Vol.2
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (388 KB)

    As is known, Ethernet has gained great popularity in LAN (local area network). Meanwhile, SDH/SONET is the backbone of today's communication networks. Then, how to exchange information between Ethernets located in different regions over SDH/SONET is becoming a hotspot. This paper provides a single chip solution of Ethernet transmission over SDH/SONET (EOS), which supports up to thirty-two 10/100Mb... View full abstract»

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