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Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings

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Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings

Date 16-20 Feb. 2004

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Title History

IP testing - the future differentiator?

Synthesis of embedded systemC design: a case study of digital neural networks

An inductance modeling flow seamlessly integrated in the RF IC design chain

Building the hierarchy from a flat netlist for a fast and accurate post-layout simulation with parasitic components

System level power modeling and simulation of high-end industrial network-on-chip

Design and implementation of a secret key steganographic micro-architecture employing FPGA

Evaluation of an object-oriented hardware design methodology for automotive applications

Modeling and analysis of heterogeneous industrial networks architectures

IEM926: an energy efficient SoC with dynamic voltage scaling

Application of a multi-processor SoC platform to high-speed packet forwarding

Expert system perimeter block placement floorplanning

NeuroFPGA-implementing artificial neural networks on programmable logic devices

RASoC: a router soft-core for networks-on-chip

Systems on chips design: system manufacturer point of view

Energy estimation based on hierarchical bus models for power-aware smart cards

A high-speed transceiver architecture implementable as synthesizable IP core

Formal refinement and model checking of an echo cancellation unit

A power optimized display memory organization for handheld user terminals

Customisable EPIC processor: architecture and tools

Analysis and modeling of energy reducing source code transformations

RUNE: platform for automated design of integrated multi-domain systems application to high-speed CMOS photoreceiver front-ends

The design and test of a smartcard chip using a CHAIN self-timed network-on-chip

A generic RTOS model for real-time systems simulation with systemC

Package design for high performance ICs

Design of very deep pipelined multipliers for FPGAs

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