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Circuits and Systems II: Express Briefs, IEEE Transactions on

Issue 6 • Date June 2013

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Displaying Results 1 - 21 of 21
  • Table of contents

    Publication Year: 2013 , Page(s): C1
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  • IEEE Transactions on Circuits and Systems-II: Express Briefs publication information

    Publication Year: 2013 , Page(s): C2
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  • 12.5-Gb/s Full-Rate CDR With Wideband Quadrature Phase Shifting in Data Path

    Publication Year: 2013 , Page(s): 297 - 301
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (961 KB) |  | HTML iconHTML  

    A 12.5-Gb/s full-rate clock and data recovery (CDR) circuit that utilizes an open-loop quadrature clock generator for wideband 90° phase shifting in the data path is presented. The differential clock from a voltage-controlled oscillator (VCO) is split into quadrature phases and subsequently mixed with data to provide in-phase and quadrature components of the data over a broad range of frequencies in the vicinity of the nominal data rate. The quadrature data phases are employed for the detection of clock phase misalignment in a mixer-based phase detector. A proof-of-concept prototype chip that integrates the critical building blocks of the proposed CDR is fabricated in a 90-nm CMOS technology. The CDR achieves a bit error rate of <; 10-12 in response to 231 - 1 pseudorandom-binary-sequence data, while the chip (which excludes VCO) consumes 84 mW from a 1.2-V supply. View full abstract»

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  • A 6.5-Gb/s 1-mW/Gb/s/CH Simple Capacitive Crosstalk Compensator in a 130-nm Process

    Publication Year: 2013 , Page(s): 302 - 306
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1241 KB) |  | HTML iconHTML  

    A capacitive crosstalk compensator (CXC) at a transmitter is presented. It employs double-path capacitive coupling to cancel accurately crosstalk-induced jitter. A mode detector and an additional clock for compensation are eliminated, and only buffers and capacitors are used. The simple architecture consumes low power (1 mW/Gb/s/CH) and occupies small area (0.009 mm2/CH). The chip was fabricated in a 130-nm CMOS process. CXC has the maximum jitter reduction of 34.1 ps (90.5%) and the maximum voltage improvement of 26.6 mV. CXC operates at up to 6.5 Gb/s. View full abstract»

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  • A Low In-Band Radiation Superregenerative Oscillator

    Publication Year: 2013 , Page(s): 307 - 310
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (625 KB) |  | HTML iconHTML  

    This brief describes a superregenerative (SR) voltage-controlled oscillator as a building block for SR receivers where most of the oscillator spectrum components are outside the reception frequency band. This allows overcoming one of the main drawbacks of SR receivers, i.e., the potential interference to nearby receivers operating at the same frequency due to oscillator reradiation. We perform a qualitative analysis of the solution of the circuit equations, describe the most relevant parameters for design, and provide some numerical simulation results. Experimental results on a proof-of-concept implementation validating the described principle and a discussion of the observed behavior are provided. View full abstract»

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  • A 990- \mu\hbox {W} 1.6-GHz PLL Based on a Novel Supply-Regulated Active-Loop-Filter VCO

    Publication Year: 2013 , Page(s): 311 - 315
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1429 KB) |  | HTML iconHTML  

    A low-power 1.6-GHz phase-locked loop (PLL) based on a novel supply-regulated voltage-controlled oscillator (SR-VCO) including an active-loop filter (ALF) is realized. In this PLL, an active RC filter is combined with SR-VCO, achieving the advantages of ALF PLL without penalties in power consumption or phase noises. The PLL has measured rms jitter of 4.82 ps, and its core consumes 990 μW from 1-V supply while the chip area is 420 × 570 μm2 including on-chip passive components required for the ALF and the supply regulator. View full abstract»

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  • A CMOS High-Voltage Transmitter IC for Ultrasound Medical Imaging Applications

    Publication Year: 2013 , Page(s): 316 - 320
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1242 KB) |  | HTML iconHTML  

    A high-voltage (HV) transmitter integrated circuit for ultrasound medical imaging applications is implemented using 0.18-μm bipolar/CMOS/DMOS technology. The proposed HV transmitter achieves high integration by only employing standard CMOS transistors in a stacked configuration with dynamic gate biasing circuit while successfully driving the capacitive micromachined ultrasound transducer device immersed in an oil environment without breakdown reliability issues. The HV transmitter including the output driver and the voltage level shifters generates over 10-Vp-p pulses at 1.25-MHz frequency and occupies only 0.022 mm2 of core die area. View full abstract»

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  • High-Accuracy Current Memory in HV CMOS Technology

    Publication Year: 2013 , Page(s): 321 - 325
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (436 KB) |  | HTML iconHTML  

    This brief describes an improved current memory circuit aimed at circumventing problems inherent in using a high-voltage double-diffused MOS (DMOS) with CMOS technology. In addition to dealing with the excessive output conductance of a simple cell with cascoding in the familiar way, the circuit addresses the significant drain-gate feedthrough seen in such technologies. A replica bias scheme ensures that the gm of the memory device remains substantially constant notwithstanding the signal current level variations, leading to improved control over charge injection errors. The topology may also be used in conventional small geometry CMOS technology. View full abstract»

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  • A Capacitorless LDO Regulator With Fast Feedback Technique and Low-Quiescent Current Error Amplifier

    Publication Year: 2013 , Page(s): 326 - 330
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1160 KB) |  | HTML iconHTML  

    This brief presents an ultralow quiescent class-AB error amplifier (ERR AMP) of low dropout (LDO) and a slew-rate (SR) enhancement circuit to minimize compensation capacitance and speed up transient response designed in the 0.11-μm 1-poly 6-metal CMOS process. In order to increase the current capability with a low standby quiescent current under large-signal operation, the proposed scheme has a class-AB-operation operational transconductance amplifier (OTA) that acts as an ERR AMP. As a result, the new OTA achieved a higher dc gain and faster settling time than conventional OTAs, demonstrating a dc gain improvement of 15.8 dB and a settling time six times faster than that of a conventional OTA. The proposed additional SR enhancement circuit improved the response based on voltage-spike detection when the voltage dramatically changed at the output node. View full abstract»

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  • A 1-mW Solar-Energy-Harvesting Circuit Using an Adaptive MPPT With a SAR and a Counter

    Publication Year: 2013 , Page(s): 331 - 335
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1288 KB) |  | HTML iconHTML  

    This brief presents an energy-harvesting system that uses an adaptive maximum power point tracking (MPPT) circuit for 1-mW solar-powered wireless sensor networks. The proposed MPPT circuit exploits a successive approximation register and a counter to solve the tradeoff problem between a fast transient response and a small steady-state oscillation with low-power consumption. The proposed energy-harvesting circuit is fabricated using a 0.35-μm CMOS process. The MPPT circuit reduces the transient response time by 76.6%, dissipates only 110 μW , and shows MPPT efficiency of 99.6%. View full abstract»

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  • An RF–DC Converter with Wide-Dynamic-Range Input Matching for Power Recovery Applications

    Publication Year: 2013 , Page(s): 336 - 340
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (516 KB) |  | HTML iconHTML  

    An improved RF-dc converter based on a class-E rectifier with wide-dynamic-range input matching is presented. The input impedance is controlled by two varactor diodes to compensate for impedance changes with RF input power and dc loading conditions. The RF-dc converter achieved a peak efficiency of 60% and an S11 less than - 20 dB over an input RF power range of 12 dB and an operating battery voltage of 2.5-4.2 V at 800 MHz. An analytical model for input impedance and efficiency was developed and shown to match simulation and measurement results. View full abstract»

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  • Boosted CMOS APS Pixel Readout for Ultra Low-Voltage and Low-Power Operation

    Publication Year: 2013 , Page(s): 341 - 345
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (915 KB) |  | HTML iconHTML  

    A new pixel readout technique is proposed for three-transistor (3T) CMOS active pixel sensor (APS) pixels. It utilizes the supply-boosting technique (SBT) in order to reduce power consumption and allow ultra low-voltage operation. The pixel supply voltage as well as the pixel reset and select signals were boosted to achieve wider and extended linear operating ranges. A CMOS image sensor containing a 54 × 50 array of 3T CMOS APS pixels was fabricated in a standard 2P3M 5-V 0.5- μm CMOS process to confirm the effectiveness of each boosting operation. Theory, simulation, and measurement results are presented. The boosting pixel supply voltage during pixel readout provides additional 31% dynamic range improvement on top of the seven times (7×) expansion attained by boosting the pixel reset signal. It was shown that the proposed boosted readout does not increase the number of transistors in the 3T CMOS APS pixels nor degrade the image quality. View full abstract»

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  • Low-Power, High-Throughput, and Low-Area Adaptive FIR Filter Based on Distributed Arithmetic

    Publication Year: 2013 , Page(s): 346 - 350
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (739 KB) |  | HTML iconHTML  

    This brief presents a novel pipelined architecture for low-power, high-throughput, and low-area implementation of adaptive filter based on distributed arithmetic (DA). The throughput rate of the proposed design is significantly increased by parallel lookup table (LUT) update and concurrent implementation of filtering and weight-update operations. The conventional adder-based shift accumulation for DA-based inner-product computation is replaced by conditional signed carry-save accumulation in order to reduce the sampling period and area complexity. Reduction of power consumption is achieved in the proposed design by using a fast bit clock for carry-save accumulation but a much slower clock for all other operations. It involves the same number of multiplexors, smaller LUT, and nearly half the number of adders compared to the existing DA-based design. From synthesis results, it is found that the proposed design consumes 13% less power and 29% less area-delay product (ADP) over our previous DA-based adaptive filter in average for filter lengths N = 16 and 32. Compared to the best of other existing designs, our proposed architecture provides 9.5 times less power and 4.6 times less ADP. View full abstract»

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  • SRAM Array Structures for Energy Efficiency Enhancement

    Publication Year: 2013 , Page(s): 351 - 355
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (485 KB) |  | HTML iconHTML  

    Energy efficiency is a supreme design concern in many ultralow-power applications. In such applications, static random-access memory (SRAM) plays a significant role in energy consumption due to the high density for evermore increased computing power. This brief explores and analyzes SRAM array structures for energy efficiency improvement. In contrast to the traditional practices where SRAM arrays enclose more rows than columns, this work reveals that better SRAM energy efficiencies can be achieved with a wider SRAM array structure with fewer rows than columns particularly at low supply voltage. The analysis shows that the array structure optimization can improve the energy efficiency up to 38% (64 kbit) and 10% (8 kbit) for the same SRAM bit density and the same supply voltage. View full abstract»

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  • Fine-Grain Dynamic Energy Tracking for System on Chip

    Publication Year: 2013 , Page(s): 356 - 360
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (839 KB) |  | HTML iconHTML  

    In this brief, we model system-on-chip consumption as a dynamic process that can be easily tracked over time through a set of power modes. The proposed method provides precise information on each block dissipation inside the system. Each generated mode defines a specific model that links power to block activity reported by a set of critical signals. The modeling approach is illustrated by real experiments. When applied to memory blocks, the model showed 10% maximum error, considering power at very fine granularity (quasi-instantaneous power). For long simulations, average and maximum energy are estimated with errors of 5.3% and 4.8%, respectively. For a memory controller and a multiply accumulate unit, only one probe is used leading to a very limited area overhead. View full abstract»

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  • l_{2} - l_{\infty } Elimination of Overflow Oscillations in 2-D Digital Filters Described by Roesser Model With External Interference

    Publication Year: 2013 , Page(s): 361 - 365
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (117 KB) |  | HTML iconHTML  

    Two-dimensional (2-D) digital filters can be corrupted by external interferences, but no stability criteria have yet been established. This brief proposes a new l2 - l stability criterion for the absence of limit cycles in 2-D digital filters that are described by Roesser model with external interference. Our new criterion ensures the attenuation of the effect of external interference on 2-D digital filters to a prescribed level. This criterion also guarantees the asymptotic stability result without external interference. The proposed criterion is represented in terms of linear matrix inequality, which can be verified by using existing numerical packages. We use an illustrative example to demonstrate the effectiveness of the proposed criterion. View full abstract»

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  • A New Spectrum Sensing Method Using Output Analysis of the PFD

    Publication Year: 2013 , Page(s): 366 - 370
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (495 KB) |  | HTML iconHTML  

    In this brief, a new blind spectrum sensing method is proposed based on frequency comparison using a phase frequency detector (PFD). The PFD output patterns are utilized in a way to sense the spectrum with no knowledge of incoming signals, noise, or channel parameters. The detection and false alarm error probabilities are analytically calculated for additive white Gaussian noise and sine-wave input and are simulated for different inputs. It is shown that the required detection and false alarm probabilities can be achieved by changing the system parameters. The results show that the proposed method has lower complexity and outperforms the previous single-antenna blind method over flat fading channel. View full abstract»

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  • Guaranteed H Performance State Estimation of Delayed Static Neural Networks

    Publication Year: 2013 , Page(s): 371 - 375
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (154 KB) |  | HTML iconHTML  

    This brief studies the guaranteed H performance state estimation problem of delayed static neural networks. The single- and double-integral terms in the time derivative of the Lyapunov functional are handled by the reciprocally convex combination and a new integral inequality, respectively. A delay-dependent design criterion is established such that the error system is globally exponentially stable with a decay rate and a prescribed H performance is guaranteed. The gain matrix and the optimal performance index are obtained via solving a convex optimization problem subject to linear matrix inequalities. A numerical example is exploited to demonstrate that much better performance can be achieved by this approach. View full abstract»

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  • IEEE Xplore Digital Library

    Publication Year: 2013 , Page(s): 376
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    Freely Available from IEEE
  • IEEE Circuits and Systems Society Information

    Publication Year: 2013 , Page(s): C3
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  • IEEE Transactions on Circuits and Systems - II: Express Briefs information for authors

    Publication Year: 2013 , Page(s): C4
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Aims & Scope

TCAS II publishes brief papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes:

  • Circuits: Analog, Digital and Mixed Signal Circuits and Systems  
  • Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic
  • Circuits and Systems, Power Electronics and Systems
  • Software for Analog-and-Logic Circuits and Systems
  • Control aspects of Circuits and Systems. 

Full Aims & Scope