# IEEE Transactions on Circuits and Systems I: Regular Papers

## Issue 99

Early Access articles are new content made available in advance of the final electronic or print versions and result from IEEE's Preprint or Rapid Post processes. Preprint articles are peer-reviewed but not fully edited. Rapid Post articles are peer-reviewed and edited but not paginated. Both these types of Early Access articles are fully citable from the moment they appear in IEEE Xplore.

## Filter Results

Displaying Results 1 - 25 of 141
• ### A Seven-Octave Broadband LNA MMIC Using Bandwidth Extension Techniques and Improved Active Load

Publication Year: 2018, Page(s):1 - 12
| |PDF (3268 KB)

This paper presents the analysis and design of a novel broadband low-noise amplifier (LNA) with larger than seven-octave bandwidth. To achieve good impedance matching, flat gain, and low noise over larger than seven-octave bandwidth, the combination technique of shunt-resistive feedback, dual inductive-peaking techniques as well as a compact improved active load supporting broadband RF biasing fro... View full abstract»

• ### FIR Filter Realization via Deferred End-Around Carry Modular Addition

Publication Year: 2018, Page(s):1 - 11
| |PDF (3941 KB)

Hardware realization of FIR filters that are based on residue number systems leads to increased speed and reduced power, where besides the popular Mersenne numbers, several moduli of the form 2n ± δ (δ ≥ 3) are commonly used. However, additional weighted 2i(i>1) end-around carries (EACs) slow down and complicate the required modular adders in comparison to modulo... View full abstract»

• ### A Mixed-Signal Technique for TX-Induced Modulated Spur Cancellation in LTE-CA Receivers

Publication Year: 2018, Page(s):1 - 14
| |PDF (4534 KB)

A mixed signal transmit (TX)-interference cancellation technique targeting Long Term Evolution (LTE) carrier aggregation (CA) receivers is proposed. The introduced architecture aims for the mitigation of TX modulated spur interference, a newly arisen issue in LTE-CA receivers. The resulting technique directly senses the TX leakage within the receiver and generates a reference signal to cancel the ... View full abstract»

• ### A 2.5-5.6 GHz Subharmonically Injection-Locked All-Digital PLL With Dual-Edge Complementary Switched Injection

Publication Year: 2018, Page(s):1 - 12
| |PDF (3941 KB)

A 2.5-5.6 GHz low-phase-noise subharmonically injection-locked sub-sampling all-digital phase-locked loop with a dual-edge complementary switched injection technique is presented. While previously reported injection-locked phase-locked loops (ILPLLs) require additional circuitry for resolving a phase alignment mismatch between the PLL loop and injection path, the presented ILPLL exhibits a simplif... View full abstract»

Publication Year: 2018, Page(s):1 - 11
| |PDF (2528 KB)

This paper presents a single-chip impulse-radio (IR) radar transceiver that utilizes a novel continuous sweep-clock generator. While requiring low power and small area, the proposed clock generator enables a versatile IR radar operation with millimeter resolution. The radar detection range and update rate are adjustable by an on-chip delay command circuit or by an external master. The IR radar tra... View full abstract»

• ### A 7-GHz CMOS Bidirectional Variable Gain Amplifier With Low Gain and Phase Imbalances

Publication Year: 2018, Page(s):1 - 10
| |PDF (3781 KB)

This paper presents a bidirectional variable gain amplifier (BVGA) with a low imbalance between amplification directions in 65-nm CMOS process. The BVGA is composed of two symmetric bidirectional amplifiers (BA) and a distributed attenuator (DA) for a low directional imbalance. The amplification direction is changed by the switching supply and ground voltages of a common gate amplifier in the BA. ... View full abstract»

• ### Wideband Techniques for Outphasing Power Amplifiers

Publication Year: 2018, Page(s):1 - 11
| |PDF (2064 KB)

In this paper a wideband, high-power amplifier that achieves an output power of 20 W with a bandwidth greater than one octave in the L and S bands is presented. Two ~ 10 W Class AB PAs are implemented with Gallium Nitride-high electron mobility transistor devices and a low loaded-Q matching network to achieve wideband performance. High power added efficiency (PAE) is achieved by combining outphase... View full abstract»

• ### A Wirelessly Powered CMOS Electrochemical Sensing Interface With Power-Aware RF-DC Power Management

Publication Year: 2018, Page(s):1 - 11
| |PDF (4427 KB)

A wirelessly powered electrochemical sensing chip with high-efficiency adaptive power management for a wide RF-powering range and a low-noise chopper-stabilization potentiostat for high-resolution electrochemical current detection is presented. The chip is fabricated using a 0.18-μm CMOS process. A novel, power-aware, multiple-path, RF-energy harvesting front end extends the high-efficiency... View full abstract»

• ### A Novel Transmitter Architecture for Spectrally-Precoded OFDM

Publication Year: 2018, Page(s):1 - 14
| |PDF (3433 KB)

Frequency nulling spectral precoding is an approach that suppresses the out-of-band emission in orthogonal frequency division (OFDM) systems. In this paper, we discuss the transmitter architecture of the spectrally precoded OFDM systems. We design a novel precoder that matches the practical implementation of the OFDM modulator. We show that spectral precoding can relax the analog low pass filterin... View full abstract»

• ### Hardware Implementation of an Event-Based Message Passing Graphical Model Network

Publication Year: 2018, Page(s):1 - 14
| |PDF (4176 KB)

This paper presents a hardware system that implements a factor graph, where messages are sent using an event-based belief propagation algorithm. The system, comprising an FPGA and an application specific integrated circuit (ASIC) chip, can be used to construct a graph with upto 16 output message channels. The ASIC chip with 16 channels is fabricated in a 0.35 um 2P4M CMOS process and occupies 2.16... View full abstract»

• ### Device and Compact Circuit-Level Modeling of Graphene Field-Effect Transistors for RF and Microwave Applications

Publication Year: 2018, Page(s):1 - 12
| |PDF (4365 KB)

Graphene field-effect transistors (GFETs) are promising candidates for future nano-electronic circuitry with excellent radio frequency (RF) and microwave performance due to the ultra-high carrier mobility, large saturation velocity, and good electrical conductivity of the graphene channel. In this paper, a compact circuit-level model of GFETs is proposed for RF and microwave high-frequency applica... View full abstract»

• ### A Monolithic High-Voltage Li-Ion Battery Charger With Sharp Mode Transition and Partial Current Control Technique

Publication Year: 2018, Page(s):1 - 11
| |PDF (4660 KB)

A high-voltage (HV) lithium-ion battery charger control chip with sharp mode transition and partial current control technique is proposed in this paper. The proposed sharp mode transition eliminates the transition region between constant current (CC) and constant voltage (CV) stages in traditional CC-CV chargers. This technique reduces the charging time and simplifies the compensator design. Furth... View full abstract»

• ### Near-Field MIMO Communication Links

Publication Year: 2018, Page(s):1 - 10
| |PDF (3196 KB)

A procedure to achieve near-field multiple input multiple output (MIMO) communication with equally strong channels is demonstrated in this paper. This has applications in near-field wireless communications, such as Chip-to-Chip (C2C) communication or wireless links between printed circuit boards. Designing the architecture of these wireless C2C networks is, however, based on standard engineering d... View full abstract»

• ### Low-Cost Lifting Architecture and Lossless Implementation of Daubechies-8 Wavelets

Publication Year: 2018, Page(s):1 - 9
| |PDF (2537 KB)

This paper presents three lifting structures of Daubechies-8 (also known as D8) wavelet transform using efficient factorization of the polyphase matrix. All new filter coefficients are optimally mapped with integers resulting in low cost hardware implementation. We first derive the polyphase matrices using a factorization algorithm, which forms the basis of multiple lifting structures of D8. A the... View full abstract»

• ### Model Reduction Using Parameterized Limited Frequency Interval Gramians for 1-D and 2-D Separable Denominator Discrete-Time Systems

Publication Year: 2018, Page(s):1 - 10
| |PDF (3543 KB)

In this paper, we propose model reduction algorithms based on the frequency-domain interval Gramians for 1-D and separable denominator 2-D discrete-time systems using balanced truncation as a parameterized combination of unweighted and the limited-frequency interval Gramians. The values of free parameters are computed using a line search optimization. The proposed algorithms provide a substantial ... View full abstract»

• ### Expansion and Compression of Analog Pulses by Bandwidth Scaling of Continuous-Time Filters

Publication Year: 2018, Page(s):1 - 12
| |PDF (2862 KB)

This paper demonstrates a completely on-chip implementation of expansion and compression of continuous-time, wideband, analog pulses. The input pulse is fed to a continuous-time filter whose delay exceeds the pulse duration. Once the pulse is completely inside the filter, it is stored in the form of the filter's state-variables, which can completely reconstruct the pulse. Instantaneously decreasin... View full abstract»

• ### A 16 x 16 CMOS Amperometric Microelectrode Array for Simultaneous Electrochemical Measurements

Publication Year: 2018, Page(s):1 - 11
| |PDF (2552 KB)

There is a requirement for an electrochemical sensor technology capable of making multivariate measurements in environmental, healthcare, and manufacturing applications. Here, we present a new device that is highly parallelized with an excellent bandwidth. For the first time, electrochemical cross-talk for a chip-based sensor is defined and characterized. The new CMOS electrochemical sensor chip i... View full abstract»

• ### Design and Evaluation of Approximate Logarithmic Multipliers for Low Power Error-Tolerant Applications

Publication Year: 2018, Page(s):1 - 13
| |PDF (6259 KB)

In this paper, the designs of both non-iterative and iterative approximate logarithmic multipliers (ALMs) are studied to further reduce power consumption and improve performance. Non-iterative ALMs, that use three inexact mantissa adders, are presented. The proposed iterative ALMs (IALMs) use a set-one adder in both mantissa adders during an iteration; they also use lower-part-or adders and approx... View full abstract»

• ### A 93% Peak Efficiency Fully-Integrated Multilevel Multistate Hybrid DC-DC Converter

Publication Year: 2018, Page(s):1 - 14
| |PDF (5284 KB)

The general structure of a multilevel multistate dc-dc converter is introduced, which is a hybrid between inductor-based (buck) converters and capacitor-based (switched capacitor) converters. The control of the new converter is hybrid between switched capacitor converters and buck converters, where the coarse tuning of the output voltage is achieved through the selection of an appropriate operatin... View full abstract»

• ### All-Digital Blind Background Calibration Technique for Any Channel Time-Interleaved ADC

Publication Year: 2018, Page(s):1 - 12
| |PDF (3278 KB)

This paper proposes a novel digital adaptive blind background calibration technique for the gain, timing skew, and offset mismatch errors in a time-interleaved analog-to-digital converter (TI-ADC). Based on the frequency-shifted basis functions generated only from the measured TI-ADC output, the three mismatch errors can be represented, extracted, and then subtracted from the TI-ADC output adaptiv... View full abstract»

• ### Low Complexity Implementation of Unified Systolic Multipliers for NIST Pentanomials and Trinomials Over GF(2m)

Publication Year: 2018, Page(s):1 - 11
| |PDF (2343 KB)

Systolic finite field multiplier over GF(2m) based on the National Institute of Standards and Technology (NIST) recommended pentanomials or trinomials can be used as a critical component in many cryptosystems. In this paper, for the first time, we propose a novel low-complexity unified (hybrid field size) systolic multiplier for NIST pentanomials and trinomials over GF(2m). We have proposed a comp... View full abstract»

• ### A 12 mV Input, 90.8% Peak Efficiency CRM Boost Converter With a Sub-Threshold Startup Voltage for TEG Energy Harvesting

Publication Year: 2018, Page(s):1 - 10
| |PDF (2687 KB)

This paper proposed a high efficiency boost converter targeting thermoelectric generator energy harvesting. The proposed converter adopts the critical conduction mode rather than the discontinuous mode to reduce the conduction loss, which can improve the peak efficiency at high input power. To reduce the minimum input voltage, an adaptive on-resistance switch, which can automatically change the hi... View full abstract»

• ### A Low-Latency and Area-Efficient Gram-Schmidt-Based QRD Architecture for MIMO Receiver

Publication Year: 2018, Page(s):1 - 11
| |PDF (3435 KB)

Despite a low algorithmic complexity, Gram-Schmidt (GS) method has not been widely employed in the dedicated hardware architecture of matrix decomposition due to its expensive square-root and division operations. This paper presents a low-latency and area-efficient QR decomposition (QRD) architecture based on the modified GS method. The low complexity architecture is enabled by efficiently substit... View full abstract»

• ### A 53 dB$Ω$ 7-GHz Inductorless Transimpedance Amplifier and a 1-THz+ GBP Limiting Amplifier in 0.13-μm CMOS

Publication Year: 2018, Page(s):1 - 13
| |PDF (7996 KB)

An inductorless 10-Gb/s optical receiver including a novel transimpedance amplifier (TIA) with dual feedback loop and a limiting amplifier with third-order nested feedback is presented. The current-buffer-based TIA employs an active Cherry-Hooper stage in the auxiliary amplifier and reuses the tail current source to achieve 10 Gb/s operation in the presence of a 1 pF photodiode input capacitance. ... View full abstract»

• ### Faster Residue Multiplication Modulo 521-bit Mersenne Prime and an Application to ECC

Publication Year: 2018, Page(s):1 - 14
| |PDF (870 KB)

We present faster algorithms for the residue multiplication modulo 521-bit Mersenne prime on 32- and 64-bit platforms by using Toeplitz matrix-vector product. The total arithmetic cost of our proposed algorithms is less than that of existing algorithms, with algorithms for 64- and 32-bit residue multiplication giving the best timing results on our test machine. The transition from 64- to 32-bit im... View full abstract»

## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK