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Test Symposium, 2003. ATS 2003. 12th Asian

Date 16-19 Nov. 2003

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Displaying Results 1 - 25 of 102
  • A DFT approach for path delay faults in interconnected circuits

    Page(s): 72 - 75
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (212 KB) |  | HTML iconHTML  

    We propose a new DFT approach for path delay faults in interconnected circuits. The proposed approach places multiplexers on the interface between two circuits in order to create new testable paths through the interconnection. The new testable paths allow us to increase the number of paths tested in each circuit. This approach does not require interconnected circuits to be isolated by test wrappers. View full abstract»

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  • Error detection and correction in VLSI systems by online testing and retrying

    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (176 KB)  

    The conventional dual-module redundant (DMR) structure with comparison is a kind of self-testing structure used in some commercial general-purpose computers, such as IBM 4341 processor and IBM S/390 G3 and G4. One of its drawbacks is it does not have error recovery ability. Retrying finds applications because of its low hardware overhead. Micro-rollback and instruction retry as in VAX 8600 are effective methods for rapid error recovery that the error detection latency is only a few clock cycles. View full abstract»

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  • Non-linear cellular automata based PRPG design (without prohibited pattern set) in linear time complexity

    Page(s): 78 - 83
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (655 KB)  

    This paper reports an efficient BIST solution for VLSI circuits. The solution is based on an onchip Pseudo-Random Pattern Generator (PRPG). The test solution guarantees non-issuence of the test patterns declared prohibited to a CUT (Circuit Under Test). It has been developed around non-linear Cellular Automata (CA) and provides a linear time solution of designing an n-bit PRPG. Experimental results confirm the enhanced pseudo-random quality of the test patterns due to application of non-linear CA rules. View full abstract»

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  • Testability improvement during high-level synthesis

    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (197 KB) |  | HTML iconHTML  

    Improving testability during the early stages of High-Level Synthesis (HLS) reduces test hardware overheads, test costs, design iterations, and also improves fault coverage. In this paper, we present a novel register allocation algorithm which is based on weighted graph coloring, targeting testability improvement. View full abstract»

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  • A DFT selection method for reducing test application time of system-on-chips

    Page(s): 412 - 417
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (272 KB) |  | HTML iconHTML  

    This paper proposes an SoC test architecture generation framework. It contains a database which stores the test cost information on several DFTs for every core, and DFT selection part which performs DFT selection for test cost minimization using this database in the early phase of the design flow. Moreover, the DFT selection problem is formulated and the algorithm which solves it is proposed Experimental results showed that bottlenecks in test application time when using the single DFT method for all cores in a SoC are reduced by performing DFT selection from several DFTs. As a result, the whole test application time is drastically shortened. View full abstract»

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  • Delay testing of MOS transistor with gate oxide short

    Page(s): 168 - 173
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (297 KB) |  | HTML iconHTML  

    Gate Oxide Short defects are becoming predominant as technology is scaling down. Boolean and IDDQ testing of this defect has been widely studied but there is no paper dedicated to delay testing of this defect. So, this paper studies the delay behavior of Gate Oxide Short faults due to pinhole in the gate oxide. The objective of this paper is to give a detailed analysis of the behavior of the GOS defect taking into account the random parameter of the defect such as the GOS resistance and the GOS location. Because art accurate analysis is desired, the bi-dimensional array will be used. Because a complete analysis is desired, we derive characteristic of the GOS as a function of the GOS resistance and location. View full abstract»

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  • An expression's single fault model and the testing methods

    Page(s): 110 - 113
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (212 KB) |  | HTML iconHTML  

    This paper proposes a single fault model for the faults of the expressions, including operator faults (operator reference fault: an operator is replaced by another, extra or missing operator for single operand), incorrect variable or constant, incorrect parentheses. These types of faults often exist in the software, but some fault classes are hard to detect using traditional testing methods. A general testing method is proposed to detect these types of faults. Furthermore the fault simulation method of the faults is presented which can accelerate the generation of test cases and minimize the testing cost greatly. Our empirical results indicate that our methods require a smaller number of test cases than random testing, while retaining fault-detection capabilities that are as good as, or better than the traditional testing methods. View full abstract»

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  • A method to calculate the reliability of component-based software

    Page(s): 488 - 491
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (206 KB) |  | HTML iconHTML  

    This paper presents a method to calculate the reliability of component-based software. The method uses the data sheet of COTS (commercial off-the shelf components), partitioning every component input into sub-domains. Then it creates a Markov chain and calculates the whole system reliability based on the relation of components. This method is plausible in calculating the reliability of component-based software. View full abstract»

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  • Efficient diagnosis for multiple intermittent scan chain hold-time faults

    Page(s): 44 - 49
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (245 KB) |  | HTML iconHTML  

    When VLSI design and process enter the stage of ultra deep submicron (UDSM), process variations, signal integrity (SI) and design integrity (DI) issues can no longer be ignored. These factors introduce some new problems in VLSI design, test and diagnosis, which increase lime-to-market, time-to-volume and cost for silicon debug. Intermittent scan chain hold-time fault is one of such problems we encountered in practice. The fault sites have to be located to speedup silicon debug and improve yield. Recent study of the problem proposed a statistical algorithm to diagnose the faulty scan chains if only one fault per chain. Based on the previous work, in this paper, an efficient diagnosis algorithm is proposed to diagnose faulty scan chains with multiple faults per chain. The presented experimental results on industrial designs show that the proposed algorithm achieves good diagnosis resolution in reasonable time. View full abstract»

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  • Sharing BIST with multiple cores for system-on-a-chip

    Page(s): 418 - 423
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (241 KB) |  | HTML iconHTML  

    A novel architecture based on mixed mode BIST for sharing among multiple logic cores on an system-on-a-chip is presented. In the architecture a single-polynomial LFSR with maximum degree in the multiple cores can be selected to generate pseudo-random patterns to cover the easy to detect faults for the all cores. For the remaining faults of the each core deterministic test patterns can be compressed by a two-dimensional compression scheme, where the LFSR encodes the seeds of a folding counter as the seeds of the LFSR so as to reduce amount of test data storage, and all of the cores under test can use the unique LFSR to decompress the encoded seeds. Experimental results indicate that the proposed scheme can achieve a significant amount of compression for test data storage, and the simple and flexible architecture can be directly embedded on chip for systems-on-a-chip test. View full abstract»

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  • An object-oriented program automatic execute model and the research of algorithm

    Page(s): 492 - 495
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (218 KB)  

    This paper describes an automatic execution model, which can be used in the automatic test of OO programs. By integrating the object transition diagram, state transition diagram, state transition driver and script chooser, this model can choose and execute script automatically, and whenever it meets any exceptional fault, the result inspector indicates the position of it. By comparing and analyzing several script chooser algorithms, an appropriate one to match this model is designed. View full abstract»

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  • SOC test time minimization under multiple constraints

    Page(s): 312 - 317
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (238 KB) |  | HTML iconHTML  

    In this paper, we propose an SOC (system-on-chip) test scheduling technique that minimizes the test application time while considering test power limitations and test conflicts. The test power consumption is important to consider since exceeding the system's power limit might damage the system. Our technique takes also into account test conflicts that are due to cross-core testing (testing of interconnections), unit testing with multiple test sets, hierarchical SOCs where cores are embedded in cores, and the sharing of test access mechanism (TAM). Our technique handles these conflicts as well as precedence constraints, which is the order in which the tests has to be applied. We have implemented our algorithm and performed experiments, which shows the efficiency of our approach. View full abstract»

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  • Build-in-self-test for software

    Page(s): 220 - 223
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (278 KB)  

    Software testing has been a hard nut in the testing area for its complex and time-consuming nature. Taking advantage of mature technologies in hardware testing, we proposed a new approach to developing a new dimension of software testing called build-in-self-test (BIST) for software, which has long been applied in hardware testing as well as design for testability. This idea of testing methods from hardware is just to alleviate the burden of testing for software by transferring some testing work onto the programmer during programming so that the programmer and the tester can work together. Some new ideas are presented for further work. View full abstract»

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  • A novel method for online in-place detection and location of multiple interconnect faults in SRAM based FPGAs

    Page(s): 262 - 265
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (215 KB) |  | HTML iconHTML  

    This paper describes a novel method for online in-place detection and location of interconnects faults in SRAM-based FPGA systems. In safety critical systems like space probes, online checkers report misbehavior of sub-circuits within the system. When one such sub-circuit is reported to misbehave, the algorithm proposed in this paper performs run time reconfiguration (RTR) of LUTs in an attempt to detect and locate the interconnect faults, if any, within the faulty sub-circuit. Even in the subcircuit under test, at any given time, only a small section of the LUTs are used by the testing procedure. In this way the degradation of the application is kept at a minimum. The proposed algorithm is in-place, i.e. it does not alter the routing structure of the application. View full abstract»

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  • Test response compression based on Huffman coding [logic IC testing]

    Page(s): 446 - 449
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (266 KB) |  | HTML iconHTML  

    Test compression/decompression is an efficient method for reducing the test application cost. In this paper, we propose a response compression method based on Huffman coding. The proposed method guarantees zero-aliasing because faulty responses are mapped into code words, not just fault-free ones. Moreover, the method is independent of the fault model and the structure of a circuit-under-test, and uses only the knowledge of the fault-free responses corresponding to a given test input set. Experimental results of the compression ratio and the size of the encoder for the proposed method are presented. View full abstract»

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  • BDD based synthesis of symmetric functions with full path-delay fault testability

    Page(s): 290 - 293
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (282 KB) |  | HTML iconHTML  

    A new technique for synthesizing totally symmetric Boolean functions is presented that achieves complete robust path delay fault testability. BDDs are used for the synthesis step. Only one additional input and one inverter are needed to achieve 100% Path Delay Fault (PDF) testability. The size of the circuit is guaranteed to be at most quadratic in the number of inputs. The test vectors for any PDF can be generated in linear time. Experimental results underline the efficiency of the technique. In contrast to previous approaches, the technique can also be applied to multi-output functions. View full abstract»

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  • Test data volume reduction by test data realignment

    Page(s): 434 - 439
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (219 KB) |  | HTML iconHTML  

    We explore an approach to input test data compression called realignment. Realignment changes a test sequence T consisting of n-bit vectors into a sequence T(m) consisting of m-bit vectors for m ≥ n. It then compresses T(m) instead of T to achieve larger levels of compression for T(m) than for T. By controlling m, realignment provides a range of possible solutions that differ in the data volume reduction and the amount of memory required between the decompressor and the circuit. The memory is required in order to translate m-bit vectors produced by the decompressor into n-bit vectors required by the circuit. We present experimental results to demonstrate this tradeoff for synchronous sequential circuits. View full abstract»

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  • A sigma-delta modulation based BIST scheme for A/D converters

    Page(s): 124 - 127
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (254 KB) |  | HTML iconHTML  

    In this paper, a built-in self test (BIST) methodology to measure the four key parameters of A/D converters, namely offset error, gain error, integral nonlinearity error and differential nonlinearity error is proposed. A sigma-delta modulation based signal generator is presented which can concurrently produce analog sinusoidal test stimuli and digital sinusoidal reference signals on chip. By comparing the sinusoidal histogram of the ADC output signals with that of the generated reference digital signals, the parameters can be determined on chip based on some previously-derived equations. This BIST scheme has the following advantages: (1) high accuracy; (2) parameter measurement capability for different frequencies; (3) dynamic sinusoidal testing capability; and (4) low chip area overhead. An 8 bit A/D converter with the proposed BIST architecture is designed and simulated using the TSMC 0.35 μm 1P4M technology. The simulation results show that the test accuracies for the four parameters are all within 0.05 LSB. View full abstract»

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  • Designing multiple scan chains for systems-on-chip

    Page(s): 424 - 427
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (290 KB) |  | HTML iconHTML  

    We propose a branch-and-bound framework for designing non-reconfigurable multiple scan chains for systems-on-chip to minimize test application time. Multiple scan chain design problem defined in this paper involves (1) partitioning wrapper cells and core internal scan registers into multiple scan chains, and (2) ordering the wrapper cells and the registers in each scan chain. We design multiple scan chains with test application times within a few percentage of the corresponding optimal in practical run-times. We also demonstrate significant improvements in test application times over prior heuristics for designing multiple scan chains. View full abstract»

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  • IC reliability simulator ARET and its application in design-for-reliability

    Page(s): 18 - 21
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (243 KB) |  | HTML iconHTML  

    To accomplish effective IC reliability evaluation and design-for-reliability (DFR), a reliability, simulator ARET was developed at Georgia Tech. ARET simulates IC reliability at both component and system levels. It also handles the ICs with physical defects generated in fabrication by a statistical approach. ARET was verified by a series of stress tests conducted at The Boeing Company, which has shown a promising accuracy. In order to perform a practical DFR, another distinct feature - reliability hotspot identification was developed in ARET. By sensitivity analysis, it can determine the weakest components in the circuit under certain failure mechanisms, which allows a local design update to obtain an improved IC reliability. This makes DFR feasible by saving huge amount of work that needs to be performed in a complete VLSI circuit re-design for reliability. View full abstract»

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  • Optimal system-on-chip test scheduling

    Page(s): 306 - 311
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (251 KB) |  | HTML iconHTML  

    In this paper, we show that the scheduling of tests on the test access mechanism (TAM) is equivalent to independent job scheduling on identical machines and we make use of all existing preemptive scheduling algorithm to produce an optimal solution in linear time. We extend the algorithm to handle (1) test conflicts elite to interconnection tests and (2) cases when a test limits all optimal usage of the TAM by using reconfigurable core test wrappers. Our extensions preserve the production of all optimal solution in respect to test time and minimizes the number of wrapper configurations as well as the TAM usage at each core. which implicitly minimizes the TAM routing. Experiments with our implementation shows its efficiency in comparison with previous approaches. View full abstract»

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  • Automated TTCN-3 test case generation by means of UML sequence diagrams and Markov chains

    Page(s): 102 - 105
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (400 KB) |  | HTML iconHTML  

    The objective of this paper is to automatically generate a MCUM (Markov chain usage model) starting from an OMG UML-SD (sequence diagram) in order to derive TTCN-3 (testing and test control notation version 3) compatible test case definitions. Our approach is a combination of statistical usage testing and specification-based testing. Within this paper, special attention is given to international standardized FDT notations, specifically UML-SD and MSC. We have also defined an XML-based representation format called MCML (Markov chain markup language) to build a common interface between various parts of the MaTeLo tool set. In the case of UML-SD, we use XMI descriptions in order to generate the desired MCML format. View full abstract»

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  • Testing the conformity of transactional attributes of components by simulation

    Page(s): 224 - 227
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (204 KB) |  | HTML iconHTML  

    The conformity of transactional attributes of components is an important issue in designing a large database application system. Although corresponding techniques called Auto-Transaction have been adopted in some products, such as Microsoft Transaction Server (MTS), to protect unconformity errors, there are still many problems in application system. In order to test the unconformity a new method based on the Performance Evaluation Architecture Description Language(PEADL in short) is provided. The conformity of transactional attributes of components is test by comparing the PEADL description of the protocol of transactions summit and the behaviors of simulating performance. To support our viewpoint we have also designed an experiment. View full abstract»

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  • Between-core vector overlapping for test cost reduction in core testing

    Page(s): 268 - 273
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (233 KB) |  | HTML iconHTML  

    This paper proposes a novel method, called "between-core vector overlapping", for parallel core testing of an SoC consisting of full-scanned cores. This method uses small number of input pins in the parallel core testing. An "over-lapped vector" obtained by overlapping all the vectors for all the core is supplied to all the cores in common for parallel core testing. Two methods for short overlapped vectors, "invert overlapping" and "split overlapping", are presented. The impact of further reduction in the number of input pins is also reported. View full abstract»

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  • An on-chip jitter measurement circuit for the PLL

    Page(s): 332 - 335
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (739 KB) |  | HTML iconHTML  

    A simple built-on-chip PLL jitter measurement circuit, which utilizes the vernier delay line principle, transforms timing difference signals into digital words and has a self calibration capability to minimize the mismatched error caused by the process variation, is proposed and demonstrated. View full abstract»

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