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Design Automation. EDAC., Proceedings of the European Conference on

Date 25-28 Feb. 1991

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Displaying Results 1 - 25 of 101
  • EDAC. Proceedings of the European Conference on Design Automation

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    Freely Available from IEEE
  • Goal orientated slicing enumeration through shape function clipping

    Page(s): 361 - 365
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    Two new methods for efficient enumeration of slicing structures useful for macro cell and sea-of-gates final placement are presented. Contrary to existing approaches a further preorder traversal of the slicing tree is added, which allows elimination of unnecessary shapes in an early design phase. Applying this look ahead strategy, memory and computation time requirements have been reduced drastically. Better placements have been achieved by using the saved resources to enlarge the search space for enumeration View full abstract»

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  • MACHETE: synthesis of sequential machines for easy testability

    Page(s): 289 - 293
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    Test generation for sequential machines is known to be computationally expensive. The authors present a scheme, called MACHETE (MACHines for Easy TEstability), for synthesizing easily testable architectures for sequential machines by adding some state transitions and their associated output vectors to the state transition table. This is done to make the internal states of the machine easily controllable as well as observable. This can enable us to obtain a high fault coverage in reasonable amounts of CPU time View full abstract»

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  • Design by similarity using transaction modeling and statistical techniques

    Page(s): 464 - 468
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    Presents a new VLSI design management system. Unlike existing systems it models and stores not only the design data but also a description of the design process itself. This information is accumulated and used to present the designer with alternative design methodologies and to suggest the most promising one, based on previous designs. Experimental results on 22 simple designs indicate that the system selected the most appropriate methodology in 81% of the cases View full abstract»

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  • GENVIEW: a portable source-level debugger for macrocell generators

    Page(s): 408 - 412
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    An effective layout design method for VLSI macrocell is presented. The method describes a way to write, to test and to validate efficient full-custom generators and tilers. First, after a brief overview of the design methodology of tilers, the GENLIB C-library of procedural design functions is described. Second, GENVIEW, a portable and graphic layout debugger for the interactive testing of generators, is detailed View full abstract»

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  • Testability analysis of hierarchical finite state machines

    Page(s): 294 - 301
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    The authors present a hierarchical analysis of interconnected finite state machines helpful for testability evaluation. Formal operators determine the controllable and observable functional parts of the modules of the hierarchy; several kinds of functional redundancies are deduced and their causes are diagnosed. A prototype written in PROLOG validates these concepts View full abstract»

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  • Decomposing data machines

    Page(s): 378 - 382
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    Describes a new FSM decomposition algorithm which extracts a data register from a given FSM. The algorithm is a generalization of the standard minimization algorithm-it selects output values which, when stored in a separate data register, will make additional states in the control machine equivalent. Experimental results show that the algorithm is both effective and fast View full abstract»

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  • Periodic signal suppression in a concurrent fault simulator

    Page(s): 565 - 569
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    Clock suppression has been proposed to take advantage of the periodic signals such as the clock present in synchronous designs. In clock suppression, no events due to the clock input are generated, but the information can be reconstructed as needed. In this paper, the authors present periodic signal suppression, which is a generalized form of clock suppression, as a means to suppress predictable events of all periodic signals throughout the circuit. To do this, a special signal state labeled P is introduced. P states indicate that signals are periodic, but cause no unnecessary activity in an event driven simulator. At any time, the original waveform can be reconstructed from the periodic signal. This general implementation allows clock suppression to work on divided or gated clocks and on signals that may alternate periodic and non-periodic behavior in addition to the clock tree. Moreover, concurrent simulation of faults on the suppressed signal wires including the clock tree is possible View full abstract»

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  • HERESY: a hybrid approach to automatic schematic generation [for VLSI]

    Page(s): 419 - 423
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    An automatic schematic generation system called HERESY is presented, which represents a well-engineered combination of algorithmic and rule-based approaches. Equipped with a set of carefully-chosen evaluation criteria, HERESY is able to generate high-quality, reasonably general classes of schematic diagrams in an efficient way. A novel levelization algorithm that can detect and resolve arbitrary cyclic structures of a circuit is described. An example schematic generated by HERESY, together with its computational efficiency is also presented View full abstract»

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  • Area and performance optimizations in path-based scheduling

    Page(s): 304 - 310
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    The authors describe the area and performance optimizations implemented in the As-Fast-As-Possible (AFAP) scheduling algorithm. The AFAP scheduling algorithm is a path-based technique that finds the minimum number of control steps for all possible sequences of operations in the control-flow graph, under given constraints. Area requirements for functional units, such as their number and type, are translated into constraints which are then met exactly. The number of registers is also minimized. The performance optimizations included in this paper are concerned mainly with the scheduling of loops View full abstract»

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  • Iterative compaction: an improved approach to graph and circuit bisection

    Page(s): 523 - 527
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    Given a graph G=(V,E), graph bisection is the problem of finding a partition of the vertex set V in two equal-sized subsets V1 and V2 so that the number of edges between them is minimized. This problem has important applications in circuit partitioning, testing, VLSI design and other network-related problems that apply the divide-and-conquer strategy. The authors introduce a new heuristic approach, called iterative compaction (IC), which employees a node degree based matching and iterative graph compaction. This gives a significant improvement over the performance of known bisection algorithms in both time and quality of the results View full abstract»

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  • Model-based fault diagnosis of sequential circuits and its acceleration

    Page(s): 224 - 229
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    Describes an algorithm for the location of faulty components in digital circuits using the model-based approach to circuit fault diagnosis. The model-based approach is first extended to apply to synchronous sequential circuits. Acceleration strategies that exploit domain knowledge particular to digital circuits are then proposed. The effect of these acceleration strategies is a drastic reduction in the execution time of the diagnosis procedure. The effectiveness and performance of the diagnosis algorithm are illustrated through an example for which encouraging results are obtained View full abstract»

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  • The VLSI-programming language Tangram and its translation into handshake circuits

    Page(s): 384 - 389
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    Views VLSI design as a programming activity. VLSI designs are described in the algorithmic programming language Tangram. The paper gives an overview of Tangram, providing sufficient detail to invite the reader to try a small VLSI program himself. Tangram programs can be translated into handshake circuits, networks of elementary components that interact by handshake signaling. The authors have constructed a silicon compiler that automates this translation and converts these handshake circuits into asynchronous circuits and subsequently into VLSI layouts View full abstract»

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  • GRTL-a graphical platform for pipelined system design

    Page(s): 424 - 428
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    Presents GRTL, a graphical design tool specifically for manual design of synchronous pipelines at the register transfer level. Abstractions (parameterized behavioral components, abstract signals) and AI methodology simplify input and reduce detail, yet useful timing analyses can be obtained. Features include integrated interactive design blackboard, Werner diagram and clocking formalisms for design correctness, open library, reversible functional simulator, and down-loading facility for external silicon compilation. Earlier work is contrasted View full abstract»

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  • PHIDEO: a silicon compiler for high speed algorithms

    Page(s): 436 - 441
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    PHIDEO is a silicon compiler targeted at the design of high performance real time systems with high sampling frequencies such as HDTV. It supports the complete design trajectory starting from a high level specification all the way down to layout. New techniques are used to perform global optimisations across loop boundaries in hierarchical flow graphs. The compiler is based on a new target architectural model. Apart from the datapaths special attention is paid to memory optimisation. The new techniques are demonstrated using a progressive scan conversion algorithm View full abstract»

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  • A hierarchical approach to timing verification in CMOS VLSI design

    Page(s): 266 - 270
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    The author describes a novel hierarchical approach to timing verification. Four types of relationship existing among signal paths are distinguished, based on a classification of the degree of interdependency in the circuit. In this way, irrelevant path delays can be excluded through consideration of the interaction between critical paths and others. Furthermore, under suitable conditions, bounded delay values for large hierarchical systems can be deduced using bounded delays determined for their constituent cells. Finally, the authors discuss the impact on design strategy of the hierarchical delay model presented in this paper View full abstract»

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  • A proposed hardware fault simulation engine

    Page(s): 570 - 574
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    Fault simulation is a essential part of the design cycle and for large circuits it can be very time consuming. The authors examine the possibility of hardware acceleration of this process, especially that of sequential circuits. In order to achieve this, the architecture of a pipelined hardware simulation accelerator, the MANchester Simulation Engine (MANSE), is examined. Finally, the modifications necessary to make MANSE capable of fault simulation are considered View full abstract»

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  • Circuit partitioning for waveform relaxation

    Page(s): 149 - 153
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    New partitioning strategies for the simulation of bipolar circuits using the waveform relaxation method are presented. On the one hand concepts known from layout-generation and node tearing simulation are used. On the other hand the hierarchical structure of the circuit description list and a minimal-cut criterion is used to find a good partitioning. With the help of these new partitioning algorithms it is possible for the first time to simulate large bipolar circuits using waveform relaxation. The applicability of the algorithms is demonstrated by the simulation of real-life circuits View full abstract»

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  • On L×n Boolean matrices with all L×k submatrices having 2k distinct row vectors

    Page(s): 528 - 532
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    The author describes a new method to construct an L×n boolean matrix for two given integers n and k (k<n), such that every L ×k submatrix contains 2k distinct row vectors of {1,0}k. The magnitude of L is O((log n)2logk). This method has considerable advantage for small k and practical n. It can be applied to test generation of VLSI circuits, design of threshold circuits and fault tolerant systems, and other fields View full abstract»

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  • On the selection of a partial scan path with respect to target faults

    Page(s): 219 - 223
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    Today the most often applied DFT-strategy is full scan path. To reduce its overhead a partial scan path can be selected. For minimizing the size of the partial scan path, existing testpatterns are used which will detect a part of the faults. Only the remaining faults, so called target faults have to be addressed using partial scan. Different methods are given to adapt a partial scan path to the target faults. They do not depend on ATPG and therefore have very short runtimes. Results on sequential ATPG-benchmarks show that a strong reduction in the size of the partial scan path is possible View full abstract»

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  • An algorithm for improving optimal placement for river-routing

    Page(s): 232 - 236
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    Describes a linear-time, terminal-position assignment algorithm that can be used in conjunction with the optimal-placement-for-river-routing algorithm to eliminate, or greatly reduce, the routing area between cells within a module. The terminal-position algorithm that is described, may be used to optimize the positions of the interconnections between the interior rows and columns of cells within a module for custom module generation. The method uses river routing within the cells to virtually eliminate routing channels between the cell rows and columns while producing little or no increase in cell area. Use of this pin assignment algorithm for optimizing the interconnections between custom-synthesized cells provides a significant improvement in area usage View full abstract»

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  • Glue-logic partitioning for floorplans with a rectilinear datapath

    Page(s): 162 - 166
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    Describes a novel glue-logic partitioning algorithm for floorplan generation in a constrained rectilinear area. This algorithm dissects the layout area into area blocks according to the given module aspect ratio. The algorithm estimates the transistor capacity for each area block, and then uses a seed-based multiway partitioning strategy to assign glue-logic components into area blocks. The algorithm runs iteratively and selects the partition with the minimum total area as the final floorplan. The examples demonstrate the algorithm's suitability for top-down hierarchical physical design View full abstract»

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  • Synthesis of fully testable sequential machines

    Page(s): 283 - 288
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    A circuit consists of logic and memory elements. Testing of a circuit involves testing both. Typically, it takes long input sequences to initialize memory elements. Without initialization of memory elements, testing is not possible. In the classical approach to design for test, such as scan design, modifications are made to the circuit to obtain easy and full controllability and observability of the memory elements. The author addresses the design for testability issue for non-scan designs, where both controllability and observabilities are reduced. In the process one ends up with a design that is also suitable for concurrent checking. Concurrent checking is a verification process, which is performed concomitantly with normal operation. The technique described here incurs an area overhead but almost no performance penalty View full abstract»

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  • A self-checking PLA automatic generator tool based on unordered codes encoding

    Page(s): 510 - 515
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    Self-checking circuits ensure concurrent error detection by means of hardware redundancy. An important drawback of self-checking circuits is the fact that they involve a significant increasing of the design time. Specific CAD tools are needed in order to cope with this drawback. In this paper the authors present a tool allowing automatic generation of self-checking PLAs. Then they validate this tool by transforming a set of PLA benchmarks into self-checking PLAs and give statistics concerning the required area overhead View full abstract»

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  • On variable ordering of binary decision diagrams for the application of multi-level logic synthesis

    Page(s): 50 - 54
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    Develops multi-level logic minimization programs using binary decision diagram (BDD). The authors present variable ordering methods of BDD. The variable ordering algorithm for two-level circuits is based on cover patterns and selects most binate variables first, and the one for multi-level circuits is based on depth first traverse of circuits. In both cases, the acquired variable orderings are optimized by exchanging a variable with its neighbor in the ordering View full abstract»

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