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Proceedings of the European Conference on Design Automation.

25-28 Feb. 1991

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Displaying Results 1 - 25 of 101
  • EDAC. Proceedings of the European Conference on Design Automation

    Publication Year: 1991
    Request permission for commercial reuse | PDF file iconPDF (12 KB)
    Freely Available from IEEE
  • PLATO-a CAD tool for logic synthesis based on decomposition

    Publication Year: 1991, Page(s):65 - 69
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (392 KB)

    A CAD system for logic synthesis (PLATO system) that exploits logic decomposition to optimize the actual circuit is presented. Unlike the traditional approach, where the partitioning or decomposition follows logic minimization, decomposition process is carried out in the PLATO system as the very first step in the logic synthesis. Experimental results indicate that a significant reduction of the si... View full abstract»

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  • Circuit partitioning for waveform relaxation

    Publication Year: 1991, Page(s):149 - 153
    Cited by:  Papers (9)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    New partitioning strategies for the simulation of bipolar circuits using the waveform relaxation method are presented. On the one hand concepts known from layout-generation and node tearing simulation are used. On the other hand the hierarchical structure of the circuit description list and a minimal-cut criterion is used to find a good partitioning. With the help of these new partitioning algorit... View full abstract»

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  • Module synthesis for finite state machines

    Publication Year: 1991, Page(s):581 - 585
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (364 KB)

    The authors present a new layout style for automatic synthesis of finite state machines which is suitable for full custom as well as sea-of-gate layouts. It is based on a combined use of slice techniques, which result in a compact layout and a matrix layout style to ensure the flexibility of this approach. For the layout optimization, multiple row folding has to be performed, for which a genetic o... View full abstract»

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  • Formal method for self-timed design

    Publication Year: 1991, Page(s):197 - 201
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB)

    A formal method of self-timed circuit design, based on compact event model-change diagrams (CD), is suggested. This model (CD) seems to be very attractive because of convenient tools for describing the semantics of concurrency which allows one to enhance the specification from distributive class of processes to semimodular ones. The necessary and sufficient conditions of CD correctness and polynom... View full abstract»

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  • Synthesis of multi-level logic with one symbolic input

    Publication Year: 1991, Page(s):60 - 64
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    Presents algorithms that perform multi-level logic synthesis on logic with one symbolic input. This method contrasts to existing approaches that encode a symbolic input before logic synthesis. These approaches determine the encoding based on heuristic estimates. The present algorithms, which perform logic synthesis directly on the logic with the symbolic input, enable one to encode the symbolic in... View full abstract»

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  • Concurrent min-max simulation

    Publication Year: 1991, Page(s):554 - 557
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (284 KB)

    Parametric process variations, which are inherent in the manufacture of complex digital circuits, can cause variations in the timing characteristics of a digital device. These device timing variations can cause catastrophic failures to the intended logical operation of the whole design. Min-max timing simulation is simulation technique which is well suited to verify that a given design functions c... View full abstract»

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  • Translating system specifications to VHDL

    Publication Year: 1991, Page(s):390 - 394
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB)

    Languages based on hierarchical and concurrent state diagrams are powerful in specifying system level designs. Simulating such languages can be simplified by translating to a simulation language such as VHDL and then using available simulators. This paper describes system level abstractions commonly found in specification languages and presents semantic preserving VHDL implementations View full abstract»

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  • SWEC: a stepwise equivalent conductance timing simulator for CMOS VLSI circuits

    Publication Year: 1991, Page(s):142 - 148
    Cited by:  Papers (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (456 KB)

    Timing simulation has always been considered a crucial step in digital VLSI circuit design. Many researchers have addressed the issues of time efficiency vs. accuracy by using simpler device models and by simplifying the numerical algorithms. StepWise Equivalent Conductance (SWEC) simulation technique is an alternative which approximates the nonlinear transfer characteristic of the transistor with... View full abstract»

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  • On the selection of a partial scan path with respect to target faults

    Publication Year: 1991, Page(s):219 - 223
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    Today the most often applied DFT-strategy is full scan path. To reduce its overhead a partial scan path can be selected. For minimizing the size of the partial scan path, existing testpatterns are used which will detect a part of the faults. Only the remaining faults, so called target faults have to be addressed using partial scan. Different methods are given to adapt a partial scan path to the ta... View full abstract»

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  • A performance analysis tool for performance-driven micro-cell generation

    Publication Year: 1991, Page(s):576 - 580
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB)

    A new method is presented to determine the power dissipation and propagation-delay time of small logical blocks (micro-cells). This method is a combination of the RC-tree and the macro modeling methods. It is a fast and accurate method, three orders of magnitude faster that SPICE, while the maximal error is ten percent. This method can be used in a performance-driven micro-cell generator for a sea... View full abstract»

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  • Fast heuristic algorithms for finite state machine minimization

    Publication Year: 1991, Page(s):192 - 196
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    A technique for the minimization of completely and incompletely specified sequential machines is described. By employing fast heuristic algorithms, it is shown that it is possible to effectively reduce large (121 states) finite state machines in reasonable computing time when compared to other methods. It has been shown that it is possible to achieve area/literal reductions in the range of 30-100%... View full abstract»

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  • PHIFACT-a design space exploration program

    Publication Year: 1991, Page(s):55 - 59
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (380 KB)

    PHIFACT is a program to synthesize combinational blocks for performance. This is mainly achieved by design space exploration at logic level. The basic multi-level architecture of the block is gradually constructed during a Boolean phase, where look ahead tools guarantee optimality. During a subsequent local restructuring phase, optimal circuits scattered in subregions of the design space are explo... View full abstract»

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  • Optimization techniques for multiple output function synthesis

    Publication Year: 1991, Page(s):545 - 551
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (492 KB)

    Design of multiple outputs CMOS combinational gates is considered. Two techniques for the minimization of multiple output functions at the switching level are introduced. These techniques are based on innovative transistor interconnection structures named Delta and Lambda networks. A branch and bound algorithm to be used for complex gate synthesis is presented. Design examples are also provided. I... View full abstract»

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  • LAST: a layout area and shape function estimator for high level applications

    Publication Year: 1991, Page(s):351 - 355
    Cited by:  Papers (20)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB)

    The author addresses the problem of area prediction of VLSI layouts. They present an approach based on two models, analytical and constructive. A circuit design is recursively partitioned down to a level specified by the user thus generating a slicing tree. An analytical model is then used to predict the shape functions of the leaf subcircuits. By traversing the tree bottom up the shape function o... View full abstract»

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  • GRTL-a graphical platform for pipelined system design

    Publication Year: 1991, Page(s):424 - 428
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (436 KB)

    Presents GRTL, a graphical design tool specifically for manual design of synchronous pipelines at the register transfer level. Abstractions (parameterized behavioral components, abstract signals) and AI methodology simplify input and reduce detail, yet useful timing analyses can be obtained. Features include integrated interactive design blackboard, Werner diagram and clocking formalisms for desig... View full abstract»

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  • The VLSI-programming language Tangram and its translation into handshake circuits

    Publication Year: 1991, Page(s):384 - 389
    Cited by:  Papers (82)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (420 KB)

    Views VLSI design as a programming activity. VLSI designs are described in the algorithmic programming language Tangram. The paper gives an overview of Tangram, providing sufficient detail to invite the reader to try a small VLSI program himself. Tangram programs can be translated into handshake circuits, networks of elementary components that interact by handshake signaling. The authors have cons... View full abstract»

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  • Eldo-XL: a software accelerator for the analysis of digital MOS circuits by an analog simulator

    Publication Year: 1991, Page(s):136 - 141
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (372 KB)

    Eldo-XL is composed of a set of techniques developed on the basis of the Eldo analog simulator and integrated in it. Eldo-XL is targeted at the simulation of MOS digital circuits with minimal loss of accuracy compared to Eldo. The basis of Eldo-XL is a simpler MOS transistor model which allows the analytical solution of the nodal equations most of the time. The costly iterations associated the imp... View full abstract»

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  • Towards optimizing global mincut partitioning

    Publication Year: 1991, Page(s):167 - 171
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    Mincut algorithms have received much attention in the past for treating the placement problem in layout synthesis. The paper introduces a new class of mincut partitioning algorithms (SQP) meeting global minimization requirements. The new class of algorithms in its different variations is empirically compared with the classical mincut procedures as well as with recent extensions. The new algorithms... View full abstract»

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  • HITEC: a test generation package for sequential circuits

    Publication Year: 1991, Page(s):214 - 218
    Cited by:  Papers (450)  |  Patents (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (380 KB)

    Presents HITEC, a sequential circuit test generation package to generate test patterns for sequential circuits, without assuming the use of scan techniques or a reset state. Several new techniques are introduced to improve the performance of test generation. A targeted D element technique is presented, which greatly increases the number of possible mandatory assignments and reduces the over-specif... View full abstract»

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  • A proposed hardware fault simulation engine

    Publication Year: 1991, Page(s):570 - 574
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (400 KB)

    Fault simulation is a essential part of the design cycle and for large circuits it can be very time consuming. The authors examine the possibility of hardware acceleration of this process, especially that of sequential circuits. In order to achieve this, the architecture of a pipelined hardware simulation accelerator, the MANchester Simulation Engine (MANSE), is examined. Finally, the modification... View full abstract»

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  • Exact and heuristic algorithms for the minimization of incompletely specified state machines

    Publication Year: 1991, Page(s):184 - 191
    Cited by:  Papers (30)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (672 KB)

    Presents two exact algorithms for state minimization of FSM's. The authors' results prove that exact state minimization is feasible for a large class of practical examples, certainly including most hand-designed FSM's. They also present heuristic algorithms, that can handle large, machine-generated, FSM's. They argue that the true objective of state reduction should be reduction toward maximal enc... View full abstract»

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  • On variable ordering of binary decision diagrams for the application of multi-level logic synthesis

    Publication Year: 1991, Page(s):50 - 54
    Cited by:  Papers (98)  |  Patents (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    Develops multi-level logic minimization programs using binary decision diagram (BDD). The authors present variable ordering methods of BDD. The variable ordering algorithm for two-level circuits is based on cover patterns and selects most binate variables first, and the one for multi-level circuits is based on depth first traverse of circuits. In both cases, the acquired variable orderings are opt... View full abstract»

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  • A fast and efficient algorithm for determining fanout trees in large networks

    Publication Year: 1991, Page(s):539 - 544
    Cited by:  Papers (11)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (408 KB)

    The authors present a heuristic algorithm the optimal selection of the fanout tree structures in VLSI circuit design. The algorithm minimizes area of the added buffers under the specified timing constraints. The algorithms described in the literatures solve a simpler problem of minimizing the circuit's timing without taking into account the area increase introduced by the buffers. Experimental res... View full abstract»

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  • Formal sizing rules of CMOS circuits

    Publication Year: 1991, Page(s):96 - 100
    Cited by:  Papers (7)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB)

    Presents a local strategy for sizing CMOS circuits. The authors show how the explicit definition of delays can be used to define delay/area optimal sizing rules. Examples are given for sizing irregular inverter arrays, NAND gates and adder cells, starting from an initial electrical netlist and ending with the fully automatically generated layout. Direct comparisons of speed/area performances are g... View full abstract»

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