Proceedings of the European Conference on Design Automation.

25-28 Feb. 1991

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Displaying Results 1 - 25 of 101
  • EDAC. Proceedings of the European Conference on Design Automation

    Publication Year: 1991
    Request permission for commercial reuse | PDF file iconPDF (12 KB)
    Freely Available from IEEE
  • A self-checking PLA automatic generator tool based on unordered codes encoding

    Publication Year: 1991, Page(s):510 - 515
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (576 KB)

    Self-checking circuits ensure concurrent error detection by means of hardware redundancy. An important drawback of self-checking circuits is the fact that they involve a significant increasing of the design time. Specific CAD tools are needed in order to cope with this drawback. In this paper the authors present a tool allowing automatic generation of self-checking PLAs. Then they validate this to... View full abstract»

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  • Experiments with autonomous test of PLAs

    Publication Year: 1991, Page(s):503 - 509
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB)

    An architecture for BIST of PLAs is presented, together with a testability analysis tool to assert test quality. The functionality of the PLA itself is utilized for stimuli generation. Experiments assert that the test patterns generated can be considered as random patterns with equal 1 and 0 probability of each input. Test quality is measured based upon computed fault detectability and estimated f... View full abstract»

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  • Address generation for array access based on modulus m counters

    Publication Year: 1991, Page(s):118 - 123
    Cited by:  Papers (16)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (344 KB)

    The necessary task of address generation for RAM and ROM accesses can often result in hardware taking up an appreciable fraction of the area of a data processing IC. Close examination of the address sequences can reveal symmetry which may be exploited to automatically devise small and simple address generators, based on counters. The authors describe automated techniques used to recognise and deve... View full abstract»

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  • Structure based methods for parallel pattern fault simulation in combinational circuits

    Publication Year: 1991, Page(s):497 - 502
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB)

    The authors present several methods which accelerate fault simulation for combinational circuits using parallel pattern evaluation. The methods are based on an extensive structure analysis of the considered circuit. On the one hand the developed methods aim at a reduction of fan-out stems for which the fault simulation has to be performed and on the other hand at a reduction of gate evaluations du... View full abstract»

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  • Restructuring VLSI layout representations for efficiency

    Publication Year: 1991, Page(s):111 - 116
    Cited by:  Papers (1)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (412 KB)

    VLSI mask layouts usually have a hierarchical representation which serves to record the structure of the design while saving storage space. It is often convenient to work directly on such a representation for performing some operations. However for many other operations it is preferable to work on the flattened representation of the circuit. The authors look at the unnesting operation on layouts t... View full abstract»

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  • Module synthesis for finite state machines

    Publication Year: 1991, Page(s):581 - 585
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (364 KB)

    The authors present a new layout style for automatic synthesis of finite state machines which is suitable for full custom as well as sea-of-gate layouts. It is based on a combined use of slice techniques, which result in a compact layout and a matrix layout style to ensure the flexibility of this approach. For the layout optimization, multiple row folding has to be performed, for which a genetic o... View full abstract»

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  • Formal methods for silicon compilation

    Publication Year: 1991, Page(s):395 - 400
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (344 KB)

    At the Philips Research Laboratories there is a large research effort on silicon compilation for DSP applications. The PIRAMID system is a prototype compiler which is capable of going from specification to layout within a few hours. The input language for PIRAMID has an applicative nature and is called SILAGE. In order to reduce the number of mistakes made during specification a good formal semant... View full abstract»

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  • Fast heuristic algorithms for finite state machine minimization

    Publication Year: 1991, Page(s):192 - 196
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    A technique for the minimization of completely and incompletely specified sequential machines is described. By employing fast heuristic algorithms, it is shown that it is possible to effectively reduce large (121 states) finite state machines in reasonable computing time when compared to other methods. It has been shown that it is possible to achieve area/literal reductions in the range of 30-100%... View full abstract»

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  • Symbolic implication in test generation

    Publication Year: 1991, Page(s):492 - 496
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB)

    All test generation algorithms make use of symbolic algebra. The symbolic value that most test generators use is `X', to denote the unknown/do not care logic value. The other end of the spectrum is to shade each X differently to fully exploit the information contained in them. This is impractical due to combinatorial explosion that results from such coloring. In this paper, the authors explore use... View full abstract»

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  • Electrical modelling of lossy on-chip multilevel interconnecting lines

    Publication Year: 1991, Page(s):106 - 110
    Cited by:  Papers (1)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB)

    A self contained method for the electrical modelling of lossy 3-D multilevel interconnections has been developed. The method allows for the generation of a multiple coupled line model, compatible with SPICE-like CAD programs, from the interconnection line constants and parasitic coupling parameters which are computed by the so-called method of moments. The proposed method can be used for the analy... View full abstract»

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  • A performance analysis tool for performance-driven micro-cell generation

    Publication Year: 1991, Page(s):576 - 580
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB)

    A new method is presented to determine the power dissipation and propagation-delay time of small logical blocks (micro-cells). This method is a combination of the RC-tree and the macro modeling methods. It is a fast and accurate method, three orders of magnitude faster that SPICE, while the maximal error is ten percent. This method can be used in a performance-driven micro-cell generator for a sea... View full abstract»

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  • Tool communication in an integrated synthesis environment

    Publication Year: 1991, Page(s):28 - 32
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB)

    A tight integration strategy developed during the realization of a hardware synthesis system is described. It allows online visualization of data changes caused for example by a synthesis tool. Common data schemes for various design views were designed. For manipulation of each design view one abstract data type is provided, avoiding redundant implementations. Communication structures for concurre... View full abstract»

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  • Translating system specifications to VHDL

    Publication Year: 1991, Page(s):390 - 394
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB)

    Languages based on hierarchical and concurrent state diagrams are powerful in specifying system level designs. Simulating such languages can be simplified by translating to a simulation language such as VHDL and then using available simulators. This paper describes system level abstractions commonly found in specification languages and presents semantic preserving VHDL implementations View full abstract»

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  • Exact and heuristic algorithms for the minimization of incompletely specified state machines

    Publication Year: 1991, Page(s):184 - 191
    Cited by:  Papers (30)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (672 KB)

    Presents two exact algorithms for state minimization of FSM's. The authors' results prove that exact state minimization is feasible for a large class of practical examples, certainly including most hand-designed FSM's. They also present heuristic algorithms, that can handle large, machine-generated, FSM's. They argue that the true objective of state reduction should be reduction toward maximal enc... View full abstract»

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  • Interactive symbolic distortion analysis of analogue integrated circuits

    Publication Year: 1991, Page(s):484 - 488
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    A program is presented that generates symbolic expressions for the harmonic distortion, caused by weak nonlinearities in continuous-time analogue integrated circuits. The program relies upon the theory of Volterra series. An approximation algorithm with a user-definable error enhances the interpretability of the expressions. The results are in good agreement with results from a numerical simulator... View full abstract»

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  • Synthesis of multi-level logic with one symbolic input

    Publication Year: 1991, Page(s):60 - 64
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    Presents algorithms that perform multi-level logic synthesis on logic with one symbolic input. This method contrasts to existing approaches that encode a symbolic input before logic synthesis. These approaches determine the encoding based on heuristic estimates. The present algorithms, which perform logic synthesis directly on the logic with the symbolic input, enable one to encode the symbolic in... View full abstract»

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  • GRTL-a graphical platform for pipelined system design

    Publication Year: 1991, Page(s):424 - 428
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (436 KB)

    Presents GRTL, a graphical design tool specifically for manual design of synchronous pipelines at the register transfer level. Abstractions (parameterized behavioral components, abstract signals) and AI methodology simplify input and reduce detail, yet useful timing analyses can be obtained. Features include integrated interactive design blackboard, Werner diagram and clocking formalisms for desig... View full abstract»

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  • Fast functional evaluation of candidate OBDD variable orderings

    Publication Year: 1991, Page(s):4 - 10
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (552 KB)

    Symbolic simulation via ordered binary decision diagrams (OBDDs) is becoming more feasible each year. These representations are often very efficient under an appropriate ordering of the variables of the functions represented. Recently, heuristics for ordering variables have been developed, but due to the nature of heuristics, no single heuristic always produces an appropriate ordering. The authors... View full abstract»

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  • Delay estimation for CMOS functional cells

    Publication Year: 1991, Page(s):101 - 105
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (308 KB)

    Presents a new RC tree network model for delay estimation of CMOS functional cells. The model is able to reflect topological changes within a cell, which is of particular interest when doing performance driven layout synthesis. Further, a set of algorithms to perform worst case analysis on arbitrary CMOS functional cells using the proposed delay model, is presented. Both model and algorithms have ... View full abstract»

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  • Optimization of microcontrollers by partitioning

    Publication Year: 1991, Page(s):368 - 373
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (412 KB)

    Presents a new partitioning method for finite state machines (FSMs). The method is particularly well suited for μ-controller circuits. It consists in grouping the μ-instructions of the control graph into classes according to a compatibility property of the output values. Only one sequence of output values is then generated for all μ-instructions of a given class. The resulting structure i... View full abstract»

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  • A proposed hardware fault simulation engine

    Publication Year: 1991, Page(s):570 - 574
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (400 KB)

    Fault simulation is a essential part of the design cycle and for large circuits it can be very time consuming. The authors examine the possibility of hardware acceleration of this process, especially that of sequential circuits. In order to achieve this, the architecture of a pipelined hardware simulation accelerator, the MANchester Simulation Engine (MANSE), is examined. Finally, the modification... View full abstract»

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  • Eldo-XL: a software accelerator for the analysis of digital MOS circuits by an analog simulator

    Publication Year: 1991, Page(s):136 - 141
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (372 KB)

    Eldo-XL is composed of a set of techniques developed on the basis of the Eldo analog simulator and integrated in it. Eldo-XL is targeted at the simulation of MOS digital circuits with minimal loss of accuracy compared to Eldo. The basis of Eldo-XL is a simpler MOS transistor model which allows the analytical solution of the nodal equations most of the time. The costly iterations associated the imp... View full abstract»

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  • Verification of synthesized circuits at register transfer level with flow graphs

    Publication Year: 1991, Page(s):22 - 26
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB)

    Presents a new approach to the verification of automatically synthesized register transfer structures. Horizontal verification is performed on the flow graph which is largely a syntax independent representation of behavior. After extracting a flow graph from the register transfer structure by symbolic simulation, the extracted and the specified flow graphs are normalized into a normal form. A comp... View full abstract»

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  • The VLSI-programming language Tangram and its translation into handshake circuits

    Publication Year: 1991, Page(s):384 - 389
    Cited by:  Papers (87)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (420 KB)

    Views VLSI design as a programming activity. VLSI designs are described in the algorithmic programming language Tangram. The paper gives an overview of Tangram, providing sufficient detail to invite the reader to try a small VLSI program himself. Tangram programs can be translated into handshake circuits, networks of elementary components that interact by handshake signaling. The authors have cons... View full abstract»

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