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Semiconductor Manufacturing, 2003 IEEE International Symposium on

Date 30 Sept.-2 Oct. 2003

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Displaying Results 1 - 25 of 122
  • Intelligent sample test using cost based methodologies

    Publication Year: 2003, Page(s):439 - 442
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB)

    In today's vertically integrated semiconductor companies, the entire manufacturing process impacts the product's bottom line. Wafer test was designed to eliminate expensive assembly of bad die. Wafer test costs are becoming high so time spent testing is less cost effective. Sample testing is a technique for lowering wafer test costs. Careful tuning can optimize the process. This paper introduces a... View full abstract»

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  • GOI improvement in analog CMOS split gate process

    Publication Year: 2003, Page(s):171 - 174
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (373 KB)

    We investigated how wafer charging before gate oxide clean impacted on GOI (Gate Oxide Integrity) in Analog CMOS split gate (dual gate) process. This wafer charging was caused by the develop rinse step of split gate pattern process, and it caused GOI degradation during dilute HF dipping for gate oxide over electrically isolated structure from the substrate. We found that light illumination with su... View full abstract»

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  • Advanced gate process critical dimension control in semiconductor manufacturing

    Publication Year: 2003, Page(s):382 - 385
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (316 KB)

    Control on the order of nanometers is crucial for gate etch, in which the smaller the gate, the faster and more valuable the resulting chip. To date, feed-forward and closed-loop schemes have been created, using a series of standalone systems in the process flow. Lately, integrating metrology capabilities with an etch platform has been proven practicable. This paper presents a model for closed-loo... View full abstract»

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  • Option-based capacity planning for semiconductor manufacturing

    Publication Year: 2003, Page(s):77 - 80
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (340 KB)

    Due to high cost of capacity investment, many semiconductor manufacturing companies have exhibited the need to pursuit innovative capacity plans and planning methods. In this paper, a case study of option-based capacity planning is presented. Three issues are addressed: estimation of production cost parameters, valuation of capacity, and analysis design. It is shown that the option-based approach,... View full abstract»

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  • 300 mm one-way front opening shipping box

    Publication Year: 2003, Page(s):443 - 446
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (364 KB)

    Supply chain and management of a re-usable 300 mm wafer-carrier shipping model for semiconductor high-volume manufacturing was identified as a significant cost savings opportunity for Intel. Breakthrough design and manufacture of a thermoformed, SEMI-compliant, one-way disposable 300mm wafer shipping carrier, codenamed "1WFOSB," has been accomplished. A 1WFOSB model eliminates empty overseas wafer... View full abstract»

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  • Tactical advanced process control

    Publication Year: 2003, Page(s):358 - 361
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (330 KB)

    To reduce implementation costs, maximize flexibility, and better manage intellectual property associated with Advanced Process Control (APC) systems, we present our experiences with tactical APC (TAPC) applications built upon established in-house tool automation, measurement collection, statistical process control (SPC), and process recipe management. TAPC includes process and software engineers, ... View full abstract»

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  • Removal of particles from wafer stage using wafer-formed cleaning material (cleaning wafer)

    Publication Year: 2003, Page(s):389 - 391
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (268 KB)

    As a method of removing particles from a wafer stage. The use of a wafer-shaped cleaning material (hereafter, Cleaning Wafer) was considered for removal of the particles. One concern in using a Cleaning Wafer was that it might be caught in the wafer transfer system; such a failure can be prevented by adjusting the viscoelasticity parameters of the cleaning layer. The other concern was that the Cle... View full abstract»

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  • Application of hydrogenated water to united water supply system for high performance and step-by-step investment type system LSI manufacturing fab

    Publication Year: 2003, Page(s):14 - 17
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (322 KB)

    This study was carried on to contribute the application of hydrogenated water to future water supply system. It shows that using hydrogenated water can perfectly control flowing out from surface for all pipe line materials, so that its application enables cooling water system to unite with ultrapure water (UPW) system for a high performance and step-by-step investment type system LSI manufacturing... View full abstract»

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  • Reengineering supply chain management architecture for the collaboration of marketing dynamics and manufacturing strategy

    Publication Year: 2003, Page(s):81 - 83
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (265 KB)

    Supply Chain Management (SCM) is the contemporary way to fulfill customer satisfaction and corporate objectives. It's brilliant at creating company value with the minimum cost to the world-class manufacture and service provider. However, from both the paper review and the observation of the global industry, it shows that the industry was dramatically suffered the Bullwhip Effect in supply chains, ... View full abstract»

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  • Evaluation of aluminum contamination on large-diameter wafers in ULSI fabrication

    Publication Year: 2003, Page(s):229 - 232
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (407 KB)

    Sophisticated impurity extraction methods, VPD (vapor phase deposition) and PEM (pack extraction method), were used to analyze the Al contamination on the back side of large-diameter reclaim wafers. Compared with the VPD method, HF/HNO3-PEM was found to be more effective to extract impurities from the surface layers of wafers. Al based slurry residues and Al embedded in the remaining su... View full abstract»

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  • Equipment buffering strategy to maximize productivity

    Publication Year: 2003, Page(s):329 - 332
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (377 KB)

    In the infancy of 300mm, I300I and J300 adopted a cost-effective 1+1 loadport buffering for most tools with a few exceptions (litho link, implant) where the run-rate and expected utilization of the tool motivated a larger buffer. Metrology tools, inspite of their very high run-rates, were to follow the standard 1+1 configuration due to the cost and footprint impact of additional loadports relative... View full abstract»

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  • Improvement of mini fab uptime by the multi-task and multi-functional tools

    Publication Year: 2003, Page(s):73 - 76
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (331 KB)

    Multi-task and multi-functional tools can achieve alternative operations for example LPCVD deposition of both Poly Si and SiN films with good repeatability and few particulate. Using those tools we can reduce total tool number and "only-one tool" which means one tool only exists for a type of tool in the fab. We have also considered mini-fab availabilities and evaluate both methods of a full calcu... View full abstract»

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  • Gap-fill performance and film properties of PMD films for the 65 nm device technology

    Publication Year: 2003, Page(s):435 - 438
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (342 KB)

    A novel high density plasma (HDP) CVD process developed for premetal dielectric applications is presented. The process facilitates void-free gap-fill in high aspect ratio structures, thus addressing one of the main challenges facing premetal dielectric (PMD) technology as device dimensions shrink in the 90 nm and 65 nm technology nodes. The effects of carrier gas composition and plasma characteris... View full abstract»

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  • 300 mm full-factory simulations for 90 nm and 65 nm IC manufacturing

    Publication Year: 2003, Page(s):35 - 38
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (357 KB)

    We present key results of some enabling capabilities realized by the development and implementation of 300 mm full-factory simulation tools supporting Intel's 90 nm high-volume manufacturing (HVM) and 65 nm technology development (TD) factories. We discuss key attributes of these simulators which are being utilized for strategic fab capacity planning, automation systems designs, and tactical execu... View full abstract»

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  • In-situ damascene trench RIE depth monitor using infrared interferometric spectrometry

    Publication Year: 2003, Page(s):362 - 365
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (289 KB)

    In-situ damascene trench RIE depth monitor employing infrared interferometric spectrometry is investigated. Infrared light transmitted through the window of the RIE chamber was incident on the sample, and the trench etch depth of the line and space damascene pattern was calculated from the interferometric spectrum of the lights reflected at the interfaces located above the top wiring layer of the ... View full abstract»

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  • Novel, at-design-rule, via-to-metal overlay metrology for 193 nm lithography

    Publication Year: 2003, Page(s):134 - 137
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (426 KB)

    The effect of scanner aberrations on the pattern placement errors (PPE) in the copper interconnect lithography process is studied both in simulations and experimentally. New grating-based AIM overlay mark enables measuring device feature overlay. It is shown that AIM mark exhibits superior performance over conventional box-in-box (BiB) marks. Comparison between Archer AIM optical and direct CD SEM... View full abstract»

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  • The world's first automated reticle handling system using OHT

    Publication Year: 2003, Page(s):21 - 24
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    The automation of wafer carrier transport in modern semiconductor fabs has progressed, with some 300 mm wafer fabs which are regarded as almost full automation. At the same time, a requirement for the automated reticle transfer system becomes higher in the photolithography step. Recent multiproduct fabs require more frequent reticle exchanges, while it's required that those reticle exchanges are p... View full abstract»

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  • Lost utilization-constraint performance management

    Publication Year: 2003, Page(s):51 - 54
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (386 KB)

    Increasing output at constraint toolsets can increase overall factory output. Although many companies might measures common metrics like utilization, availability, and output at constraints, it is difficult to decipher intelligence. This paper will focus on an indicator that pulls from common metrics to provide insight into constraint operations. By generating this data and applying common problem... View full abstract»

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  • A novel wafer reclaim method for silicon carbide film

    Publication Year: 2003, Page(s):191 - 194
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (365 KB)

    As feature size keeps shrinking down, it is expected that amorphous SiC will replace Si3N4 in the Cu dual-damascene structure soon. SiC is chemically inert and is hard to be etched by wet processing. This property become adverse effect from the wafer reclaiming point of view. In this work, a novel wafer reclaiming method of oxidation followed by HF etching is proposed. Compar... View full abstract»

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  • Megasonic free single wafer ozone jet cleans: concept and feasibility

    Publication Year: 2003, Page(s):233 - 236
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (342 KB)

    A newly developed single wafer ozone cleaning process shows high particle removal performance without the use of megasonics. The process utilizes gaseous ozone stream with diluted HF and NH4OH chemicals to remove wafer particles at room temperature. This new single wafer cleaning process utilizes the strong oxidative properties of ozone with the zeta potential advantages of NH... View full abstract»

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  • Fault detection and classification of plasma CVD tool

    Publication Year: 2003, Page(s):123 - 125
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (272 KB)

    A fault detection and classification (FDC) study by means of principle component analysis (PCA) is conducted on a high density plasma (HDP) chemical vapor deposition (CVD) tool. The design of experiment (DOE) of gas flow and RF power effects is introduced to study the feasibility of PCA for FDC as well as to investigate the correlation of tool parameters. In this study, the first wafer effect of H... View full abstract»

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  • An approach of time-oriented-multiple-objective for production target setting of wafer fabrication

    Publication Year: 2003, Page(s):333 - 336
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB)

    This paper presents a Time-Oriented-Multiple-Objective (TOMO) approach to Production Target Setting system (PTSs) of wafer fabrication (Fab). One approach to determine those weighting of each objective that are based on different production phase. This paper attempts to set specific step target for the production line by taking into account the TOMO approach of each WIP and the available tool capa... View full abstract»

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  • Novel ion implantation method for extending source life with solid source of indium and antimony

    Publication Year: 2003, Page(s):149 - 152
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB)

    InCl3 and Sb2O3 that contain a dopant having a large stopping power than conventional ions are indispensable ion source materials for the fabrication of future high-end ultra large scale integrated circuits (VLSI). However, these materials cause the decline of ion source life due to source filament sputtering during implantation process and it impacts to tool avail... View full abstract»

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  • Elimination of CMP process in BEOL by using Low-k scan planarization

    Publication Year: 2003, Page(s):392 - 395
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (391 KB)

    The improvement of global planarity after the Low-k film formation is indispensable for raise of the yield and reduction of the steps for planarization in dual damascene multilayer interconnection process. We confirmed that scan coating has more excellent uniformity and planarization ability than conventional spin coating. View full abstract»

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  • Electrical characteristics of non-visual defects detected by E-beam inspection

    Publication Year: 2003, Page(s):263 - 266
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (357 KB)

    VC defects detected by e-beam inspection were analyzed in detail. Dark defects were fatal and the root causes easily identifiable. Bright defects were not always fatal and were hard to identify. The electrical characteristics of such defects were measured by electrical probe and small leak currents were observed. These leak levels depend on the voltage applied. We optimized the e-beam inspection c... View full abstract»

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