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Third Annual IEEE Proceedings on ASIC Seminar and Exhibit

17-21 Sept. 1990

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Displaying Results 1 - 25 of 121
  • Proceedings. Third Annual IEEE ASIC Seminar and Exhibit (Cat. No.90TH0303-8)

    Publication Year: 1990
    Request permission for commercial reuse | PDF file iconPDF (10 KB)
    Freely Available from IEEE
  • Elements of VHDL for description of hardware: a tutorial view

    Publication Year: 1990, Page(s):T/7.1 - T/7.9
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1022 KB)

    An introduction to hardware description languages, a discussion of the emergence of VHDL as the standard HDL, and an overview of the VHDL language are given. The constructs of VHDL for design and modeling of hardware are emphasized. An overview of VHDL is given by use of a simple example which is broken into subcomponents, each of which is described at various levels of abstraction. Advanced featu... View full abstract»

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  • Logic synthesis in a CAE design environment - A tutorial

    Publication Year: 1990, Page(s):T/10.1 - T/10.6
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (469 KB)

    Logic synthesis is defined with respect to its input and output, and the flow of data and control in a logic synthesis system is described. Each individual step in such a system is described in detail and the function of each such step is defined. The transformation that the design representation goes through is defined and it is shown how user information and control serves to direct the synthesi... View full abstract»

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  • The realities of ASIC packaging

    Publication Year: 1990
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (45 KB)

    Summary form only given, as follows. ASIC is the technology driver for advanced packaging. This includes high-pin-count surface mount devices, high-performance ceramic packages, tape automated bonding (TAB) packages, and multichip modules (MCM). Emphasis is placed on fine-pitch technology (FPT) and the advantages and limitations of quad flat packs (QFP). Limitations due to power dissipation, abili... View full abstract»

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  • Modeling and simulation methods for mixed signal circuit simulation

    Publication Year: 1990, Page(s):T/14.1 - T/14.5
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (180 KB)

    Summary form only given. Modeling methods that are commonly employed by designers in abstracting mixed signal circuit behavior are discussed. Modeling and overall simulation methods for both analog and digital sections of the circuit that can significantly reduce the total simulation time (CPU and designer) while maintaining acceptable accuracy are also considered.<> View full abstract»

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  • The architecture constraints in test equipment designs

    Publication Year: 1990, Page(s):P4/5.1 - P4/5.4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (300 KB)

    The trends in technology and those issues that might prevent the industrial and defense bases from being successful at an affordable cost are discussed. The deficiencies in current automatic test equipment (ATE) designs are illustrated using the VLSI design and test process as an example. Future test technology requirements and a proposed solution are proposed View full abstract»

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  • Multi circular buffer controller chip for advanced ESM system

    Publication Year: 1990, Page(s):P14/5.1 - P14/5.4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    A 90 K transistor 1.5 μm CMOS integrated circuit that operates at a data transfer rate of 20 MHz and implements an array of variable size circular buffers mapped into a high-speed RAM through physical and virtual addressing techniques is discussed. The device is fully programmable with the capability of single and block data transfers. The target application is an advanced multiprocessor ESM sy... View full abstract»

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  • `VHSIC' technology from a merchant ASIC supplier

    Publication Year: 1990, Page(s):P4/4.1 - P4/4.4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB)

    The definition of very-high-speed integrated circuit (VHSIC) technology has changed over the last several years to encompass an entire system to IC design and manufacturing methodology supporting program lifecycle requirements. As the definition has changed, so has the source of VHSIC technology. It is no longer limited to the original VHSIC contractors. Some of the premier merchant ASIC suppliers... View full abstract»

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  • BiCMOS submicron compiler memories

    Publication Year: 1990, Page(s):P3/3.1 - P3/3.3
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (260 KB)

    An advanced submicron BiCMOS process and an ASIC memory compiler are discussed. The BICMOS process uses bipolar transistors to enhance the fast CMOS transistors by driving heavily loaded nodes at high speeds. The multiple layers of metal in the process significantly increase the gate density available for system-level design View full abstract»

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  • Superintegrated smart access controller

    Publication Year: 1990, Page(s):P2/5.1 - P2/5.4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (244 KB)

    The smart access controller (SAC) integrated circuit is discussed. This chip has been designed to serve serial communication control applications such as terminals, printers, modems, and slave communication processes, for 8, 16- and 32-bit MPU-based systems. Enhancements and cost reductions of existing hardware using Z80/Z180 with Z8530/Z85C30 serial communication controller (SCC) applications are... View full abstract»

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  • An Intel 18253 ASIC chip design

    Publication Year: 1990, Page(s):P14/4.1 - P14/4.4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (292 KB)

    The establishment of the engineering rules to create the executable and synthesizable (and/or testable) specification for an ASIC design in an ASIC CAD environment is discussed. The Intel 8253 programmable timer/counter was selected as a test example to illustrate the strengths and weaknesses of this CAD technology. The need for a high-performance cell-based ASIC/IC CAD system is critical for this... View full abstract»

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  • Systems engineering: a summary of electronics packaging techniques available for present and future systems

    Publication Year: 1990, Page(s):P4/3.1 - P4/3.4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (332 KB)

    The different microelectronics packaging approaches currently available and in development are summarized for system engineers. Some of the important attributes the various approaches are pointed out. Some of the packaging issues a system engineer should consider when attempting to baseline a packaging approach are discussed. Four major categories of advanced packaging techniques are considered. T... View full abstract»

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  • A development system for an SRAM-based user-reprogrammable gate array

    Publication Year: 1990, Page(s):P3/2.1 - P3/2.4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB)

    This tool is applicable to an SRAM-based user-reprogrammable gate array based on a logic block interconnect architecture. An algorithm which led to a powerful design editor with a schematic entry dedicated to this device structure has been developed. It determines minute logics in each block and wiring paths, both automatically and manually. The total system supports hierarchical designs by genera... View full abstract»

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  • GRCA: a global approach for floorplanning synthesis

    Publication Year: 1990, Page(s):P16/5.1 - P16/5.4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (372 KB)

    A global-routing-driven floorplanning technique that is based on a top-down approach is presented. Rectangular cells such as in macrocell design are considered. The topics discussed include: (1) a model for the prediction of shape functions which enables consideration of a more general class of floorplan representations, (2) an improved two-dimensional partitioning procedure, and (3) a dynamic upd... View full abstract»

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  • Putting it all together: using automated techniques for the design and test of large telecommunication devices

    Publication Year: 1990, Page(s):P2/4.1 - P2/4.6
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (468 KB)

    The design process for a large ASIC that will be used in AT&T data transmission systems is described. The design presented many challenges, including a large gate count and a short schedule. The circuitry was difficult to test both for proper functionality and for fault coverage. Many synergistic benefits were realized from the techniques employed in this process, including: (1) a heavy relian... View full abstract»

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  • System designer's realization of a core-based ASIC in a comfortable environment [microcontrollers]

    Publication Year: 1990, Page(s):P14/3.1 - P14/3.2
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (180 KB)

    A case study of the use of ASIC technology by an original equipment manufacturer (OEM) is presented. The development process of a complex ASIC is described. The authors include the reasons for choosing an ASIC approach, the criteria for selecting and ASIC vendor, and the design cycle View full abstract»

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  • Direct access test scheme-implementation and verification in embedded ASIC designs

    Publication Year: 1990, Page(s):P13/1.1 - P13/1.6
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (300 KB)

    The direct access test scheme (DATS) that eliminates the designer's burden of embedded block cell test generation is discussed. This scheme provides for testing of embedded block cells using proven test vectors. The implementation and automatic verification of DATS in ASIC designs is discussed View full abstract»

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  • The microelectronic device selection process

    Publication Year: 1990, Page(s):P4/2.1 - P4/2.4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (356 KB)

    A methodology which has yielded excellent results in identifying critical device needs for complex military systems is described. This methodology is illustrated using examples derived from advanced satellite and other processing system studies. The microelectronic device selection process begins with the identification of mission requirements. The system designer then identifies the system functi... View full abstract»

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  • Testability features in a high-density memory module

    Publication Year: 1990, Page(s):P3/1.1 - P3/1.3
    Cited by:  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (228 KB)

    A configurable multichip memory module designed in silicon-on-silicon hybrid form is discussed. The memory controller IC, which has been implemented in a CMOS gate array, also functions as an in-circuit tester for the memory chips. This capability, supplemented by the controller's own scan-path and boundary-scan features, results in increased in-field testability as well as greatly reduced product... View full abstract»

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  • Cost benefit tradeoffs for ASIC versus programmable logic device

    Publication Year: 1990, Page(s):P1/5.1 - P1/5.4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB)

    Two approaches to the implementation of logic-gate arrays and programmable logic are compared. It is shown that there is a large advantage of using gate arrays instead of programmable logic device field-programmable gate arrays (PLD/FPGAs). The performance of the circuits is dramatically improved in terms of speed, power consumption, reduction in parts cost, and reliability of the circuits. Gate a... View full abstract»

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  • The ideal multiplier compiler

    Publication Year: 1990, Page(s):P16/4.1 - P16/4.4
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (344 KB)

    The ideal multiplier compiler is defined as one which produces a product that achieves high performance and high density and is also portable to different technologies. In addition, such a compiler should support multiple data formats and extend to any data size. It should be reconfigurable and evolvable, and it should incorporate automatic test vector generation (ATVG). The multiplier presented m... View full abstract»

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  • A complete VLSI treatment for the LAPD protocol (ISDN level 2)

    Publication Year: 1990, Page(s):P2/3.1 - P2/3.3
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (236 KB)

    A set of ICs that can execute the bearer functions of one user network in an ISDN has been developed. This set consists of two chips for treatment of the physical layer (layer 1 of the OSI Reference Model) of the S and U interfaces, one chip for terminal adaptation and one chip for treatment of the link layer protocol carried by the D channel, the so called LAPD. The development of two of these ch... View full abstract»

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  • An automated, structured layout methodology for staggered pad, I/O-bound ASIC design

    Publication Year: 1990, Page(s):P11/6.1 - P11/6.4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (340 KB)

    A design methodology developed and implemented for high-pin-count cell-based BiCMOS ASIC designs is discussed. Described is the orchestration of different vendors' CAD tools via tool-specific shell scripts, macros, file reformatting/conversion software and application software to methodically place and route I/O pad cells, I/O circuit cells, and core logic megacells, rapidly completing the correct... View full abstract»

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  • Electronic remote identification-a case study

    Publication Year: 1990, Page(s):P14/2.1 - P14/2.3
    Cited by:  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (356 KB)

    The specification, design, and development of an electronic identification system are discussed. The system has the advantages of long-read-range, orientation-independent, low-cost, passive tags, which are easy to manufacture, require simple installation procedures, and are suitable for use in many countries, over a wide and diverse set of application areas View full abstract»

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  • Automated maintenance of ASIC libraries in a dynamic design environment

    Publication Year: 1990, Page(s):P12/7.1 - P12/7.4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB)

    In order to ensure that simulation libraries are correct and reliable for ASIC design verification, a quality assurance process which is automated and based on a comprehensive test strategy must be in place. Maintenance automation for ASIC libraries provides benefits similar to design automation, namely reduced test and verification times of the libraries, reduced resources, increased productivity... View full abstract»

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