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Third Annual IEEE Proceedings on ASIC Seminar and Exhibit

17-21 Sept. 1990

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  • Proceedings. Third Annual IEEE ASIC Seminar and Exhibit (Cat. No.90TH0303-8)

    Publication Year: 1990
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    Freely Available from IEEE
  • The realities of ASIC packaging

    Publication Year: 1990
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (45 KB)

    Summary form only given, as follows. ASIC is the technology driver for advanced packaging. This includes high-pin-count surface mount devices, high-performance ceramic packages, tape automated bonding (TAB) packages, and multichip modules (MCM). Emphasis is placed on fine-pitch technology (FPT) and the advantages and limitations of quad flat packs (QFP). Limitations due to power dissipation, abili... View full abstract»

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  • Modeling and simulation methods for mixed signal circuit simulation

    Publication Year: 1990, Page(s):T/14.1 - T/14.5
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (180 KB)

    Summary form only given. Modeling methods that are commonly employed by designers in abstracting mixed signal circuit behavior are discussed. Modeling and overall simulation methods for both analog and digital sections of the circuit that can significantly reduce the total simulation time (CPU and designer) while maintaining acceptable accuracy are also considered.<> View full abstract»

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  • Automated maintenance of ASIC libraries in a dynamic design environment

    Publication Year: 1990, Page(s):P12/7.1 - P12/7.4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB)

    In order to ensure that simulation libraries are correct and reliable for ASIC design verification, a quality assurance process which is automated and based on a comprehensive test strategy must be in place. Maintenance automation for ASIC libraries provides benefits similar to design automation, namely reduced test and verification times of the libraries, reduced resources, increased productivity... View full abstract»

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  • ASIC education at Tampere University of Technology

    Publication Year: 1990, Page(s):P10/2.1 - P10/2.4
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (344 KB)

    The ASIC education program at the Tampere University of Technology is discussed. The design tools, educational activities, and foundry services are described. Hardware description languages and system-level simulations are adopted from basic design courses to shift the emphasis in education from layout-level descriptions towards ASIC system oriented designs at undergraduate level. Silicon foundry ... View full abstract»

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  • An economic comparison of telecommunication system design costs utilizing a modular design approach

    Publication Year: 1990, Page(s):P1/2.1 - P1/2.5
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (316 KB)

    A modular ASIC system design approach for telecommunications equipment is compared with system design utilizing conventional ASIC design approaches and standard products. The modular design approach utilizes telecom system blocks (TSBs) which are predesigned and tested telecommunication functions contained in a megacell or netlist format which represent system functions as viewed by the systems de... View full abstract»

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  • Validating an ASIC standard cell library

    Publication Year: 1990, Page(s):P12/6.1 - P12/6.5
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB)

    The accurate validation of the CHMOS III and CHMOS IV cell-based libraries is discussed. The validation methodology consists of library test chips which isolate each cell in a measurable and meaningful circuit. These chips use the customer design, layout, and simulation environment, incorporating all library cells. Manufacturing the test chip wafers across the worst-case process corners further gu... View full abstract»

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  • NetList+: a simple language for fast ASIC prototyping

    Publication Year: 1990, Page(s):P6/7.1 - P6/7.4
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB)

    A simple circuit specification language, NetList+, for rapid turn-around cell-based ASIC prototyping is discussed. By using NetList+, uniform representation is achieved for the specification, simulation, and physical description of a design. The goal is to establish an easy interfacing method between design specification and independent CAD tools so that a simple description ... View full abstract»

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  • Design and test strategy for differential cascode voltage switch circuits

    Publication Year: 1990, Page(s):P9/6.1 - P9/6.4
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (208 KB)

    A test methodology for the differential cascode voltage switch (DCVS) is described. The design methodology of DCVS makes it more testable compared to other technologies. In testing DCVS, a precharge state always precedes a test pattern or a functional pattern. This test methodology permits detection of delay faults and stuck-open faults. The good circuit outputs of a logic tree are orthogonal. A h... View full abstract»

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  • Managing ASIC projects

    Publication Year: 1990, Page(s):P1/1.1 - P1/1.2
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (148 KB)

    The elements of a successful ASIC (application-specific integrated circuit) project, from the front-end development point of view, are discussed. Personnel requirements and training, vendor and tool selection, project specification, and scheduling and budgeting are considered in detail. A successful project requires detailed planning and must be executed with strict management discipline View full abstract»

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  • Economic implications of logic synthesis

    Publication Year: 1990, Page(s):P16/6.1 - P16/6.5
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB)

    An overview of logic synthesis and the different methodologies used in the tools realizing synthesis is presented. The objective is to show the economic implications of synthesis (performance and area of the chip, design time, silicon costs, etc.). The mainstream methodology used in synthesis tools and the possible applications are presented. Future methodologies and some ideas for the reduction o... View full abstract»

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  • Characterizing a cell library using iCCS [ASIC design]

    Publication Year: 1990, Page(s):P12/5.1 - P12/5.4
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (260 KB)

    Maintaining accuracy during the rapid generation of a standard cell library is a problem in ASIC development. Errors can occur in all phases of library generation: design, characterization, modeling, and documentation. The integrated cell characterization system (iCCS), developed to automate the production of a standard cell library, is discussed. ICCS generates accurate models and documentation b... View full abstract»

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  • Quick turn around time ASIC design using KBSC

    Publication Year: 1990, Page(s):P6/6.1 - P6/6.5
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (256 KB)

    A quick turn-around time (QTAT) approach to ASIC design using a rule-based expert system called Knowledge Based Silicon Compiler (KBSC) is described. KBSC provides ASIC designers with an interactive graphic interface for flow chart entry to automatic logic synthesis. KBSC took approximately 1/5 the time required by non-KBSC methods View full abstract»

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  • Synchronous design: the right technique for digital ASICs

    Publication Year: 1990, Page(s):P6/1.1 - P6/1.5
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    The synchronous design methodology for ASIC system design is illustrated. The advantages and disadvantages of this design approach are discussed. The synchronous design style has many advantages over the more popularly used asynchronous style. To be successful in designing high-density ASICs with more than 100 K gates, or high-speed ASICs with system speeds of several hundred MHz, this design appr... View full abstract»

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  • Efficient timing analysis for general synchronous and asynchronous circuits

    Publication Year: 1990, Page(s):P5/4.1 - P5/4.4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (268 KB)

    After partitioning the circuit into a set of clock groups, an event-driven approach is used to find paths with delays greater than a given threshold value. False paths detected during event propagation are reported to the user. In addition to breaking asynchronous loops dynamically, the tool also checks setup/hold time and minimum pulse width violations in a multiple clock environment. Experimenta... View full abstract»

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  • Characterization of ASIC performance via application specific test engineering

    Publication Year: 1990, Page(s):P13/3.1 - P13/3.5
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (256 KB)

    Some of the benefits of customer- and application-specific characterization of ASICs are discussed. The author discusses why ASIC device performance is characterized. An example of characterization data is presented for a CMOS gate array. The benefits of having this data are given. A cost analysis of using contract test engineering services to provide this data is presented View full abstract»

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  • Reliability, testability and yield of majority voting VLSI

    Publication Year: 1990, Page(s):P9/5.1 - P9/5.4
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    Mathematical models for determining the reliability and yield of VLSI designs incorporating majority voting techniques are developed. Significant reliability and yield improvements are predicted and compared to actual VLSI implementations. By satisfying testability conditions, a unified approach to fault and defect tolerance is achieved View full abstract»

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  • Modeling and simulation with Saber

    Publication Year: 1990, Page(s):T/11.1 - T/1111
    Cited by:  Papers (10)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (664 KB)

    The Saber simulator, a comprehensive simulator spanning analog and digital domains and capable or simulating systems described by a mixture of models at the primitive, functional, and behavioral levels is discussed. Saber uses the analog hardware description language MAST to completely divorce the modeling and simulation aspects of creating a practical simulation environment View full abstract»

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  • Third-generation architecture boosts speed and density of field-programmable gate arrays

    Publication Year: 1990, Page(s):P15/6.1 - P15/6.7
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (392 KB)

    A third-generation family of field-programmable gate arrays (FPGAs) that utilizes a combination of architectural and process improvements and features up to twice the density and speed of currently available FPGA devices is discussed. The architecture allows complete and efficient automated design implementation of FPGA-based designs, as well as maximum density and performance. User-configurable o... View full abstract»

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  • Putting the designer in control with desktop prototyping

    Publication Year: 1990, Page(s):T/16.1 - T/16.5
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (344 KB)

    It is pointed out that MAX+PLUS software is the ideal tool to produce a prototype efficiently, completely, and quickly. It provides all necessary prototyping tools in one single system, ensuring that necessary iterations do not slow down the overall prototyping process. Furthermore, the MAX family of EPLDs provides high-density, high-performance devices that integrate general-purpose logic designs... View full abstract»

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  • JTAG and Hitachi's autodiagnosis

    Publication Year: 1990, Page(s):P9/2.1 - P9/2.4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (232 KB)

    The autodiagnosis technique that uses scan design is described and its relation to the IEEE Joint Test Action Group (JTAG) boundary scan is pointed out. The similarities between autodiagnosis and the JTAG boundary scan are emphasized. JTAG and the tradeoffs in such a conversion are discussed View full abstract»

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  • Mixed analog/digital in a mixed bipolar/MOS technology

    Publication Year: 1990, Page(s):P8/4.1 - P8/4.4
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (228 KB)

    SBIMOS tools for mixed analog/digital applications are discussed. This 40-V BiCMOS technology, together with the design system and the libraries, supports the integration of high-performance analog/digital in an ASIC at a low semicustom cost. This is illustrated by showing some standard cells followed by a compiled filter and an integrated circuit View full abstract»

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  • A pipelined ASIC for color matrixing and convolution

    Publication Year: 1990, Page(s):P7/6.1 - P7/6.6
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    A VLSI chip that can perform either 3×3 matrix multiplication or 3×3 digital convolution is discussed. Built-in self-test (BIST) techniques have been incorporated into the chip to ensure high fault coverage. The chip is designed in a 2-μm CMOS technology using a silicon compiler for physical layout. The device is designed to operate at 14.3 MHz, making it suitable for real-time vide... View full abstract»

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  • GRCA: a global approach for floorplanning synthesis

    Publication Year: 1990, Page(s):P16/5.1 - P16/5.4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (372 KB)

    A global-routing-driven floorplanning technique that is based on a top-down approach is presented. Rectangular cells such as in macrocell design are considered. The topics discussed include: (1) a model for the prediction of shape functions which enables consideration of a more general class of floorplan representations, (2) an improved two-dimensional partitioning procedure, and (3) a dynamic upd... View full abstract»

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  • Automatic characterization and modeling [ASIC design]

    Publication Year: 1990, Page(s):P12/4.1 - P12/4.4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB)

    It is shown how an automatic characterization and modeling system called the library compiler reduces library development time, produces a consistent methodology, and increases the accuracy of characterization and modeling. The major characteristics of the system that help produce library development are shown to be automatic input vector generation, process portability, hierarchical parameters, C... View full abstract»

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