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Computer Design, 2003. Proceedings. 21st International Conference on

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Computer Design, 2003. Proceedings. 21st International Conference on

Date 13-15 Oct. 2003

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Title History

Profiling interrupt handler performance through kernel instrumentation

Verification of timed circuits with failure directed abstractions

Multiple fault diagnosis using n-detection tests

Power efficient data cache designs

An efficient VLIW DSP architecture for baseband processing

Paradigm shift for jitter and noise in design and test > Gb/s communication systems (an invited paper for ICCD 2003)

Aggressive test power reduction through test stimuli transformation

Design and performance of compressed interconnects for high performance servers

Charge-recycling voltage domains for energy-efficient low-voltage operation of digital CMOS circuits

A physical design methodology for 1.3 GHz SPARC 64 microprocessor

A Compact model for analysis and design of on-chip power network with decoupling capacitors

A mixed-mode delay-locked-loop architecture

Automatic generation of critical-path tests for a partial-scan microprocessor

On combining pinpoint test set relaxation and run-length codes for reducing test data volume

SCATOMi: scheduling driven circuit partitioning algorithm for multiple FPGAs using time-multiplexed, off-chip, multicasting interconnection architecture

Boolean decomposition based on cyclic chains

Knapbind: an area-efficient binding algorithm for low-leakage datapaths

Cost-efficient memory architecture design of NAND flash memory embedded systems

Power-time tradeoff in test scheduling for SoCs

Dynamic thread resizing for speculative multithreaded processors

ROAD: an order-impervious optimal detailed router for FPGAs

Fully differential receiver chipset for 40 Gb/s applications using GaInAs/InP single heterojunction bipolar transistors

Precomputation-based guarding for dynamic and leakage power reduction

Optimal inductance for on-chip RLC interconnections

Specifying and verifying systems with multiple clocks

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