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Electron Devices Meeting, 1990. IEDM '90. Technical Digest., International

Date 9-12 Dec. 1990

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Displaying Results 1 - 25 of 231
  • A 4 M bit NVRAM technology using a novel stacked capacitor on selectively self-aligned FLOTOX cell structure

    Page(s): 931 - 933
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    A novel stacked capacitor on selective self-aligned FLOTOX (SSSF) cell technology for 4-Mb nonvolatile DRAM (NV-DRAM) is described which enables a nondestructive flash store/recall (DRAM to EEPROM/EEPROM to DRAM) operation that does not disturb the original data in DRAM or EEPROM. The newly developed SSSF cell is fabricated by a triple polysilicon technology and consists of three transistors and one storage capacitor stacked on these transistors. A novel technology for the formation of a self-aligned tunnel region using selective oxide growth on the implanted region is shown together with a new self-aligned DRAM technology for storage node contact to the source. The timing diagrams in store/recall operations are also shown along with the DRAM to EEPROM data transfer characteristics.<> View full abstract»

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  • Low-resistance CVD W plug on Ti silicide for advance CMOS applications

    Page(s): 928 - 930
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    A novel approach is used to form a selective CVD (chemical-vapor-deposited) W plug on a Ti silicide surface by adding a nucleation layer in the contact hole. The technique is called SANIC (self-aligned nucleation layer formation in the contact). The process sequences of SANIC are described and the process latitude of the SANIC technique is examined. The SANIC process has been demonstrated on 1- mu m (drawn) CMOS SRAM and ring oscillators. The CMOS device characteristics and the corresponding gate delays of ring oscillators are shown.<> View full abstract»

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  • Gas flow patterns and thermal uniformity in rapid thermal processing equipment

    Page(s): 921 - 924
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    Two-dimensional simulation of a rapid thermal processing (RTP) reactor is used to determine the radiative heating and the radiative and convective cooling. The gas flow patterns are found to be a strong function of temperature. Edge losses dominate the wafer thermal nonuniformity at high temperature, while convective cooling dominates at low temperature. A peak in the stress is found under transient conditions. To validate the model, some of the results are compared to experimental data from a small custom RTP system.<> View full abstract»

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  • LPCVD profile simulation using a re-emission model

    Page(s): 917 - 920
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    A novel, physically based 3D simulator has been developed that includes the dominant effect of re-emission. This simulator is part of the Stanford Profile Emulator for Etching and Deposition in IC Engineering (SPEEDIE). Unlike previous simulators which consider only the arrival of deposition precursors by unshadowed direct transport and by surface diffusion, SPEEDIE also considers transport into shadowed areas by adsorption and re-emission. The importance of re-emission was established by using overhang test structures to separate the roles of surface diffusion and re-emission. For the depositions investigated (SiO/sub 2/, poly-Si and W) it was found that re-emission dominates over surface diffusion in controlling surface contours. Using the simulator to fit experimental LPCVD (low-pressure chemical vapor deposition) SiO/sub 2/ profiles, it was found that a single constant sticking coefficient model with a cosine re-emission distribution gave excellent fits independent of geometry for a given deposition condition.<> View full abstract»

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  • Optimization and design of plasma etching process utilizing a glow discharge model and a transport model simulation

    Page(s): 913 - 916
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    A glow discharge model and a neutral transport model were developed to optimize and to design the plasma reactors. Simulation was performed for a parallel-plate single-wafer plasma etching reactor. Using the glow discharge model, the distinct features of electronegative discharge compared to electropositive discharge were revealed. In addition, the effect of pressure, interelectrode spacing, RF/DC voltages, and applied frequency on discharge physics was investigated. The neutral transport model was utilized to study etching rate and uniformity as a function of reactor geometry and operating conditions. Model predictions showed good agreement with experimental results obtained using optical emission spectroscopy. Two novel reactor designs were proposed to improve the reactor performance. These include a graded gas velocity at the reactor inlet and a plasma-impulse mode of operation.<> View full abstract»

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  • Physically-based models of alignment schemes in commercial steppers

    Page(s): 909 - 912
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    Optical alignment between reticle and wafer in photolithography processes has become one of the limiting factors for achieving submicron design rules. Various alignment schemes have been designed by stepper vendors to overcome the problem. Physically based models have been developed to simulate the images of the wafer alignment mark detected by these alignment schemes. The alignment schemes that can be modeled are the Ultratech key-target convolution scheme, the Censor and Hitachi bright field scheme, the GCA dark field scheme, the Canon dark field scheme, and the ASM moire interference scheme. Together with other metrology schemes, these alignment schemes have been implemented into a software tool, METRO, to facilitate the simulation task.<> View full abstract»

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  • New topography expression model and 3D topography simulation of Al sputter deposition, etching, and photolithography

    Page(s): 905 - 908
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    It is shown that the material surface can be described by the constant concentration area (the contour surface), by using the continuity principle at the material surface and considering the essential property of the material surface. Based on this model and the conservation of mass, the authors present a simulation algorithm and develop a 3D topography simulator (3D MULSS: Three-Dimensional Multi Layer Shape Simulator). It is demonstrated that this simulator can simulate the coverage of Al sputter deposition accurately, by comparing simulations and experimental results. 3D MULSS can also simulate the sequential processes of deposition, etching, and photolithography in three dimensions. In addition, it is shown that the proposed model can be applied to the surface tension by the 2D simulation of reflow.<> View full abstract»

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  • Submillimeter backward-wave oscillator

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    Lewis Research Center is conducting a program to develop a series of backward-wave oscillators (BWOs) for use as voltage tunable local oscillators in spectrometers deployed above the Earth's atmosphere. The project goal is to produce an oscillator with an operating frequency of 2 THz. The BWO program has produced a number of successful design innovations. These include a microfabricated circuit on a diamond substrate, an optical output coupler, and a high-impedance slow wave structure. Experiments being conducted on the BWO are briefly described.<> View full abstract»

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  • A submillimetre wave extended interaction oscillator with novel broadband mechanical tuning

    Page(s): 897 - 900
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    A novel method for tuning an extended interaction oscillator cavity by separation of the cavity halves is described. This method has been devised by the European Space Agency in response to a foreseen requirement for a submillimeter power source where submillimeter manufacturing techniques would have to be used. The method, which is equally applicable to all frequency bands, is described, and full details of cold test results clearly demonstrating the feasibility of the device are given.<> View full abstract»

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  • The Emission Gated Device Experiment

    Page(s): 893 - 896
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    The Emission Gated Device Experiment has been constructed to observe a prebunched electron beam in a traveling wave circuit. The objective of this study is to define the efficiency, bandwidth, and high-frequency performance of emission gated devices for potential applications in radar, electronic warfare, and neutral particle beam accelerators. With tight bunches injected into an undriven helix one wavelength long, an efficiency of 6% and a gain of 10 dB have been observed. Experimental results and simulations are compared with a view to understanding the dynamics of the bunched beam in the circuit fields. Tight bunching and high average current are shown to be the strongest contributors to high efficiency; therefore, a practical device requires a very high gain input circuit.<> View full abstract»

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  • Design of an 850-MHz klystrode

    Page(s): 889 - 892
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    The klystrode is a compact, highly efficient microwave source which has been proposed for application in the neutral particle beam program. As part of the klystrode design effort, extensive use is being made of computational methods, including MAGIC, an electromagnetic particle-in-cell code. The authors describe several ongoing calculations on klystrode efficiency, in particular on the design of the input cavity circuit and the use of double buncher cavities to improve beam bunching.<> View full abstract»

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  • Modification of klystron beam loading by initial velocity modulation of the beam

    Page(s): 885 - 888
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    The authors discuss the correction of klystron cavity beam-loading formulas for the effect of velocity modulation on the beam. These effects were small for older klystrons, in which the quarter-plasma-wavelength spacing minimized the velocity modulation at each gap. It is noted that they appear to be significant for recent designs using larger numbers of cavities with irregular spacings. Accurate formulas are given for the transit time and exit velocity of individual particles, and analytic solutions are presented which appear to have some merit but are incomplete.<> View full abstract»

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  • Development of an 800 W Ka-band, ring-bar TWT

    Page(s): 881 - 884
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    A detailed description of the ring-bar design is presented along with the RF performance data on one of the development tubes. Performance tests have demonstrated in excess of 700 W at 31 GHz. The tube features periodic permanent magnet (PPM) focusing, conduction cooling, and a nonintercepting gridded gun design. Helix derived circuits such as the ring-bar circuit offer several advantages over traditional helix circuits, including higher power levels, higher efficiencies, and improved thermal capabilities while maintaining equivalent costs. This development program is directed toward a 800-W tube operating at 35 GHz, at duties up to 30%.<> View full abstract»

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  • 2.5 dimensional time domain particle-in-cell simulation code for collection design

    Page(s): 877 - 880
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    A 2.5-dimensional time-domain particle-in-cell simulation code for traveling-wave-tube collectors is presented. The code integrates various features of collector design, including depressed electrode configurations, external magnetic fields, and time-varying input electron distribution. This enables the user to change various tube parameters and observe the effect on collector efficiency nand thermal load. Among those parameters which are variable are depressed electrode voltages, geometry, magnetic field strength, and RF power. Numerical calculations have been made for two different types of collectors: a single-stage depressed collector which is used on the TMEC microtube, and a two-stage collector used on a 600-W Ku-band communication tube.<> View full abstract»

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  • Development of sidebands in ultra high power traveling wave tube amplifiers

    Page(s): 873 - 876
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    Results are presented from recent research on the development of high-efficiency, high-power traveling-wave-tube amplifiers (TWTAs). A rippled wall TWTA is used as the slow-wave structure for wave interactions with an 850 keV, 1 kA, 100 ns duration electron beam. The output power of the tube is in excess of 400 MW at 8.76 GHz, corresponding to an electron beam to microwave energy conversion efficiency of 48%. At high output power levels (>100 MW), sidebands are observed to develop which carry an increasing fraction of the output signal as the beam current is increased. The sidebands are asymmetrically located with respect to the center frequency of the amplifier and do not appear to be associated with trapped particles. It is postulated that the sidebands result from finite length effects in the short amplifier sections used.<> View full abstract»

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  • Mechanism and device-to-device variation of leakage current in polysilicon thin film transistors

    Page(s): 867 - 870
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    An experimental study of mechanisms responsible for off-stage leakage currents in n- and p-channel poly-TFTs (thin-film transistors) is presented. Unlike turn-on characteristics, leakage currents are not symmetrical with respect to source-drain voltage polarity. The conduction mechanism in the off-state is consistent with the model of thermionic-field emission near the drain. The spatial and energetic distribution of trap-states in the drain depletion region affects the tunneling probability and causes device-to-device variation and the asymmetry in leakage current. The temperature dependence of the leakage current arises from the thermally activated carrier population at the energy state of the maximum tunneling probability. Cumulative leakage currents follow a Poisson-type log-normal distribution which can be significantly affected by processing control. Less than 10-fA/ mu m TFT width in leakage current and more than nine orders of magnitude on/off current ratio at 10-V drain bias were achieved in n-channel poly-TFTs.<> View full abstract»

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  • Evaluation of polycrystalline silicon thin film transistors with the charge pumping technique

    Page(s): 863 - 866
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    Poly-Si TFT (thin-film transistor) characteristics are evaluated by using the charge pumping technique. The generation-recombination current at the grain boundary (GB) traps is measured as the charge pumping current. Therefore, the influence of the GB traps is directly evaluated. It is confirmed that a large number of donorlike and acceptorlike traps exist at the GBs in poly-Si TFTs. The trap density is derived from the pulse frequency and pulse risetime dependence of the charge pumping current. It is observed that there is a direct correlation between the field-effect mobility and the charge pumping current. The influence of device type and process temperature on trap properties is examined using the charge pumping technique. Furthermore, the device characteristic degradation after hot carrier stress is evaluated using this technique.<> View full abstract»

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  • Two-dimensional device simulation for avalanche induced short channel effect in poly-Si TFT

    Page(s): 859 - 862
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    A novel two-dimensional device simulator for poly-Si TFTs (thin-film transistors) is developed, in which the effects of grain boundaries (GBs) are incorporated into the carrier mobility model. In this simulator, the basic semiconductor equations are iteratively solved in combination with the carrier generation/recombination model, which consists of avalanche, S-R-H, and Auger processes. By using this simulator, the effects of GBs on device characteristics are accurately evaluated. In addition, the avalanche-induced short channel effect in poly-Si TFTs is numerically analyzed.<> View full abstract»

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  • Modeling and parameter extraction of amorphous silicon thin-film-transistors for active-matrix liquid-crystal displays

    Page(s): 855 - 858
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    An analytical model for the series resistors is derived based on two-dimensional current flow in the source/drain regions. This model accounts for effects of band-tail states on channel conduction, finite overlap of the gate to source and drain, and combined contact resistivity of the intrinsic and n/sup +/ a-Si films. Coupling this model with a consistent model for the intrinsic TFT (thin-film transistor) yields a complete description of the staggered TFT at low drain-to-source voltage, and this model has been used to extract key device parameters for a-Si TFTs.<> View full abstract»

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  • A new a-Si TFT with Al/sub 2/O/sub 3//SiN double-layered gate insulator for 10.4-inch diagonal multicolor display

    Page(s): 851 - 854
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    A novel a-Si TFT (thin film transistor) with an Al gate electrode and an Al/sub 2/O/sub 3//SiN double-layered gate insulator has been developed and successfully applied to a 10.4-in diagonal multicolor display panel. Al is a low resistivity metal and it is also possible to form Al/sub 2/O/sub 3/ by anodic oxidation. These features contribute greatly to decreasing the number of defects in the panel and are indispensable for manufacturing a large-size display. The Al, which is used as a gate electrode, can also be used as a gate bus-line metal. As a result, the gate bus-line resistance of the panel can be reduced to about 2 k Omega , which is quite effective for improving the image quality of the panel.<> View full abstract»

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  • A high-reliability, low-operation-voltage monolithic active-matrix LCD by using advanced solid-phase-growth technique

    Page(s): 847 - 850
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    A highly reliable poly-Si thin-film transistor (TFT) integrated driver circuit for a monolithic active-matrix LCD (liquid crystal display) panel has been developed. The lifetime of the present driver circuit has been improved to be much longer than that of the conventional driver circuits as a result of the decrease of the supply voltage from 16 V to 8.2 V. This decrease of operation voltage has been attained by the increase of the field effect mobilities to 130 cm/sup 2//V-s for n-channel TFTs and 70 cm/sup 2//V-s for p-channel TFTs by enlarging the grain size of the poly-Si film to 5 mu m. This enlargement of grain size has been achieved by a solid-phase growth technique using a low-temperature LPCVD (low-pressure chemical vapor deposition) method with Si/sub 2/H/sub 6/ source gas.<> View full abstract»

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  • Active matrix liquid crystal display design using low and high temperature processed polysilicon TFTs

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    The authors compare polysilicon n- and p-channel thin-film transistors (TFTs) which have been fabricated using either a low-temperature (> View full abstract»

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  • Deep submicron nitrided-oxide CMOS technology for 3.3-V operation

    Page(s): 837 - 840
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    Deep-submicron CMOSFETs with ONO (reoxidized nitrided oxide) gate dielectrics have been demonstrated to satisfy 3.3-V operation, contrary to conventional SiO/sub 2/ FETs. The 1.4- mu m ONO CMOS devices achieve (1) an improved saturation transconductance g/sub m/ of 250 mu S/ mu m for n-FETs together with acceptably small degradation in p-FET g/sub m/, resulting in an excellent CMOS gate delay time of 55 ps/stage (comparable or superior to the device/circuit performance of SiO/sub 2/ FETs) and (2) device lifetimes improved by approximately 100 times to exceed 10 years with respect to both ON- and OFF-state hot-carried reliability for n-FETs as well as TDDB together with unchanged p-FET hot-carrier reliability, all under 3.3-V operation.<> View full abstract»

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  • Drain structure optimization for highly reliable deep submicron nMOSFETs with 3.3 V high performance operation

    Page(s): 833 - 836
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    A guideline for optimization of the n/sup -/ fully gate overlapped structure (FOLD) has been established. Its reliability and performance were investigated in comparison with optimized LDD (lightly doped drain) structure (op.LDD). It is found that the superiority in reliability for the two structures is reversed below 3.5 V, and the optimized FOLD structure (op.FOLD) has higher reliability than the op.LDD structure. This is due to a discrepancy between peak electric field and current flow caused by high controllability of the gate electrode of the FOLD structure at the n/sup -/ extension region. The op.FOLD structure achieves high performance on the trend at 3.3 V, in spite of nonscaled gate oxide thickness (11 nm), which results from TDDB limitation for 3.3 V operation.<> View full abstract»

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  • Self-aligned silicided inverse-T gate LDD devices for sub-half micron CMOS technology

    Page(s): 829 - 832
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    A nitride-sealed L-shaped Si spacer technique is used to form inverse-T gate sub-half micron N- and P-LDD (lightly doped drain) device structures with self-aligned Ti silicided gate and source-drain. The advantage of the L-shaped Si spacer N-LDD devices over the L-shaped nitride spacer devices is to extend the gate electrode so that it fully overlaps the N/sup +/ S/D region, which provides (1) higher current drive due to a reduction of series resistance with an increased carrier concentration at the LDD region and (2) less degradation during hot carrier aging due to a reduction of maximum lateral electric field and greater tolerance to higher trapped charges.<> View full abstract»

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