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Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,

25-28 Sept. 1989

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  • Proceedings: The Second Annual IEEE ASIC Seminar and Exhibit (Cat. No.89TH0280-8)

    Publication Year: 1989
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    Freely Available from IEEE
  • A university flexible technology foundry for VLSI application specific integrated circuits

    Publication Year: 1989, Page(s):P14 - 2/1-4
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (324 KB)

    The Rochester Institute of Technology has established a factory operation within its cleanroom facility. The factory coexists with class laboratory instruction and research. About one lot per week is released into the factory, and processing is completed automatically by paid student operators several weeks later. The customers for the factory are students and faculty involved in VLSI design cours... View full abstract»

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  • BiCMOS ASICs: technology and applications

    Publication Year: 1989, Page(s):T6 - T0
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (28 KB)

    Summary form only given. An overview is presented of BiCMOS ASIC (application-specific integrated circuit) technology and applications. This covers device design, technology, gate array applications, standard cell applications, and system implications. A survey is conducted of current BiCMOS ASIC products. This presentation will address all current products by vendor, and by product types. It prov... View full abstract»

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  • Creation of an undergraduate curriculum in ASIC design

    Publication Year: 1989, Page(s):P14 - 1/1-4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (220 KB)

    A VLSI program at the University of Hawaii initiated in 1987 is discussed. Since this time, the curriculum has been expanded to offer undergraduate classes in analog and digital VLSI design. The expansion and development of this new curriculum are described View full abstract»

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  • Fault simulation basics

    Publication Year: 1989, Page(s):T5 - 1/1-9
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (660 KB)

    A description is given of the principles of fault simulation, fault modeling techniques and the economic benefits of fault simulation. The principles of fault simulation are discussed, including serial, parallel, and concurrent fault simulation algorithms. Digital faults, fault coverage, and fault mechanisms typically found in digital circuits are described. The tradeoffs of fault placement, fault... View full abstract»

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  • The integration of power supply components within standard cell integration circuits

    Publication Year: 1989, Page(s):P13 - 5/1-4
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (268 KB)

    The authors present aspects of the design of three standard-cell ASICs (application-specific integrated circuits). Each ASIC had an unusual power supply and I/O level requirement determined by its operating environment. The designs were completed using a highly automated procedure which included combining cells from Sierra's 1.5-μm standard cell library with a few additional custom cells. The c... View full abstract»

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  • A network access interface ASIC for a cross-connect system

    Publication Year: 1989, Page(s):P8 - 2/1-4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (380 KB)

    The Alcatel Bell methodology for ASIC (application-specific integrated circuit) design is presented, showing the feasibility of a high degree of circuit reusability. The methodology is supported by a proprietary integrated ASIC CAD system, providing access to libraries and technologies of various ASIC vendors. A considerable reduction in design effort is gained due to reusing and/or adapting compo... View full abstract»

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  • Ground bounce in CMOS ASICs

    Publication Year: 1989, Page(s):P9 - 4/1-4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB)

    A study has been undertaken to investigate the ground bounce phenomena in CMOS ASICs (application-specific integrated circuits). A simple mathematical analysis was performed to help gain an intuitive understanding of the problem. SPICE simulations were then performed to build a more detailed model. The SPICE model allowed different problem solving approaches to be compared in a straightforward man... View full abstract»

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  • Mixed signal ASIC design issues and methodologies

    Publication Year: 1989, Page(s):T4 - 1/1-9
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (844 KB)

    A broad overview is presented of the major design issues related to creating mixed analog/digital application-specific integrated circuits (ASICs). This subject is discussed from the perspective of a potential customer or designer by outlining the design decisions, limitations, tradeoffs and requirements he or she will face during the course of a mixed signal ASIC project. The major technical issu... View full abstract»

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  • Predictive analysis of sensitivity to chip-routing parasitics

    Publication Year: 1989, Page(s):P13 - 4/1-4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (256 KB)

    The authors describe a system which is able automatically to bring to the attention of the designer significant performance sensitivities which are introduced through interconnection parasitics. The input to the tool is a SPICE file and a performance specification provided by a designer. The output is again a SPICE file, but augmented with those interconnection parasitics which are most significan... View full abstract»

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  • Case study: an NTSC imaging system timing gate array design

    Publication Year: 1989, Page(s):P8 - 1/1-4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (372 KB)

    A case study of the design of a timing generator ASIC (application-specific integrated circuit) for an NTSC-compatible imaging system is presented. The case history includes many of the classic problems in this type of design. Consideration is given to the problems of changing specifications during the design process, adding special functionality while minimizing testability enhancements, the pres... View full abstract»

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  • Incremental netlist compilation for IKOS hardware logic simulator

    Publication Year: 1989, Page(s):P9 - 3/1-4
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (260 KB)

    Incremental compilation is desirable to avoid recompiling a large network when only a few modules are modified. An algorithm that partitions a network in a hierarchical manner is described. The linker links together separately compiled or linked modules to generate machine codes for the IKOS hardware simulator. The machine codes generated for the duplicate subnetworks (or logic blocks) need not be... View full abstract»

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  • Introduction to CMOS analog standard cell ASIC design

    Publication Year: 1989, Page(s):T2 - 1/1-4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (224 KB)

    This study is directed toward the mixed-signal ASIC (application-specific integrated circuit) system designer. The demand for mixed signal ASIC products continues to grow and places increased importance on reducing the design cycle time for the analog section of the chip. Modern generic digital CMOS technology is examined for use in analog integrated circuit design. Analog standard cells and desig... View full abstract»

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  • Composite device model enhances worst case simulation of bipolar analog ASICs

    Publication Year: 1989, Page(s):P13 - 3/1-3
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (212 KB)

    It is shown that practical simulations of worst-case performance of analog ASIC (application-specific integrated circuit) designs are enhanced by the use of a composite device model containing low, typical, and high sets of parameters. The composite model allows process related parameters, mismatch effects, and correlation between parameters to be included in single sets of simulations using sensi... View full abstract»

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  • A 25 MOPS systolic integer divider IC

    Publication Year: 1989, Page(s):P7 - 4/1-3
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (180 KB)

    The divide function in signal processing systems is, in many instances, unavoidable, particularly when implementing range scaling, matrix operations, or perspective transforms, in system applications such as workstations, radar systems, and image processors. Traditionally this need has been fulfilled at the expense of reduced system speed and efficiency by relying on converging recursive technique... View full abstract»

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  • Perspective on BiCMOS

    Publication Year: 1989, Page(s):P1 - 2/1-4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (152 KB)

    The objective of Hi-BiCMOS is to combine speed performance approaching that of ECL and integration density approaching that of CMOS. A high-performance 1.3-μm BiCMOS technology and its applications to ASICs (application-specific integrated circuits) are described. This Hi-BiCMOS gate array contains 3072 gates and 90 input/output buffers. The inclusion of bipolar transistors enables this array t... View full abstract»

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  • A 1.3 μm BiCMOS gate array with configurable on-chip 3-port RAM

    Publication Year: 1989, Page(s):P3 - 4/1-4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (176 KB)

    A 10 K-gate BiCMOS gate array with a configurable 4.6-kb SRAM (static RAM) has been developed using a 1.3-μm technology. The propagation delay time of a two-input NAND is 0.45 ns at 0.6-pF load. The on-chip memory can be configured as ×9, ×18, ×36 b. A description is given of the device structure, the basic cell design, the memory configuration, and the performance of this mem... View full abstract»

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  • High density and high performance ECL: some design tips

    Publication Year: 1989, Page(s):T9 - 1/4-6
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (232 KB)

    Recent developments in ECL (emitter-coupled logic) circuit technology have led to a new generation of high-density and higher-performance gate arrays. The choice of an ECL ASIC (application-specific integrated circuit) technology is discussed with regard to the use of proven versus new technology, ASIC benchmarks, and second sourcing. Design issues considered are the optimization of density and pe... View full abstract»

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  • Fault grading, a measure of logic simulation integrity

    Publication Year: 1989, Page(s):P9 - 2/1-4
    Cited by:  Papers (1)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    It is argued that although fault grading is generally used as a measure of the completeness of the test program, it has an even greater potential in measuring the integrity of the functional analysis as performed by the logic simulation. A brief description of stuck-at-1 and stuck-at-0 fault simulation is given. Fault simulation is contrasted with the typical controllability and observability meas... View full abstract»

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  • ASIC design for testability

    Publication Year: 1989, Page(s):T1 - 1/1-10
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (652 KB)

    Advanced testability techniques are described for ASIC (application-specific integrated circuit) design. BIST (built-in self-test), scan test, boundary scan, embedded cores, and mixed-signal circuitry are among the topics discussed. A CAE methodology and a specific case study are analyzed for each ASIC design choice. Emphasis is on modular design for test, automated testability analyses, and compr... View full abstract»

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  • An analog module generator that includes operational sensitivities

    Publication Year: 1989, Page(s):P13 - 2/1-4
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (372 KB)

    The stringent requirement of precision in the design of analog integrated circuit layout for correct functionality and reasonable performance warrant the use of parameterized module generators. A methodology for the design of a module generator is developed which outputs the mask-level topological description of the layout of the specified analog circuit and a (circuit-level) simulation model that... View full abstract»

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  • Design test-flexible, efficient, and thorough solutions to overcome simulation-to-test roadblocks

    Publication Year: 1989, Page(s):P4 - 2/1-4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    Provided with the proper tools, the ASIC (application-specific integrated circuit) designer can thoroughly address ASIC verification at points early in the design cycle. The capabilities of this type of verification tool set are presented, including an efficient high-level simulation language, software verification of the intended design function, and thorough emulation of tester environments. The... View full abstract»

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  • ASIC design of digital ECG filter

    Publication Year: 1989, Page(s):P7 - 3/1-4
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (296 KB)

    An ASIC (application-specific integrated circuit) design for a linear-phase ECG (electrocardiogram) filter is presented. The filter utilizes a novel recursive multiplierless architecture. A bit-serial approach has been chosen to keep circuit area and power consumption as small as possible. The implementation has been done using partly full custom and partly standard cell techniques, yielding high ... View full abstract»

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  • Trends in ECL array technology

    Publication Year: 1989, Page(s):P1 - 1/1-4
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB)

    Trends for future ECL (emitter-coupled logic) gate-array circuits and the technology developments needed to support new products are described. Trends are determined by analyzing product life cycles together with active process development and circuit design research projects. Subjects covered include projected logic densities, array architectures, performance levels, power handling, and memory re... View full abstract»

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  • A single-polysilicon flip-flop EEPROM for ASIC application

    Publication Year: 1989, Page(s):P3 - 3/1-4
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (176 KB)

    A single-polysilicon flip-flop EEPROM has been developed. A single-polysilicon structure which is suitable for ASIC (application-specific integrated circuit) application and a flip-flop-type cell give an endurance of more than 1,000,000 cycles. With this technology, a one-chip computer with CPU, RAM, ROM, some I/O ports, and EEPROM has been fabricated View full abstract»

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