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ASIC Seminar and Exhibit, 1989. Proceedings., Second Annual IEEE

Date 25-28 Sept. 1989

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  • Proceedings: The Second Annual IEEE ASIC Seminar and Exhibit (Cat. No.89TH0280-8)

    Publication Year: 1989
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  • Predicting and scaling power consumption in CMOS ASICs

    Publication Year: 1989 , Page(s): P8 - 6/1-4
    Cited by:  Papers (2)
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    CMOS ASIC (application-specific integrated circuit) devices are known for their low power consumption, but with the increased complexity and high pin counts of today's chips, even CMOS devices consume large amounts of power. The fundamentals of power consumption in CMOS ASICs and the many problems associated with predicting it are discussed. Both internal and external power are examined, as well as the effects of scaling View full abstract»

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  • Zygen timing model generator

    Publication Year: 1989 , Page(s): P12 - 5/1-5
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    A description is given of the Zygen timing model generator tool, which provides engineers with a method for producing gate-level timing models more accurately and more quickly than by using hand calculations. The problem of assigning delays through multiple delay paths ranges from a trivial to a very complex task. The complexity arises when timing paths are reconvergent, overlapping, subdivided by nonoverlapping clocks, or when the model contains simulator-specific functions for which timings cannot be easily mapped. Zygen overcomes this complexity by employing the Zycad Magnum II hardware accelerator, Intel's reference simulator, in determining valid data paths throughout the model. In addition, it employs the power of the Simplex algorithm in solving the system of linear timing equations. A description of the algorithm and capabilities of Zygen is presented with two examples of how Zygen solved the timing problem View full abstract»

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  • Composite device model enhances worst case simulation of bipolar analog ASICs

    Publication Year: 1989 , Page(s): P13 - 3/1-3
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    It is shown that practical simulations of worst-case performance of analog ASIC (application-specific integrated circuit) designs are enhanced by the use of a composite device model containing low, typical, and high sets of parameters. The composite model allows process related parameters, mismatch effects, and correlation between parameters to be included in single sets of simulations using sensitivity and Monte Carlo techniques. Results of these simulations provide the designer with design optimization data, sensitivity, test limits, and yield data View full abstract»

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  • Predictive analysis of sensitivity to chip-routing parasitics

    Publication Year: 1989 , Page(s): P13 - 4/1-4
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    The authors describe a system which is able automatically to bring to the attention of the designer significant performance sensitivities which are introduced through interconnection parasitics. The input to the tool is a SPICE file and a performance specification provided by a designer. The output is again a SPICE file, but augmented with those interconnection parasitics which are most significant for the performance specification prescribed by the designer. The value attached to a parasitic is a quantitative estimate of how significant the parasitic is. This information is derived from a simulation of the circuit prior to layout. The list of most significant routing parasitics could be used to provide feedback to a human designer, direct an automatic layout tool, or guide a circuit extractor View full abstract»

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  • High performance CMOS dual-port SRAM compiler

    Publication Year: 1989 , Page(s): P3 - 2/1-4
    Cited by:  Papers (3)
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    A high-density, high-performance dual-port SRAM (static RAM) compiler has been developed with standard product features. The compiler can generate different SRAM configurations with a minimum of 512 bits up to a maximum of 9 kbits. The SRAM has a typical access time of 15 ns (1.5-μm ASIC (application-specific integrated circuit) process) for the largest configuration (1 K words×9 bits or 512 words×18 bits). It is scalable to a 1-μm ASIC process with a typical access time of 9 ns. The compiler takes only five min to generate a complete layout block, a transistor netlist, or a gate-level model netlist for any SRAM configuration View full abstract»

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  • Trends in ECL array technology

    Publication Year: 1989 , Page(s): P1 - 1/1-4
    Cited by:  Papers (2)
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    Trends for future ECL (emitter-coupled logic) gate-array circuits and the technology developments needed to support new products are described. Trends are determined by analyzing product life cycles together with active process development and circuit design research projects. Subjects covered include projected logic densities, array architectures, performance levels, power handling, and memory requirements. Developments are underway in all these areas to keep ECL the technology of choice for high-performance system design View full abstract»

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  • A single-polysilicon flip-flop EEPROM for ASIC application

    Publication Year: 1989 , Page(s): P3 - 3/1-4
    Cited by:  Patents (1)
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    A single-polysilicon flip-flop EEPROM has been developed. A single-polysilicon structure which is suitable for ASIC (application-specific integrated circuit) application and a flip-flop-type cell give an endurance of more than 1,000,000 cycles. With this technology, a one-chip computer with CPU, RAM, ROM, some I/O ports, and EEPROM has been fabricated View full abstract»

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  • An integrated circuit for texture distance computation

    Publication Year: 1989 , Page(s): P8 - 4/1-6
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    A systolic-array-based architecture for texture distance computation is presented. Texture information is extracted and then represented as a set of histograms for various texture features. On the basis of this representation and the concept of event set distance, a transportation-like simplex algorithm is used to compute the texture distances between pairs of textures. Using this algorithm, the texture matching process is reduced to finding a solution to the streamlined transportation simplex problem. The solution to this problem requires two algorithms. The first algorithm is used to obtain the initial basic feasible solution (IBFS) based on Russel's approximation. The second algorithm tests the optimality of the computed IBFS. The authors also present the design and implementation of a prototype VLSI chip which maps the systolic implementation of the two algorithms onto silicon View full abstract»

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  • Perspective on BiCMOS

    Publication Year: 1989 , Page(s): P1 - 2/1-4
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    The objective of Hi-BiCMOS is to combine speed performance approaching that of ECL and integration density approaching that of CMOS. A high-performance 1.3-μm BiCMOS technology and its applications to ASICs (application-specific integrated circuits) are described. This Hi-BiCMOS gate array contains 3072 gates and 90 input/output buffers. The inclusion of bipolar transistors enables this array to support both TTL (transistor-transistor logic) and ECL logic interfaces. A Hi-BiCMOS memory-plus-logic gate array has also been fabricated using a 1.3-μm drawn two-layer metal silicon gate process technology. It contains approximately 10 K logic gates, 4.6 kb of triple port RAM, and 220 input/output buffers. A Hi-BiCMOS standard cell library has been developed to improve design productivity in microprocessor designs. Megacells such as ALUs, registers, ROMs, RAMs, multipliers and other macrofunctions are available as part of the macro library View full abstract»

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  • A CMOS micropower heart rate indicator

    Publication Year: 1989 , Page(s): P10 - 4/1-6
    Cited by:  Papers (4)
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    The aim of this work is to develop a micropower heart rate indicator integrated with CMOS technology. The implementation will use several micropower blocks, such as a continuous-time DC-compensated gain stage, an antialias filter, a switched-capacitor bandpass filter, and a QRS detector which consists of several nonlinear stages. So far, two types of experimental micropower amplifiers and the complete DC compensated preamplifier have been designed and tested for the heart rate indicator. In general, the test results show good agreement with the simulations. The differences between the measurement results and simulations are discussed View full abstract»

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  • Application-specific array processors

    Publication Year: 1989 , Page(s): T8 - 1/1-6
    Cited by:  Patents (1)
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    An application-specific array processor (ASAP) means a high-speed, application-driven, massively parallel, modular, and programmable computing system. The ever-increasing super-high-speed requirement (in giga/tera FLOPS) in modern engineering applications suggests that mainframe scientific computers will not be adequate for many real-time signal/image processing and scientific computing applications. Therefore, the new trend of real-time computing systems points to special-purpose parallel processors, whose architecture is dictated by the very rich underlying algorithmic structures and therefore optimized for high-speed processing of large arrays of data. It is also recognized that a fast-turnaround design environment will be in a great demand for such parallel processing systems. This has become more realistic and more compelling with the increasingly mature VLSI and CAD technology. Therefore, a major advance in the state of the art in the next decade or so is expected. How to effectively design an application-specific parallel processing system which leads to a fast-turnaround design methodology is discussed View full abstract»

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  • PIMM1, an image processing ASIC based on mathematical morphology

    Publication Year: 1989 , Page(s): P7 - 1/1-4
    Cited by:  Papers (2)
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    To meet image analysis requirements in terms of processing speed and computing capacities, the authors have developed an ASIC (application-specific integrated circuit) with a programmable architecture, supporting the latest algorithms of mathematical morphology. Designed in 1.5-μm CMOS technology, the ASIC can process 8-b images at a 20-MHz pixel frequency, in pipeline or in parallel. The architecture of PIMM1 is discussed, along with two multiprocessor organizations View full abstract»

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  • Custom cell development for standard cell designs

    Publication Year: 1989 , Page(s): P11 - 4/1-3
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    The ASIC (application-specific integrated circuit) designer often searches through various ASIC databooks trying to locate a cell that the design requires. If it is not possible to find the cell needed, the designer either changes the design so it can be implemented using cells that are available or requests the development of a custom cell from the ASIC supplier. A discussion is presented of custom cell development considerations for standard cell designs. The benefits and risks of custom cell development are examined, and recommendations for minimizing the risks are made View full abstract»

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  • Ground bounce in CMOS ASICs

    Publication Year: 1989 , Page(s): P9 - 4/1-4
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    A study has been undertaken to investigate the ground bounce phenomena in CMOS ASICs (application-specific integrated circuits). A simple mathematical analysis was performed to help gain an intuitive understanding of the problem. SPICE simulations were then performed to build a more detailed model. The SPICE model allowed different problem solving approaches to be compared in a straightforward manner. Laboratory experiments were performed to confirm the validity of the simulation and mathematical analyses. The results indicate that there are effective measures which can be taken to reduce the magnitude of voltage transients induced by the device and to minimize the device's sensitivity to ground bounce View full abstract»

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  • Custom RISC has international applications

    Publication Year: 1989 , Page(s): P5 - 5/1-4
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    The authors describe the VL86C010 family of RISC (reduced-instruction-set computer) processors and peripherals, which was originally a custom design for Acorn Computers Ltd. The resultant performance proved its value in many other functions as well, providing an ASIC (application-specific integrated circuit) core. The VL86C020 provides an ASIC-capability two-and-a-half times performance increase over the previous generation VL86C010 while maintaining software compatibility. By offering the CPU and cache memory on a single device, and itself as a core, the processor offers a superior upward migration path because the highest-frequency memory path is not required to cross a chip boundary. As process rules continue to shrink, the clock frequency can be increased for on-chip operations accordingly without making undue demands on external memory system bandwidth View full abstract»

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  • SPHINX-a VLSI processing element chip for pyramid computer

    Publication Year: 1989 , Page(s): P5 - 3/1-4
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    A VLSI processing element chip with a flexible clocking mode is presented. Each instruction can be executed in 4, 5, 7 clocking phases according to its clocking mode. A dual-outlet ALU was introduced to exploit the maximum intrainstruction parallelism. A condition flag and a special local pointer were introduced to realize some local or associative operations. Some design tradeoffs are discussed. This CMOS VLSI processing element chip was designed with compiled memory and standard cell, giving a transistor count of about 90000, and works with a clocking frequency of 14.3 MHz View full abstract»

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  • A GaAs 600 Mbit/s 24B1P coder/decoder ASIC

    Publication Year: 1989 , Page(s): P5 - 1/1-4
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    The technical details, tradeoffs, and economics associated with the design of a gallium arsenide 600-Mb/s 24B1P coder/decoder ASIC (application-specific integrated circuit) are reviewed. Key features of the design include the use of common components to allow integration of encoder and decoder on the one chip, a novel data accelerator/decelerator, and the use of asynchronous control circuitry. The ASIC is evaluated in terms of both complexity and effort in relation to designing with gallium arsenide standard cells. An improved design that can operate at rates in excess of 1.3 Gb/s is presented View full abstract»

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  • Synthesis of analog ASICs using optimization in conjunction with circuit simulation techniques

    Publication Year: 1989 , Page(s): P10 - 3/1-5
    Cited by:  Papers (1)
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    A description is given of the optimization methodology applied by the PRECISE computer program for the synthesis of analog ASICs. The application of simulation and optimization technology allows engineers to determine easily and automatically the element values and geometries needed to reach desired or measured analog circuit performance. The integration of both technologies to determine the optimum design parameters necessary to reach circuit objectives specified by the designer is described. Optimization in AC, DC, and transient domains can occur simultaneously to account for the interdependencies of the circuit element value in those domains. In addition, the optimization process can take place in discrete and constrained design parameter space so that the technological limits are accounted for and the optimal drawn lengths and widths are manufacturable. The optimization approach can be a powerful tool for the design of analog ASICs View full abstract»

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  • Introduction to CMOS analog standard cell ASIC design

    Publication Year: 1989 , Page(s): T2 - 1/1-4
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    This study is directed toward the mixed-signal ASIC (application-specific integrated circuit) system designer. The demand for mixed signal ASIC products continues to grow and places increased importance on reducing the design cycle time for the analog section of the chip. Modern generic digital CMOS technology is examined for use in analog integrated circuit design. Analog standard cells and design considerations are presented to assist in developing CMOS analog standard cell libraries for ASIC design View full abstract»

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  • A network access interface ASIC for a cross-connect system

    Publication Year: 1989 , Page(s): P8 - 2/1-4
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    The Alcatel Bell methodology for ASIC (application-specific integrated circuit) design is presented, showing the feasibility of a high degree of circuit reusability. The methodology is supported by a proprietary integrated ASIC CAD system, providing access to libraries and technologies of various ASIC vendors. A considerable reduction in design effort is gained due to reusing and/or adapting components of a library constructed from building blocks created during previous designs. This is illustrated by the design of the network access interface circuit (NAIC), a key component in a telecommunication cross-connect system View full abstract»

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  • IEEE-1149.1 use in design for verification and testability at Texas Instruments

    Publication Year: 1989 , Page(s): P4 - 1/1-5
    Cited by:  Papers (1)
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    Products aimed at standardization and cost reduction of IC and system test and debug, compatible with the JTAG/IEEE-1149.1 scan protocols and standards, are discussed. Included are ASIC (application-specific integrated circuit) cells, standard interface ICs, a bus master IC, a controller interface board for IBM compatibles, a high-speed scan interface, and software to control the scan bus. Tradeoffs to be looked at when using the JTAG/IEEE-1149.1 standard for ASIC are evaluated View full abstract»

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  • OASYS: a framework for analog circuit synthesis

    Publication Year: 1989 , Page(s): P13 - 1/1-4
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    A description is given of a hierarchical structure for a knowledge-based analog circuit synthesis tool. Analog circuit topologies are represented as a hierarchy of abstract functional blocks, each with associated design knowledge. The author also describes mechanisms for selecting from among alternate design styles and translating performance specifications from one level in the hierarchy to the next lower level. A prototype implementation, OASYS, synthesizes sized transistor schematics for CMOS operational amplifiers and comparators from a set of performance specifications and process parameters. The role such a synthesis system can play in exploring the space of designable circuits is examined View full abstract»

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  • ASIC design project scheduling

    Publication Year: 1989 , Page(s): P11 - 2/1-4
    Cited by:  Papers (1)
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    With the market-driven need to reduce product development times in the face of increasing complexity, the ability to forecast ASIC (application-specific integrated circuit) development time has become of paramount importance. The authors present techniques to forecast schedules more accurately, to minimize risks, and to improve productivity on a continuing basis. They found that it is critical to have a specification and a resource team; otherwise, schedule slips are almost certain. They point out that during the development process, tradeoffs must be made by the ASIC designer. To do so effectively, he or she must understand the end application. Risks need assessing and contingency planning. Scheduling itself must be addressed in three senses: future (forecasts), present (monitors) and past (data). The historical database helps to forecast as well as to identify opportunities for productivity improvement View full abstract»

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  • In-circuit-emulation in ASIC architectural core designs

    Publication Year: 1989 , Page(s): P6 - 4/1-4
    Cited by:  Papers (1)  |  Patents (15)
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    Software development and system integration in designs with microprocessors and microcontrollers is often accomplished with the aid of an in-circuit-emulator (ICE). Designs incorporating an architectural microcontroller core cell and peripheral cells embedded in an application-specific integrated circuit (ASIC) present additional challenges in software development and system integration. A description is given of the ASIC UCS51 family and a fully functional ICE that supports it. The core and peripheral cells are emulated with multiple ICs, and the user logic is emulated with programmable logic devices. Results of the first customer application and use are included View full abstract»

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