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Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,

25-28 Sept. 1989

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Displaying Results 1 - 25 of 82
  • BiCMOS ASICs: technology and applications

    Publication Year: 1989, Page(s):T6 - T0
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (35 KB)

    Summary form only given. An overview is presented of BiCMOS ASIC (application-specific integrated circuit) technology and applications. This covers device design, technology, gate array applications, standard cell applications, and system implications. A survey is conducted of current BiCMOS ASIC products. This presentation will address all current products by vendor, and by product types. It prov... View full abstract»

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  • Proceedings: The Second Annual IEEE ASIC Seminar and Exhibit (Cat. No.89TH0280-8)

    Publication Year: 1989
    Request permission for commercial reuse | PDF file iconPDF (34 KB)
    Freely Available from IEEE
  • Design of integrated circuits for electronic imaging applications

    Publication Year: 1989, Page(s):T11 - 1/1-6
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (396 KB)

    Electronic imaging places stringent demands on the signal processing circuitry for real-time operation. Dedicated processors that are algorithmic-specific are very attractive from speed, cost, and size considerations. The design of a digital image processing chip-set that falls in this domain is discussed. The design methodology, which includes circuit technologies for CMOS logic, memory, and data... View full abstract»

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  • Incremental netlist compilation for IKOS hardware logic simulator

    Publication Year: 1989, Page(s):P9 - 3/1-4
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (260 KB)

    Incremental compilation is desirable to avoid recompiling a large network when only a few modules are modified. An algorithm that partitions a network in a hierarchical manner is described. The linker links together separately compiled or linked modules to generate machine codes for the IKOS hardware simulator. The machine codes generated for the duplicate subnetworks (or logic blocks) need not be... View full abstract»

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  • A case study of functional design using functional simulation and logic synthesis

    Publication Year: 1989, Page(s):P2 - 1/1-4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB)

    Design time reduction to a half of what was previously required was achieved by a register-transfer-level (RTL) design procedure. The problems encountered in rule-based synthesis were identified through a detailed comparison of the manual logic design procedure with the rule-based logic synthesis procedure. A logic synthesizer using a rule base for local transformations was developed that is able ... View full abstract»

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  • ASIC design project scheduling

    Publication Year: 1989, Page(s):P11 - 2/1-4
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (372 KB)

    With the market-driven need to reduce product development times in the face of increasing complexity, the ability to forecast ASIC (application-specific integrated circuit) development time has become of paramount importance. The authors present techniques to forecast schedules more accurately, to minimize risks, and to improve productivity on a continuing basis. They found that it is critical to ... View full abstract»

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  • Electrical design rule checker for core and block based ASIC designs

    Publication Year: 1989, Page(s):P6/2/1 - P6/2/4
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (220 KB)

    Due to the complexity of ASIC (application-specific integrated circuit) designs, especially those containing core or block cells, it is necessary to perform automated design-rule checking on a netlist. An electrical design rule checker (EDRC) developed to perform design rule checks for conventional standard cells as well as core and block cells is described. Intel uses this tool as a part of accep... View full abstract»

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  • Wide-band analog CMOS circuits at intermediate frequencies

    Publication Year: 1989, Page(s):P10 - 1/1-6
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (324 KB)

    A cell library has been created for development of semicustom analog ICs. This library includes amplifier, variable gain amplifier, limiter, and switch cells for use in the 5-500 MHz band. Performance is comparable to that of similar IF frequency devices in both hybrid and discrete form. These circuits exhibit predictable characteristics, high yields, and high levels of integration. Suitable appli... View full abstract»

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  • Choosing a design center

    Publication Year: 1989, Page(s):T10 - 1/1-3
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (220 KB)

    A description is given of different paths available for a designer in implementing an ASIC (application-specific integrated circuit). ASIC implementation can be long, complicated, and risky if the choices are not made correctly at the beginning of the project. ASICs can be implemented using a vendor design center, distributor design center, independent design center, or a captive/in-house design c... View full abstract»

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  • Fault grading, a measure of logic simulation integrity

    Publication Year: 1989, Page(s):P9 - 2/1-4
    Cited by:  Papers (1)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    It is argued that although fault grading is generally used as a measure of the completeness of the test program, it has an even greater potential in measuring the integrity of the functional analysis as performed by the logic simulation. A brief description of stuck-at-1 and stuck-at-0 fault simulation is given. Fault simulation is contrasted with the typical controllability and observability meas... View full abstract»

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  • Performance analysis of a BiNMOS device

    Publication Year: 1989, Page(s):P1 - 4/1-4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (184 KB)

    The BiNMOS device associated with 2-μm n-well BiCMOS technologies consumes substantial area for isolation. A merged BiNMOS device structure is introduced to reduce device size. The performance of the merged BiNMOS device has been analyzed by PISCES-2B. DC characteristics show that the merged BiNMOS device has a higher driving capability. Turn-on transient analysis shows substantial substrate cu... View full abstract»

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  • Heuristic issues in analog IC design

    Publication Year: 1989, Page(s):P10 - 5/1-4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB)

    Design issues in analog IC design are discussed. Heuristic algorithms are considered as a means of reducing the computational complexity of the problem. A module generator for an op amp, which incorporates heuristic algorithms to choose circuit technology and reduce crosstalk in the placement and routing of the layout, is presented View full abstract»

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  • IEEE-1149.1 use in design for verification and testability at Texas Instruments

    Publication Year: 1989, Page(s):P4 - 1/1-5
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (344 KB)

    Products aimed at standardization and cost reduction of IC and system test and debug, compatible with the JTAG/IEEE-1149.1 scan protocols and standards, are discussed. Included are ASIC (application-specific integrated circuit) cells, standard interface ICs, a bus master IC, a controller interface board for IBM compatibles, a high-speed scan interface, and software to control the scan bus. Tradeof... View full abstract»

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  • Automation of core-based design construction

    Publication Year: 1989, Page(s):P6 - 1/1-4
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB)

    There are numerous complex tasks involved in the construction and verifications of a customized ASIC (application-specific integrated circuit) system design. Intel's UCS51 design entry tool (UCS51 DET) greatly simplifies this process by automating schematic capture of the intricate connections between an ASIC version of the 80C51 microcontroller and its associated peripheral cells. Furthermore, th... View full abstract»

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  • A university flexible technology foundry for VLSI application specific integrated circuits

    Publication Year: 1989, Page(s):P14 - 2/1-4
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (324 KB)

    The Rochester Institute of Technology has established a factory operation within its cleanroom facility. The factory coexists with class laboratory instruction and research. About one lot per week is released into the factory, and processing is completed automatically by paid student operators several weeks later. The customers for the factory are students and faculty involved in VLSI design cours... View full abstract»

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  • Application-specific array processors

    Publication Year: 1989, Page(s):T8 - 1/1-6
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    An application-specific array processor (ASAP) means a high-speed, application-driven, massively parallel, modular, and programmable computing system. The ever-increasing super-high-speed requirement (in giga/tera FLOPS) in modern engineering applications suggests that mainframe scientific computers will not be adequate for many real-time signal/image processing and scientific computing applicatio... View full abstract»

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  • A circuit simulation model of submicron MOSFETs for SPICE

    Publication Year: 1989, Page(s):P9 - 5/1-4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (308 KB)

    A computationally efficient submicron MOSFET I-V model for circuit simulation in SPICE is provided. It is an improved model of the LEVEL3 MOS model in SPICE and supports the design of conventional as well as LDD (lightly doped drain) MOSFETs down to the submicron range. The drain-source series resistance and three-dimensional geometry effects are included in the model. In additio... View full abstract»

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  • Custom cell development for standard cell designs

    Publication Year: 1989, Page(s):P11 - 4/1-3
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (212 KB)

    The ASIC (application-specific integrated circuit) designer often searches through various ASIC databooks trying to locate a cell that the design requires. If it is not possible to find the cell needed, the designer either changes the design so it can be implemented using cells that are available or requests the development of a custom cell from the ASIC supplier. A discussion is presented of cust... View full abstract»

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  • In-circuit-emulation in ASIC architectural core designs

    Publication Year: 1989, Page(s):P6 - 4/1-4
    Cited by:  Papers (1)  |  Patents (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (272 KB)

    Software development and system integration in designs with microprocessors and microcontrollers is often accomplished with the aid of an in-circuit-emulator (ICE). Designs incorporating an architectural microcontroller core cell and peripheral cells embedded in an application-specific integrated circuit (ASIC) present additional challenges in software development and system integration. A descrip... View full abstract»

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  • ASIC technical training-the challenges and opportunities

    Publication Year: 1989, Page(s):P14 - 4/1-4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (252 KB)

    The author explores the challenges for ASIC (application-specific integrated circuit) technical training, now and in the future, in the area of standard product vs. ASIC training (i.e. microcontrollers). She examines the opportunity for setting the ASIC customer up for success through training. Specifically, the author introduces a method for training designed to reduce the risk involved in ASIC d... View full abstract»

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  • GaAs ASIC design case study

    Publication Year: 1989, Page(s):T9 - 1/3
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (112 KB)

    A design experience with GaAs ASICs (application-specific integrated circuits) is presented from the user's point of view. Vendor selection criteria, design experience, board considerations, and testings are discussed in detail. It is shown that through the application of GaAs ASICs a much greater understanding of what is required to implement them into a system has been achieved. Generally, these... View full abstract»

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  • High performance compilers for ASIC designs

    Publication Year: 1989, Page(s):P12 - 2/1-4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (356 KB)

    An explanation is given of why it is important for an IC designer to consider the use of precompiled modules such as RAM, ROM, and multipliers in application-specific IC (ASIC) circuits. The advantages in IC performance and the subsequent improvement in the overall system performance are explained. Examples of compiled memories and multipliers are compared to give the reader an idea of the perform... View full abstract»

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  • ECL ASIC, a practical choice of high performance systems

    Publication Year: 1989, Page(s):T9 - 1/7-9
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (188 KB)

    The authors give designers who are not familiar with ECL (emitter-coupled logic) ASICs (application-specific integrated circuits) the basic knowledge necessary for starting an ECL array design. They cover basic ECL ASIC technology and explain how to take advantage of its unique features. The issue of power consumption and methods for reducing it are discussed in detail View full abstract»

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  • Fault grading operational self-test

    Publication Year: 1989, Page(s):P9 - 1/1-5
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (420 KB)

    A study is presented on fault grading of the OST (operation self-test) for a Delco VHSIC 1750A computer in its early design phases, using a commercially available hardware accelerator. The OST fault-grading effort illustrated the need for design methodologies that take into consideration the capabilities of today's CAE tools. A fault simulation methodology and design guidelines for optimizing the ... View full abstract»

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  • High performance CMOS dual-port SRAM compiler

    Publication Year: 1989, Page(s):P3 - 2/1-4
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (252 KB)

    A high-density, high-performance dual-port SRAM (static RAM) compiler has been developed with standard product features. The compiler can generate different SRAM configurations with a minimum of 512 bits up to a maximum of 9 kbits. The SRAM has a typical access time of 15 ns (1.5-μm ASIC (application-specific integrated circuit) process) for the largest configuration (1 K words×9 bits or ... View full abstract»

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