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ASIC Seminar and Exhibit, 1989. Proceedings., Second Annual IEEE

Date 25-28 Sept. 1989

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  • Proceedings: The Second Annual IEEE ASIC Seminar and Exhibit (Cat. No.89TH0280-8)

    Publication Year: 1989
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    Freely Available from IEEE
  • Composite device model enhances worst case simulation of bipolar analog ASICs

    Publication Year: 1989 , Page(s): P13 - 3/1-3
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (212 KB)  

    It is shown that practical simulations of worst-case performance of analog ASIC (application-specific integrated circuit) designs are enhanced by the use of a composite device model containing low, typical, and high sets of parameters. The composite model allows process related parameters, mismatch effects, and correlation between parameters to be included in single sets of simulations using sensi... View full abstract»

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  • Predictive analysis of sensitivity to chip-routing parasitics

    Publication Year: 1989 , Page(s): P13 - 4/1-4
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    The authors describe a system which is able automatically to bring to the attention of the designer significant performance sensitivities which are introduced through interconnection parasitics. The input to the tool is a SPICE file and a performance specification provided by a designer. The output is again a SPICE file, but augmented with those interconnection parasitics which are most significan... View full abstract»

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  • A single-polysilicon flip-flop EEPROM for ASIC application

    Publication Year: 1989 , Page(s): P3 - 3/1-4
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (176 KB)  

    A single-polysilicon flip-flop EEPROM has been developed. A single-polysilicon structure which is suitable for ASIC (application-specific integrated circuit) application and a flip-flop-type cell give an endurance of more than 1,000,000 cycles. With this technology, a one-chip computer with CPU, RAM, ROM, some I/O ports, and EEPROM has been fabricated View full abstract»

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  • Perspective on BiCMOS

    Publication Year: 1989 , Page(s): P1 - 2/1-4
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (152 KB)  

    The objective of Hi-BiCMOS is to combine speed performance approaching that of ECL and integration density approaching that of CMOS. A high-performance 1.3-μm BiCMOS technology and its applications to ASICs (application-specific integrated circuits) are described. This Hi-BiCMOS gate array contains 3072 gates and 90 input/output buffers. The inclusion of bipolar transistors enables this array t... View full abstract»

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  • PIMM1, an image processing ASIC based on mathematical morphology

    Publication Year: 1989 , Page(s): P7 - 1/1-4
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (312 KB)  

    To meet image analysis requirements in terms of processing speed and computing capacities, the authors have developed an ASIC (application-specific integrated circuit) with a programmable architecture, supporting the latest algorithms of mathematical morphology. Designed in 1.5-μm CMOS technology, the ASIC can process 8-b images at a 20-MHz pixel frequency, in pipeline or in parallel. The archi... View full abstract»

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  • Ground bounce in CMOS ASICs

    Publication Year: 1989 , Page(s): P9 - 4/1-4
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (360 KB)  

    A study has been undertaken to investigate the ground bounce phenomena in CMOS ASICs (application-specific integrated circuits). A simple mathematical analysis was performed to help gain an intuitive understanding of the problem. SPICE simulations were then performed to build a more detailed model. The SPICE model allowed different problem solving approaches to be compared in a straightforward man... View full abstract»

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  • Synthesis of analog ASICs using optimization in conjunction with circuit simulation techniques

    Publication Year: 1989 , Page(s): P10 - 3/1-5
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (384 KB)  

    A description is given of the optimization methodology applied by the PRECISE computer program for the synthesis of analog ASICs. The application of simulation and optimization technology allows engineers to determine easily and automatically the element values and geometries needed to reach desired or measured analog circuit performance. The integration of both technologies to determine the optim... View full abstract»

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  • IEEE-1149.1 use in design for verification and testability at Texas Instruments

    Publication Year: 1989 , Page(s): P4 - 1/1-5
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (344 KB)  

    Products aimed at standardization and cost reduction of IC and system test and debug, compatible with the JTAG/IEEE-1149.1 scan protocols and standards, are discussed. Included are ASIC (application-specific integrated circuit) cells, standard interface ICs, a bus master IC, a controller interface board for IBM compatibles, a high-speed scan interface, and software to control the scan bus. Tradeof... View full abstract»

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  • A university flexible technology foundry for VLSI application specific integrated circuits

    Publication Year: 1989 , Page(s): P14 - 2/1-4
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (324 KB)  

    The Rochester Institute of Technology has established a factory operation within its cleanroom facility. The factory coexists with class laboratory instruction and research. About one lot per week is released into the factory, and processing is completed automatically by paid student operators several weeks later. The customers for the factory are students and faculty involved in VLSI design cours... View full abstract»

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  • GaAs ASIC technology

    Publication Year: 1989 , Page(s): T9 - 1/1-2
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    The state of the GaAs IC industry is summarized from an application-specific product perspective. Presently available products, packaging technology, applications, reliability, and future product directions are discussed View full abstract»

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  • A high throughput, asynchronous, dual port FIFO memory implemented in ASIC technology

    Publication Year: 1989 , Page(s): P3 - 1/1-4
    Cited by:  Papers (2)  |  Patents (8)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (264 KB)  

    An ASIC (application-specific integrated circuit) first-in-first-out (FIFO) memory circuit that has the capability of interfacing two data processing units operating at different speeds is described. The memory is implemented using a circular queue structure, which permits writing and reading of data indefinitely as long as the boundary flag conditions are not met. This memory also has the capabil... View full abstract»

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  • High density and high performance ECL: some design tips

    Publication Year: 1989 , Page(s): T9 - 1/4-6
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (232 KB)  

    Recent developments in ECL (emitter-coupled logic) circuit technology have led to a new generation of high-density and higher-performance gate arrays. The choice of an ECL ASIC (application-specific integrated circuit) technology is discussed with regard to the use of proven versus new technology, ASIC benchmarks, and second sourcing. Design issues considered are the optimization of density and pe... View full abstract»

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  • A 1.3 μm BiCMOS gate array with configurable on-chip 3-port RAM

    Publication Year: 1989 , Page(s): P3 - 4/1-4
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (176 KB)  

    A 10 K-gate BiCMOS gate array with a configurable 4.6-kb SRAM (static RAM) has been developed using a 1.3-μm technology. The propagation delay time of a two-input NAND is 0.45 ns at 0.6-pF load. The on-chip memory can be configured as ×9, ×18, ×36 b. A description is given of the device structure, the basic cell design, the memory configuration, and the performance of this mem... View full abstract»

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  • Key to a successful cell library development: design methodology

    Publication Year: 1989 , Page(s): P12 - 1/1-4
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (256 KB)  

    It is argued that cell library development will not be successful unless a solid design methodology is established. The design methodology directs the development of a library that meets the needs of both the ASIC customer and the library developer. A discussion is presented of a method of devising a design methodology flow that results in a library with three essential attributes: productivity, r... View full abstract»

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  • A circuit simulation model of submicron MOSFETs for SPICE

    Publication Year: 1989 , Page(s): P9 - 5/1-4
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (308 KB)  

    A computationally efficient submicron MOSFET I-V model for circuit simulation in SPICE is provided. It is an improved model of the LEVEL3 MOS model in SPICE and supports the design of conventional as well as LDD (lightly doped drain) MOSFETs down to the submicron range. The drain-source series resistance and three-dimensional geometry effects are included in the model. In additio... View full abstract»

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  • Automation of core-based design construction

    Publication Year: 1989 , Page(s): P6 - 1/1-4
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (368 KB)  

    There are numerous complex tasks involved in the construction and verifications of a customized ASIC (application-specific integrated circuit) system design. Intel's UCS51 design entry tool (UCS51 DET) greatly simplifies this process by automating schematic capture of the intricate connections between an ASIC version of the 80C51 microcontroller and its associated peripheral cells. Furthermore, th... View full abstract»

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  • ASIC replacement for an SSI component design-a case study

    Publication Year: 1989 , Page(s): P8 - 5/1-4
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (348 KB)  

    This case study covers the practical issues of design for functionality, design for simulation, and design for testability in replacing aging SSI (small-scale-integration) component designs with ASIC (application-specific integrated circuit) gate arrays. The replacement of a 169-TTL (transistor-transistor logic) component design with a CMOS ASIC gate array is presented. Existing functionality is m... View full abstract»

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  • Heuristic issues in analog IC design

    Publication Year: 1989 , Page(s): P10 - 5/1-4
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (312 KB)  

    Design issues in analog IC design are discussed. Heuristic algorithms are considered as a means of reducing the computational complexity of the problem. A module generator for an op amp, which incorporates heuristic algorithms to choose circuit technology and reduce crosstalk in the placement and routing of the layout, is presented View full abstract»

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  • BiCMOS ASICs: technology and applications

    Publication Year: 1989 , Page(s): T6 - T0
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (28 KB)  

    Summary form only given. An overview is presented of BiCMOS ASIC (application-specific integrated circuit) technology and applications. This covers device design, technology, gate array applications, standard cell applications, and system implications. A survey is conducted of current BiCMOS ASIC products. This presentation will address all current products by vendor, and by product types. It prov... View full abstract»

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  • PC/AT-compatible devices: fewer is better

    Publication Year: 1989 , Page(s): P8 - 3/1-4
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (256 KB)  

    The use of several chip sets for the IBM PC/AT-type system, which offered cost and performance advantages over other standard discrete implementation, is discussed. It is shown that using ASIC (application-specific integrated circuit) techniques allows not only huge device count reductions, but also permits further, proprietary ASIC advances for enhanced or unique functions. A system based on the ... View full abstract»

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  • Painless ASIC design in the system environment

    Publication Year: 1989 , Page(s): P11 - 3/1-3
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (240 KB)  

    ASICs (application-specific integrated circuits) have been successfully designed at the component level using engineering workstations (EWS) since the early eighties. Although many workstations allow `right-first-time' chips to be produced, they do not always offer system designers a secure link for the incorporation of these chips into the overall system. The author explores the needs, features a... View full abstract»

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  • Design automation system and architecture for high-performance integer applications

    Publication Year: 1989 , Page(s): P7 - 2/1-4
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (360 KB)  

    A CAD system for design and synthesis of high-performance processors tailored to digital signal processing (DSP) applications is described. A unique design capture system supports independent specification of processor function, throughput, and accuracy, while a powerful circuit generation system isolates designers from details of the processor implementation. Circuits are assembled automatically ... View full abstract»

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  • ECL and CMOS ASICs for time-to-digital conversion

    Publication Year: 1989 , Page(s): P5 - 2/1-4
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (336 KB)  

    ECL (emitter-coupled logic) and CMOS ASICs (application-specific integrated circuits) that are designed for short time interval measurements are presented. An ECL gate array designed for a time-to-digital converter based on analog interpolation techniques and constructed by discrete techniques in order to reduce its power consumption and circuit board area is described. The design and test of an i... View full abstract»

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  • ASIC design for testability

    Publication Year: 1989 , Page(s): T1 - 1/1-10
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (652 KB)  

    Advanced testability techniques are described for ASIC (application-specific integrated circuit) design. BIST (built-in self-test), scan test, boundary scan, embedded cores, and mixed-signal circuitry are among the topics discussed. A CAE methodology and a specific case study are analyzed for each ASIC design choice. Emphasis is on modular design for test, automated testability analyses, and compr... View full abstract»

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