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System Synthesis, 2002. 15th International Symposium on

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System Synthesis, 2002. 15th International Symposium on

Date 2-4 Oct. 2002

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Title History

15th International Symposium on System Synthesis (IEEE Cat. No.02EX631)

A Trimaran based framework for exploring the design space of VLIW ASIPs with coarse grain functional units

Tuning of loop cache architectures to programs in embedded system design

Combined functional partitioning and communication speed selection for networked voltage-scalable processors

Optimal message-passing for data coherency in distributed architecture

Unifying memory and processor wrapper architecture in multiprocessor SoC design

An accelerated datapath width optimization scheme for area reduction of embedded systems

Datapath merging and interconnection sharing for reconfigurable architectures

A run-time word-level reconfigurable coarse-grain functional unit for a VLIW processor

Energy/power estimation of regular processor arrays

Controller estimation for FPGA target architectures during high-level synthesis

System-level modeling of a network switch SoC

Multiprocessor mapping of process networks: a JPEG decoding case study

System-level design of IEEE1394 bus segment bridge

Security-driven exploration of cryptography in DSP cores

A case study of hardware and software synthesis in ForSyDe

An adaptive low-power transmission scheme for on-chip networks

CMP on SoC: architect's view

Design experience of a chip multiprocessor Merlot and expectation to functional verification

OpenMP: parallel programming API for shared memory multiprocessors and on-chip multiprocessors

Managing dynamic concurrent tasks in embedded real-time multimedia systems

A design space exploration framework for reduced bit-width Instruction Set architecture (rISA) design

Timing analysis of embedded software for speculative processors

Modeling assembly instruction timing in superscalar architectures

Code compression for VLIW processors using variable-to-fixed coding

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