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Real Time, 1989. Proceedings., Euromicro Workshop on

Date 14-16 Jun 1989

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Displaying Results 1 - 25 of 27
  • The design of Tri-D real-time computer systems

    Page(s): 84 - 92
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    A family of designs are presented for high-performance real-time computers based on novel real-time computer design principles. These design principles are founded upon a three-dimensional measure that defines system performance in three critical dimensions of real-time computing: raw computational speed, high-speed interrupt handling, and high input/output throughput. High three-dimensional performance is achieved through: (1) the design of an architecture based on a symmetrical tightly-coupled multiprocessor structure; (2) the use of custom-designed very large-scale integration (VLSI) and application-specific integrated circuit (ASIC) chips; and (3) the development of a real-time Unix operating system. In addition, these so-called Tri-D systems are characterized by several key fault tolerance features that provide enhanced reliability, availability, and graceful degradation capabilities View full abstract»

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  • A priori execution time analysis for parallel processes

    Page(s): 62 - 65
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    A method of knowing a priori the time required by parallel processes to complete their execution is described, which allows for the automatic estimation of an upper bound for a task's execution time. The method is discussed within the framework of the high-level real-time programming language Pearl. Several language extensions are defined to enable the execution-time estimations for all language constructs. The practical implementation of the method is based on a combination of a control-flow analyzer with procedures determining the execution times of compiled code and carrying out the developed estimation rules, respectively. The importance of the method for the utilization of deadline-driven scheduling is pointed out View full abstract»

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  • Queueing analysis in dynamic distributed real-time systems

    Page(s): 162 - 166
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    The effect of queueing on a dynamic distributed real-time system, in which jobs have hard deadline requirements, is studied. A job can be guaranteed to be completed before its deadline expires; it is rejected otherwise. An analytic model is presented to calculate the probability that an arbitrary arriving job will be guaranteed. An embedded Markov chain is first established, followed by a probability analysis. In the model, only one copy of the resource is considered. If more than one copy exists in the distributed real-time system, the scheduling discipline for incoming jobs among these copies will affect the probability that a job can be guaranteed. It is shown that a round-robin scheduling, in which arriving jobs are assigned to all the copies of the resource in a cyclic order, is the best strategy. In this strategy, a job that cannot be guaranteed by its assigned copy can never be guaranteed by other copies either. However, it requires a centralized controller to assign the load. The performance issue for cases with multiple copies of a resource is noted with respect to various strategies. The model is nevertheless useful for further research where multiple copies will be taken into account or for the design of a real-time system where jobs with a hard deadline requirement arrive to the system dynamically and nonperiodically View full abstract»

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  • Real time properties of LANs according to the Manufacturing Automation Protocol (MAP)

    Page(s): 146 - 150
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    The author reports on an evaluation of real-time properties of Manufacturing Automation Protocol (MAP) networks through analytical considerations which are then compared to measurement data. Measurements were made on a MAP 2.1 network that consists of 5 nodes based on the Motorola VME-bus MAP-controller MVME 372. This implementation has a complete logical link control layer (LLC-layer) and MAP-layer according to ISO 8802/8804 (with LLC-type 3 and priorities). Figures for message delay (for the MAC layer) and response time (for the transport layer) are given. Results for selecting protocol parameters affecting real-time behavior are given. Aspects for improved implementations of communication controllers for MAP networks are discussed View full abstract»

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  • Scheduling problems while compiling the real-time language Lustre on the digital signal processor ST18930

    Page(s): 178 - 186
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    An experiment in optimizing the computations of loops on a digital signal processor is reported. Working with a simple pipelined monoprocessor, the DSP ST18930, the goal was to optimize the code generated by a dedicated version of the Lustre compiler. If there is a computation loop whose end may be overlapped with the beginning of the next loop, the problem is to minimize the delay between two successive initiations of such loops. After briefly summarizing Lustre, the source real-time language, the DSP ST18930 is briefly described. The pipeline used in the execution of instructions is highlighted. The method is verified using a lattice filter example View full abstract»

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  • Computational reflection in RT systems

    Page(s): 31 - 36
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    Computational reflection is the activity performed by a computational system when doing computation about its own computation. This concept is highly relevant in real-time (RT) nonstopping systems where the distinction between host and target vanishes. The authors present a model where the system is represented as a network of objects and relations. Objects have multiple representations partitioned into environments devoted to specific reflection activities. The approach allows the design of a system in an integrated way and the implementation of each environment according to cost-performance tradeoffs View full abstract»

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  • New approaches for distributed industrial process control systems aimed to cope with strict time constraints

    Page(s): 130 - 136
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    Four approaches aimed to cope with strict timing constraints as encountered in industrial process control applications are presented. For each node in a distributed system, an asymmetrical two-processor architecture is used that is capable of guaranteeing response times. One processor in each node is dedicated to the kernel of a real-time operating system. Its three reaction levels are constructively described by outlining their functional units and control procedures. It is shown that some problems of real-time computers can be solved by endowing the node computers with process peripherals View full abstract»

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  • Dynamically reconfigurable devices used to implement a self-tuning, high performance PID controller

    Page(s): 107 - 112
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    The implementation of an autotuning proportional-integral-differential (PID) digital controller using devices called logic cell arrays (LCAs) is described. The most significant difference with respect to conventional gate arrays is the fact that LCAs in the functions of the logic networks are defined by a configuration pattern stored in a RAM internal to the device itself. Thus, logic cell arrays require no custom factory fabrication; each device is identical until configured by the user. The PID autotuning method implemented in this system is briefly described and a detailed description of the PID prototype is given. The resulting prototype shows the possibility of implementing a low-cost control system where time-critical operations are performed by these reconfigurable devices, while supervising tasks are accomplished by traditional programmable logic View full abstract»

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  • Analysis and implementation of hierarchical real-time architectures

    Page(s): 66 - 73
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    Multiprocessor architectures for real-time applications in signal processing and control are described. An investigation of these architectures to determine their performance under a variety of applications and task mixes is presented. The goal is to develop tools for configuring applications on multiple processor systems so that real-time constraints are met. The approach used is to solve queueing models that have been verified by empirical measurement of critical parameters taken during actual operation of the systems. Results relating to contention for bus use in the system are shown View full abstract»

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  • Real-time reconfiguration of two-dimensional VLSI arrays

    Page(s): 217 - 225
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    The extension of index mapping to the reconfiguration of two-dimensional VLSI arrays in real time is presented. Index mapping is implemented by a two-operator technique which assigns to a faulty cell a unique fault free space. This process is accomplished by a decentralized parallel approach which finds the appropriate of deformation for the recomputation of the indices and their mapping. It is proved that this process is O(1) if the number of simultaneously faulty cells is restricted to one. The proposed technique can also be applied efficiently in the presence of multiple (accumulated) faulty cells. It is shown that the hardware overhead required for routing and switching is very small. It is proved also that the proposed technique provides an optimal solution to reconfiguration if cells fail according to certain patterns. Illustrative examples are shown View full abstract»

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  • Multiple processor architectures for real time parameter estimation

    Page(s): 93 - 100
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    Several multiple processor architectures which allow parallel implementations of the recursive least-squares estimation algorithm are presented and evaluated. The multiple processor architectures are based on the transputer which supports the process model of computation and allows the distribution of concurrent processes on different processors. The computational complexity of the estimation algorithm for a nr ×m matrix of parameters can be reduced from O(nr ×m2) to O(m) using suitable systolic architectures. Also shown are computation time measurements. The parallel architectures allow an effective implementation of the estimation algorithm, even in complex applications which require a computation time of hundreds of microseconds View full abstract»

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  • Architectural support for debugging and monitoring real-time software

    Page(s): 200 - 210
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    A two-phase approach for nonintrusive debugging of real-time programs is outlined. The first phase involves monitoring the program and the second phase is concerned with replaying the program to get identical behavior. The first phase is concentrated on in this paper, and some of the difficulties in nonintrusive monitoring are highlighted. Architectural modifications that must be made to the target processor to enable nonintrusive debugging are proposed. A memory scheme that enables nonintrusive checkpointing is described, and the authors explain how the architectural modifications coupled with the proposed memory scheme provide a framework for nonintrusive debugging View full abstract»

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  • Adaptive real-time file handling in local area networks

    Page(s): 153 - 161
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    Current and future needs in building adaptive real-time systems are analyzed and a series of design requirements for their hardware/interconnection, operating system, and application levels are formulated. The major features of the corresponding integrated system design model are described. On the operating system level, services are rendered by the DRAGON SLAYER distributed operating system to both meet real-time constraints and provide for high availability in a hazardous environment. It also allows for replicating, relocating, or deleting file copies. Such copies may also assume a different status regarding the recency of their information. Depending on the deadline failure history, status changes as well as file replication, deletion, or relocation are analyzed and managed by local file assigners, based on cost and time delay criteria. Also reported is a sensitivity study that shows how promptly the model file system reacts to changing environmental situations (changing request patterns). Findings are discussed, and future work is outlined View full abstract»

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  • TPP-SO/P: a real-time operating system for distributed applications

    Page(s): 44 - 50
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    The authors present a real-time, multitasking, multiuser operating system for a processor board based on the Intel microprocessor iAPX 286. Protection mechanisms and task management features of the processor are noted. An extended CHILL concurrency environment is implemented to provide facilities for real-time software development. Memory management, system interface, debugging, fault treatment, implementation, and usage are also discussed View full abstract»

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  • Machine control systems: performance evaluation of conventional and dataflow concepts

    Page(s): 114 - 123
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    A performance evaluation of a novel or dataflow architecture for embedded systems is presented with a comparison with the conventional control system. An analytic model of the two architectures (OR dataflow and control flow) is constructed. Based on this model, performance parameters, such as throughput, delays, and capacity, were calculated. The theoretical analysis and comparison of the dataflow-driven and control-flow-driven systems suggest a superiority of the OR dataflow architecture. To verify these results, a real grinding machine control system was built and an experimental verification of the theoretical approach was performed. The OR dataflow-driven control system was constructed using the same hardware components as its conventional control-flow-driven counterpart. The efficiency of this system is compared with that of conventional control systems using as an example the grinding of a workpiece to stringent quality requirements View full abstract»

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  • The rationale of an environment for real-time software

    Page(s): 37 - 42
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    Some core ideas that lead to the definition of an environment for real-time systems are discussed. It is explained how integration, flexibility, and validation support can be achieved by using a suitable formalism as a hidden underlying kernel for the environment. The kernel formal notation proposed (called environment relationship nets, or ER nets) is an extension of Petri nets where tokens are not anonymous. Rather, they are environments, i.e. mappings between variables and values. The use of the kernel model for supporting the development cycle is described, and the flexibility of the model which can support a wide set of views at different levels of abstraction and for different kinds of users at the same level is shown. The problems connected with the quality assurances of the system being developed are also discussed View full abstract»

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  • Designing time critical systems with TACT

    Page(s): 74 - 82
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    The authors propose a small set of extensions with language and run-time support, based on reliable communication and atomic actions, to the concurrent programming language OCCAM2. A description of the syntax and a formal definition of the semantics of the constructs, which are based on labeled transition systems, are given. Provisions for backward error recovery are described that allow well-established fault-tolerant strategies to be constructed. A simple example of the design paradigm is described. Some details of implementation issues are also given View full abstract»

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  • Routing messages with release time and deadline constraints

    Page(s): 168 - 177
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    The problem of deciding if a set of real-time messages can be transmitted in a unidirectional ring network with m>1 nodes is considered. Complexity results are given for various restrictions on the four parameters associated with each message: origin node, destination node, release time and deadline. For nonpreemptive transmission, it is shown that the problem is solvable in polynomial time for any case when only one of the four parameters is allowed to be arbitrary. Also shown is that it is NP-complete for each case when any two of the four parameters are fixed. For preemptive transmission, the problem is solvable in polynomial time for any case when only one of the four parameters is allowed to be arbitrary. Also, it is NP-complete for each case when any two of the four parameters are fixed, except the following two cases: (1) same origin node and release time; and (2) same destination node and deadline View full abstract»

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  • Combining different granularity of concurrency for real time applications

    Page(s): 11 - 17
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    The authors investigate how adequate tools for concurrent programming may improve the development of real-time applications. First, any such application can be decomposed as a set of cooperating processes. Secondly, if adequate architectural support is available, further parallelism of execution can be achieved on critical parts of the program. The model of concurrency, and the granularity of decomposition, which are best suited for meeting either objective, are shown to be different. Then, the problem of automatically decomposing critical sequential parts into parallel tasks is examined. An example is given, to illustrate the advantages of the proposed methodology, and an implementation strategy for its run-time support is outlined View full abstract»

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  • Testing and debugging in real time systems-design decisions to use a distributed computer architecture in a real time application

    Page(s): 101 - 106
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    A description is given of the design decisions that lead to a distributed computer architecture along with the computer's test and debugging facilities. This architecture was developed for an autonomous mobile robot and supports the special data processing structure of such real-time applications. Time behavior considerations led to the use of a distributed computer architecture with static task distribution and without a multitasking environment in the nodes. Because the nodes are thus loosely coupled and exchange their results via a communication system with a separate processor, the modules and the communication between them can easily be monitored without influencing the time behavior by listening to the data and results transported by the communication system View full abstract»

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  • The ART testbed: towards a predictable and reliable distributed real-time system

    Page(s): 211 - 216
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    An overview of the software components of the Advanced Real-time Technology (ART) system is given. In particular, the integrated time-driven scheduling model which provides predictability, flexibility, and ease of modification for both hard and soft real-time activities, the ARTS kernel including real-time object and thread support, and its basic performance are described. Also included is a summary of the testbed's current status View full abstract»

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  • Pattern-directed real-time execution of SA/RT specifications

    Page(s): 3 - 9
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    Initial results with an experimental run-time system are reported. The run-time system makes possible real-time execution of software specifications created according to the structured analysis for real-time systems (SA/RT) techniques. A prototype of the run-time system is implemented in C language and runs in an Apple MacIntosh II/MPW C environment. Average execution speeds of approximately 2000 state transitions or data transformations/s were measured for nontrivial benchmark specifications. The run-time system is capable of executing SA/RT specifications that are generated automatically into object-oriented C language format from high-level Petri-net representation of SA/RT specifications. The run-time system is based on an efficient pattern-directed implementation of the Ward scheduling algorithms View full abstract»

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  • Time-closed layer: a design principle for time-critical applications

    Page(s): 138 - 145
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    A design principle, called time-closed layer, is developed for specifying and designing time-critical computing systems. The principle is based on the pseudoserialization to the systems activities. Each sub-activity is represented by a layer that satisfies both communication and time closedness properties. Operations such as SEQ, WHILE, ELSE, and ALT may be performed on layers. These operations allow the designer to manipulate layers in an algebraic manner. Formal semantics of the layers is also given using operational semantics approach to programming languages. The use of the time-closed layer is illustrated by designing a simple time-critical system which monitors and controls a reactor View full abstract»

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  • TRIO, a logic formalism for the specification of real-time systems

    Page(s): 26 - 30
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    Results are presented of a research project aimed at the definition of an executable logic formalism for the specification of real-time systems. The logic language TRIO allows the specifier to express formally and quantitatively the temporal properties of the specified systems. A formal definition of execution of specifications in terms of generation of interpretations for the corresponding formulas is given. Also given are the conditions and degrees of generality in which such execution is possible. A specification environment based on the TRIO formalism is outlined View full abstract»

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  • Different approaches to real-time application allocation to a multiprocessor system

    Page(s): 18 - 23
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    Existing approaches to the design of real-time application assignment algorithms are classified and evaluated. The different approaches considered are: one described by T.L. Casavant and J.G. Kuhl (IEEE Trans. Soft. Eng., vol.14, no.2, 1988), load balancing, interprocessor communication minimization, fixed allocation first, those that use precedence consideration methods, and constraint allocation. The influence of the module size ratio and module replication are also noted. A method is then briefly reviewed that tries to combine all mentioned policies in a flexible way. This means the user can always emphasize the criterion which is the most important for a particular real-time application View full abstract»

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