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Memory Technology, Design and Testing, 2003. Records of the 2003 International Workshop on

Date 28-29 July 2003

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Displaying Results 1 - 15 of 15
  • An electrical simulation model for the chalcogenide phase-change memory cell

    Publication Year: 2003, Page(s):86 - 91
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (248 KB) | HTML iconHTML

    Chalcogenide glass is being investigated by several companies as the basis for a scalable and embeddable nonvolatile phase-change memory technology. One phase is a high-resistance amorphous phase that is obtained by melting a small volume of glass using ohmic heating, and then quenching it. The second phase is a low-resistance crystalline phase that is obtained by heating the glass to just below t... View full abstract»

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  • A multilevel DRAM with hierarchical bitlines and serial sensing

    Publication Year: 2003, Page(s):14 - 19
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (257 KB) | HTML iconHTML

    We propose a multilevel DRAM (MLDRAM) with serial sensing that has lower area overhead than designs that use single-step, flash conversion sensing. The new design exploits hierarchical, multidivided bitlines to offset the reduction in noise margins caused by multilevel signaling and thereby better preserve the signal-to-noise ratio. The multiple sensing operations required to recover multilevel da... View full abstract»

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  • A 40 ns random access time low voltage 2Mbits EEPROM memory for embedded applications

    Publication Year: 2003, Page(s):81 - 85
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (276 KB) | HTML iconHTML

    2Mbits EEPROM memory has been designed using the ATMEL 0.18 μm embedded technology. On silicon program and read access time measurements are given, and an optimized production testing flow is proposed. View full abstract»

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  • Optimal spare utilization in repairable and reliable memory cores

    Publication Year: 2003, Page(s):64 - 71
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (308 KB) | HTML iconHTML

    Advances in System-on-Chip (SoC) technology rely on manufacturing and assembling high-performance system cores for many critical applications. Among these cores, memory occupies the largest portion of the SoC area; this trend much likely will continue in the future as it is widely anticipated that it will approach the 94% level by the year 2014. As memory cells are more prone to defects and faults... View full abstract»

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  • Reducing test time of embedded SRAMs

    Publication Year: 2003, Page(s):47 - 52
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (226 KB) | HTML iconHTML

    Compared with traditional functional fault models, fault model obtained from an Inductive Fault Analysis (IFA) test flow can provide an attractive basis for obtaining a good estimate of the overall test quality in terms of defect level and yield. However, the associated surging test time due to increased SRAM capacity is becoming a major challenge when testing either standalone or embedded SRAMs. ... View full abstract»

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  • Application specific DRAMs Today

    Publication Year: 2003, Page(s):7 - 13
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (275 KB) | HTML iconHTML

    DRAMs have historically been high volume, standard, commodity memories. Today with many high volume applications having differing requirements, DRAMs are becoming more application specific. This talk discusses a variety of application specific DRAMs including those with high speed interfaces such as the DDR and DDRII SDRAM and those with speed enhancing internal architectures; DRAMs with low power... View full abstract»

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  • Cost optimum embedded DRAM design by yield analysis

    Publication Year: 2003, Page(s):20 - 24
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (245 KB) | HTML iconHTML

    We study on cost optimum embedded DRAM interconnect technologies by using a simple VLSI particle-induced fault simulator modified for the embedded DRAM macro. The fault simulator is applied to an assumed 4-Mbit DRAM macro production process with DRAM interconnect technologies of DRAM 1/2 pitch 115 nm and ASIC 1/2 pitch of from 115 nm to 500 nm (peripheral circuits). The DRAM macro is included in a... View full abstract»

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  • Applying defect-based test to embedded memories in a COT model

    Publication Year: 2003, Page(s):72 - 77
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (224 KB) | HTML iconHTML

    Defect-based testing for digital logic concentrates primarily on methods of test application, including for example at-speed structural tests and IDDQ testing. In contrast, defect-based testing for memory concentrates on defect analysis of key parts of the layout and the development of application-independent patterns that will test for likely failures. Testing hundreds of embedded memories on tod... View full abstract»

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  • A testability-driven optimizer and wrapper generator for embedded memories

    Publication Year: 2003, Page(s):53 - 56
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (229 KB) | HTML iconHTML

    Memory cores (especially SRAM cores) used on a system chip usually come from a memory compiler. Commercial memory compilers have their limitation-a large memory may need to be implemented with multiple small memories, if generated by memory compilers. In this paper we introduce a testability-driven memory optimizer and wrapper generator that generates BISTed embedded memories by using a commercial... View full abstract»

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  • Systematic memory test generation for DRAM defects causing two floating nodes

    Publication Year: 2003, Page(s):27 - 32
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (322 KB) | HTML iconHTML

    The high complexity of the faulty behavior observed in DRAMs is caused primarily by the presence of internal floating nodes in defective DRAMs. This paper describes a new analysis method to apply electrical simulation for investigating the faulty behavior resulting from defects causing two floating nodes within the memory. The paper also presents the results of a simulation study performed on bit ... View full abstract»

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  • ITRS commodity memory roadmap

    Publication Year: 2003, Page(s):61 - 63
    Cited by:  Papers (5)  |  Patents (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (209 KB) | HTML iconHTML

    The ITRS (International Technology Roadmap for Semiconductors) roadmap is updated on a yearly basis to forecast industry silicon trends. The ITRS Test Working Group (TWG) identifies the key trends that will have an impact on device test and summarizes them to provide direction to test suppliers. The commodity memory roadmap is a key part of that forecast and covers discrete and embedded DRAM and F... View full abstract»

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  • A fault primitive based analysis of linked faults in RAMs

    Publication Year: 2003, Page(s):33 - 39
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (374 KB) | HTML iconHTML

    Linked faults are very important for memory testing because they reduce the fault coverage of the tests. Their analysis has proven to be a source for new memory tests, characterized by an increased fault coverage for a given test time. This paper presents an analysis of linked faults, based on the concept of fault primitives, such that the whole space of linked faults is investigated, accounted fo... View full abstract»

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  • Output timing measurement using an Idd method

    Publication Year: 2003, Page(s):43 - 46
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (253 KB) | HTML iconHTML

    The exact placement of the data output eye for high speed single and double data rate (SDR, DDR) synchronous dynamic random access memories (SDRAM) allows high speed operation. For the timing measurement method via current presented in this paper the tester drives data at the same time as the device. The current consumption of the device is depending on the overlap of the tester output waveform an... View full abstract»

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  • Records of the 2003 IEEE International Workshop on Memory Technology, Design and Testing

    Publication Year: 2003
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (236 KB)

    The following topics are dealt with: application specific DRAMs; cost optimum embedded DRAM design; memory test generation for DRAM defects; linked faults analysis in RAMs; reducing test time of embedded SRAMs; testability-driven optimizer and wrapper generator for embedded memories; ITRS commodity roadmap; electrical simulation model for the Chalcogenide phase-change memory cell. View full abstract»

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  • Author index

    Publication Year: 2003, Page(s): 95
    Request permission for commercial reuse | PDF file iconPDF (148 KB)
    Freely Available from IEEE