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On-Line Testing Symposium, 2003. IOLTS 2003. 9th IEEE

Date 7-9 July 2003

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Displaying Results 1 - 25 of 48
  • Introducing SW-based fault handling mechanisms to cope with EMI in embedded electronics: are they a good remedy?

    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (222 KB) |  | HTML iconHTML  

    We summarize a study on the effectiveness of two software-based fault handling mechanisms in terms of detecting conducted electromagnetic interference (EMI) in microprocessors. One of these techniques deals with processor control flow checking. The second one is used to detect errors in code variables. In order to check the effectiveness of such techniques in RF ambient, an EIC 61.000-4-29 normative-compliant conducted RF-generator was implemented to inject spurious electromagnetic noise into the supply lines of a commercial off-the-shelf (COTS) microcontroller-based system. Experimental results suggest that the considered techniques present a good effectiveness to detect this type of faults, despite the multiple-fault injection nature of EMI in the processor control and data flows, which in most cases result in a complete system functional loss (the system must be reset). View full abstract»

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  • An efficient BIST scheme for high-speed adders

    Page(s): 89 - 93
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (281 KB) |  | HTML iconHTML  

    In this paper we present a new pseudorandom BIST scheme for high-speed adders. Under this scheme an adder is simultaneously used as a test pattern generator and as a response compactor during its own testing. The main advantages of the proposed scheme, compared to prior methods, are minimal performance penalty, small hardware overhead and the benefits of at-speed testing. View full abstract»

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  • An evaluation of built-in vs. off-chip strategies for online transient current testing

    Page(s): 178 - 182
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (685 KB) |  | HTML iconHTML  

    We evaluate the possibilities of transient current testing practical implementation by comparing the transient supply current signature at the external circuit supply pins to its internal behavior. To do this we develop and analyze a hierarchical power-grid equivalent circuit to evaluate the supply current frequency components and their distribution over the power/ground grid hierarchy. This is a key step to determine the feasibility of on-chip vs. off-chip idd(t) strategies and their successive application to online testing. View full abstract»

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  • Crosstalk effect minimization for encoded busses

    Page(s): 214 - 218
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (346 KB) |  | HTML iconHTML  

    In this paper we present a technique which allows to reduce the crosstalk-induced delay within busses implementing an error detecting/correcting code. This technique is based on the observation that the maximum delay on an encoded bus is usually due to the check bits that are added to provide the desired error detection/ tolerance ability. These bits, in fact, are computed from the bus information bits by an ad hoc encoder, which adds an extra delay to the crosstalk-induced bus delay. We will show that, by proper placement of the lines carrying the information with respect to those carrying the check bits, it is possible to reduce the effective coupling capacitance due to the Miller effect among adjacent lines. This allows a reduction of propagation delay which, depending on the implemented code, can overcome the 20% with respect to the conventional placement of encoded busses. View full abstract»

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  • Synthesis of low-cost parity-based partially self-checking circuits

    Page(s): 35 - 40
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (348 KB) |  | HTML iconHTML  

    A methodology for the synthesis of partially self-checking multilevel logic circuits with low-cost parity-based concurrent error detection (CED) is described. A subset of the inputs of the circuit is selected to realize a simple characteristic function such that CED is disabled whenever the inputs belong to the OFF-set of the characteristic function. This don't-care space in the operation of the CED circuitry is used to optimize the CED circuitry during synthesis. It is shown that this methodology is very effective at targeting faults with a high sensitization probability. Experimental results show that the proposed approach, which is of special interest in applications where a low-cost CED solution is desired, achieves a significant reduction in the error rate in logic circuits. View full abstract»

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  • Memory built-in self-repair for nanotechnologies

    Page(s): 94 - 98
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (392 KB) |  | HTML iconHTML  

    This paper presents memory built-in self-repair approaches allowing to achieve high yield for defect densities several orders of magnitude higher than in current technologies. Such repair schemes illustrate that we could build memories in nanoelectronic technologies that are subject to very high defect densities. View full abstract»

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  • Power consumption of fault tolerant codes: the active elements

    Page(s): 61 - 67
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (438 KB) |  | HTML iconHTML  

    On-chip global interconnections in very deep submicron technology (VDSM) ICs are becoming more sensitive and prone to errors caused by power supply noise, crosstalk noise, delay variations and transient faults. Error correcting codes can be employed in order to provide signal transmission with the necessary data integrity. We compared Dual Rail encoding versus Hamming with respect to power consumption of the bus wires themselves (passive capacity model) [Rossi et al., 2002]. In this paper we analyze the contribution of the active elements of both coding schemes. We first present a detailed analysis of the power consumption of an encoded bus, taking into account the bus wires (with mutual capacitances, drivers, repeaters and receivers), as well as the encoding/decoding circuitry. Then we compare the two considered coding technique with respect to the power consumption, and we show how different tradeoffs can be achieved. Our analysis is based on a realistic bus structure, implemented in a 0.13μm CMOS technology. View full abstract»

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  • InTeRail: using existing and extra interconnects to test core-based SOCs

    Page(s): 219 - 223
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (256 KB) |  | HTML iconHTML  

    A flexible test access mechanism (TAM) for embedded cores and their interconnects in a System-on Chip (SOC) environment is presented. It targets core testing parallelism and reduced test application time while explicitly taking into consideration area and performance issues. The TAM primarily uses core interconnects but also allows for extra interconnects. The DFT hardware can be implemented either at the SOC or at the core level. It combines features of TAMs that have been designed for low test application time and those for SOC area and performance criteria. View full abstract»

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  • A design method for embedded self-testing t-UED and BUED code checkers

    Page(s): 43 - 48
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (295 KB) |  | HTML iconHTML  

    A novel method for designing t-UED and BUED code checkers is presented. In particular we consider Borden codes for t = 2k - 1, Bose and Bose-Lin codes. The design technique for all three checker types is mainly based on averaging weights and check symbol values of the code words. The checkers have a simple and regular structure that does not depend on the set of code words that is provided by the circuit under check. The checkers are very well suited for use as embedded checkers since they are self-testing with respect to single stuck-at faults and almost all combinational faults in a single cell under very weak assumptions. All three checker types can be tested with only 2 or 3 code words. View full abstract»

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  • Accurate and efficient analysis of single event transients in VLSI circuits

    Page(s): 101 - 105
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (263 KB) |  | HTML iconHTML  

    Single event transients (SETs) on combinational gates are becoming an issue in deep sub-micron technologies, thus efficient and accurate techniques for assessing their impact are strongly required. This paper presents a new technique that embeds time-related information in the topology of the analyzed circuit, allowing evaluating the effects of SETs via zero-delay simulation instead of timed simulation. The analysis of complex designs becomes thus possible at a very limited cost in terms of CPU time. The paper reports results showing how the proposed method can be effectively used to analyze complex designs. View full abstract»

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  • A modulo p checked self-checking carry select adder

    Page(s): 25 - 29
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (297 KB) |  | HTML iconHTML  

    In this paper a new self-checking carry select adder is proposed. The duplicated adder blocks which are inherent to a carry select adder without error detection are checked modulo 3. Compared to a carry select adder without error detection the delay of the MSB of the sum of the proposed adder does not increase. Compared to a self-checking duplicated carry select adder the area is reduced by 20%. No restrictions are imposed on the design of the adder blocks. View full abstract»

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  • Low-cost, on-line software-based self-testing of embedded processor cores

    Page(s): 149 - 154
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (269 KB) |  | HTML iconHTML  

    A comprehensive online test strategy requires both concurrent and non-concurrent fault detection capabilities to guarantee SoCs's successful normal operation in-field at any level of its life cycle. While concurrent fault detection is mainly achieved by hardware or software redundancy, like duplication, non-concurrent fault detection, particularly useful for periodic testing, is usually achieved through hardware BIST. Software-based self-test has been recently proposed as an effective alternative to hardware-based self-test allowing at-speed testing while eliminating area, performance and power consumption overheads. In this paper we focus on the applicability of software-based self-test to non-concurrent on-line testing of embedded processor cores. Low-cost in-field testing requirements, particularly small test execution time and low power consumption guide the development of self-test routines. We show how self-test programs with a limited number of memory references and based on compact test routines provide an efficient low-cost on-line test strategy. View full abstract»

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  • The positive effect on IC yield of embedded fault tolerance for SEUs

    Page(s): 75 - 79
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (378 KB) |  | HTML iconHTML  

    Fault tolerant design is a technique emerging in Integrated Circuits (IC's) to deal with the increasing error susceptibility (Soft Errors, or Single Event Upsets, SEU) caused by e.g. alpha particles. A side effect of these methods is that they also compensate for manufacturing defects (the Hard Errors). Currently, yield engineers focus on perfecting the manufacturing process and designers spend their effort in minimizing the area to increase the yield. In this paper, it is shown that increasing the IC area (by applying fault tolerant design techniques) leads under certain conditions to a better yield (more working dies from a wafer) and lower production cost. This is counter-intuitive for many design and yield engineers. To guide designers in deciding when the fault tolerant techniques are beneficial, break-even points between fault tolerant and regular design are presented as function of IC area, fault tolerant overhead and defect density. View full abstract»

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  • On the probability of detecting data errors generated by permanent faults using time redundancy

    Page(s): 68 - 74
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (300 KB) |  | HTML iconHTML  

    Time redundant execution of tasks and comparison of results is a well-known technique for detecting transient faults in computer systems. However, time redundancy is also capable of detecting permanent faults that occur during or between the executions of two task replicas, provided the faults affect the results of the two tasks in different ways. In this paper, we derive an expression for estimating the probability of detecting data errors generated by permanent faults with time redundant execution. The expression is validated experimentally by injecting permanent stuck-at faults into a multiplier unit of a microprocessor. We use the derived expression to show how tasks can be scheduled to improve the detection probability of errors generated by permanent faults. We also show that the detection capability of permanent faults is low for the Temporal Error Masking (TEM) technique (i.e. triplicated execution and voting to mask transient faults) and may not be increased by scheduling. Thus, we propose complementing TEM with special test tasks. View full abstract»

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  • Designing FPGA based self-testing checkers for m-out-of-n codes

    Page(s): 49 - 53
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (294 KB) |  | HTML iconHTML  

    The paper describes a specific method for designing self-checking checkers for m-out-of-n codes. The method is oriented to the field programmable gate arrays technology and is based on decomposing the sum-of-minterms corresponding to an m-out-of-n code. The self-testing property of the proposed checker is proven for a set of multiple stuck-at faults at input and output poles of a logic cell. An estimated complexity of obtained m-out-of-n checker demonstrates high efficiency of the proposed method. View full abstract»

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  • Separate dual-transistor registers: a circuit solution for on-line testing of transient error in UDMC-IC

    Page(s): 7 - 11
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (336 KB) |  | HTML iconHTML  

    This paper addresses the soft-error problem in UDSM circuits by presenting on-line fault-tolerant circuit design techniques. In our scheme, separate dual transistor (SDT) structure is introduced into the register design as a key component to increase the input-signal stability as well as the robustness of the circuit against the effects of ionizing particles. Our work not only demonstrates the feasibility of its physical implementation, but also shows the cost effectiveness. To compare with other fault-tolerant techniques, ISCAS89 circuits have been synthesized with the SDT standard cells to investigate its cost/timing overheads. Our benchmark comparison reveals its better applicability over two representative techniques (TMR and ECC) for the logic circuits in digital systems. View full abstract»

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  • An improved source design for scan BIST

    Page(s): 106 - 110
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (258 KB) |  | HTML iconHTML  

    Recently, Markov sources were shown to achieve 100% fault efficiency at low area overhead when used as pseudo-random pattern generators in scan BIST. In this paper we give a new method of designing Markov sources. The new design attempts to match probabilities of 1 to 0 and 0 to 1 transitions in consecutive bits of a set of test vectors, taking into account that the transition probabilities may be different for different bit positions. Experimental results show that the proposed method considerably reduces the hardware overhead and test lengths required to achieve 100% fault coverage. View full abstract»

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  • FAUST: fault-injection script-based tool

    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (193 KB) |  | HTML iconHTML  

    The tool described in this paper aims at evaluating the effectiveness of software-implemented fault-tolerant techniques used in safety-critical systems. The target application is stressed with the injection of transient or permanent faults. The user can therefore observe the real behaviour of the application in presence of a fault, and, if necessary, take the appropriate countermeasures. The accent is put on the extreme easiness of the use and the portability on all UNIX platforms. View full abstract»

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  • Automatic toolset for fault tolerant design: results demonstration on a running industrial application

    Page(s): 197 - 201
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (270 KB) |  | HTML iconHTML  

    This paper describes an automatic toolset to validate fault tolerant designs. The toolset has been produced as a demonstrator for the AMATISTA European project (IST project 11762), to test the effectiveness of the new FT (Fault Tolerant) tools, developed as the main target of the project. The toolset has been applied on a typical automotive application already modified by the insertion of FT structures. This paper describes the set-up of the demonstrator and the significant results obtained. View full abstract»

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  • Evaluation of the quality of testing path delay faults under restricted input assumption

    Page(s): 168 - 170
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (270 KB) |  | HTML iconHTML  

    We show that in the case when the set of vector pairs that occur at the input of a combinatorial network in the system environment is restricted (as it is for most applications), the information on such restrictions should be accounted for when evaluating the quality of testing delay faults, especially if the test sequence "mimics" the normal operation, i.e. if only those vector pairs that may occur in normal operation are applied during testing. View full abstract»

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  • On-line error detecting constant delay adder

    Page(s): 17 - 22
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (312 KB) |  | HTML iconHTML  

    Fault tolerance requires the inclusion of redundant information. In this paper an on-line error detecting adder is presented in which the redundant information serves a dual purpose. It provides fault tolerance during the arithmetic operations while also providing a method by which addition is constrained to become a constant delay operation regardless of the word size of the operands. View full abstract»

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  • On-line testable decimation filter design for AMS systems

    Page(s): 83 - 88
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (419 KB) |  | HTML iconHTML  

    This paper presents an implementation of on-line testing techniques for the case of a decimation filter. The decimation filter is used in a ΣΔ analogue-to-digital converter that is in turn used in a built-in-self-test (BIST) circuitry for mixed-signal core testing. Thus, the filter itself must be self-testable. Three different one-line self-test techniques are studied and compared for a 0.18 μm CMOS technology. The first one uses a non-concurrent structural test technique and the others are both based on semi-concurrent test methodologies. In all cases, the on-line test circuitry is automatically synthesized and exploits the idle time of the functional units to apply either a structural or a functional test. View full abstract»

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  • Foundation of combined datapath and controller self-checking design

    Page(s): 30 - 34
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (375 KB) |  | HTML iconHTML  

    We consider the problem of designing self-checking controllers for applications with sequential datapaths. Firstly we compare encoded and unencoded (one-hot) controller implementations and we argue that self-checking of encoded control signals is not sufficient in terms of testability. Subsequently, we present four alternative controller self-checking schemes, based both on parity and on the observation that a self-checking data path can be employed for control path self-checking as well, by exploiting intrinsically secure control states. We discuss the properties of each of them, and present a few experimental results. View full abstract»

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  • An analog checker with input-relative tolerance for duplicate signals

    Page(s): 54 - 58
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (280 KB) |  | HTML iconHTML  

    We discuss the design of a novel analog checker that monitors two duplicate signals and provides a digital error indication when their absolute difference is unacceptably large. The key feature of the proposed checker is that it establishes a test criterion that is dynamically adapted to the magnitude of its input signals. We demonstrate that, when this checker is utilized in concurrent error detection, the probability of both false negatives and false positives is diminished. In contrast, checkers implementing a static test criterion may only be tuned to achieve efficiently one of the aforementioned objectives. Likewise, when the proposed checker is employed for off-line test purposes, it results simultaneously in both high yield and high fault coverage. View full abstract»

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  • Radiation test methodology for SRAM-based FPGAs by using THESIC+

    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (188 KB) |  | HTML iconHTML  

    Benefits resulting from the adoption of SRAM-based FPGAs as design target technology in space applications are manifold. These devices, however, exhibit a potentially high susceptibility to single event upsets (SEU) due to the presence of a large number of configuration memory cells. As fault injection alone is not able to reach every circuitry inside FPGA, radiation ground testing is mandatory in order to perform the analysis on a larger set of SEU upsets. This paper presents a radiation test methodology for Xilinx Virtex FPGAs based on the THESIC+ system. View full abstract»

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