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Rapid Systems Prototyping, 2003. Proceedings. 14th IEEE International Workshop on

Date 9-11 June 2003

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Displaying Results 1 - 25 of 33
  • Proceedings 14th IEEE International Workshop on Rapid Systems Prototyping

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  • Synthesis of LOTOS specification of the IEEE-1394 firewire protocol

    Page(s): 86 - 92
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (364 KB) |  | HTML iconHTML  

    Rigorous techniques must be embraced in order to reduce the risk of designing bug-affected devices. Use of formal techniques solves several design matters, but often synthesis is not able to maintain properties of specification. In this paper a direct-synthesis method of a formal specification is discussed and its application to the IEEE-1394 protocol synthesis is presented. View full abstract»

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  • Author index

    Page(s): 241 - 242
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    Freely Available from IEEE
  • Emulation of analog components for the rapid prototyping of wireless baseband systems

    Page(s): 172 - 178
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    The increasing complexity of modern wireless baseband systems demands the use of rapid prototyping methodologies to provide an early estimation of system functionality and performance. In order to achieve an efficient hardware emulation, the complete system including the analog part should be prototyped. In this work we present synthesizable descriptions of a communication channel module and a sigma delta modulator, suitable for fundamental emulation of wireless baseband environments. By avoiding time-intensive hardware/software cosimulation, a great speedup of the system verification can be attained. In order to assist the designer and speed up the design process we also created an environment for automatically customizing the modules according to a specific scenario. View full abstract»

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  • Simulation and analysis of embedded DSP systems using Petri nets

    Page(s): 64 - 70
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    In this paper, we present a simulation and architectural analysis technique of embedded DSP systems modeled using the MASIC methodology. MASIC is a grammar based methodology, which clearly separates the communication from the computation part of the model and begins with an abstract level of modeling. Computations in embedded blocks are carried out using C functions and the flow of data among the blocks is expressed by the communication protocol written in the MASIC grammar description. Later, the abstract model is refined to a cycle true model. Different architectural decisions, like the bus architecture or the memory organization added during the refinement process, significantly affect the system performance. We use a Petri net based approach that provides the necessary synchronization to perform co-simulation and helps to evaluate the effects of architectural decisions. The correctness of the protocol description is verified using Petri net based boundedness and conservation analysis. View full abstract»

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  • Evaluation of middleware architectures in achieving system interoperability

    Page(s): 108 - 116
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (285 KB) |  | HTML iconHTML  

    The current state-of-the-art for integration of heterogeneous systems involves manually resolving differences in data modeling and mapping for each interface between systems, in an inherently customized manner. The first step in advancing the state-of-the-art is to develop a general model of the interoperation among systems. Keeping this as the broad objective, in this paper we have worked on classification of modeling differences among autonomously developed, heterogeneous systems as differences in what is being modeled (view) and differences in how the modeled information is represented (representation). Further to this, a set of criteria was selected for conducting an evaluation of existing interoperability approaches in order to compare their success in resolving such heterogeneities. These criteria were used to evaluate seven of the leading approaches for achieving interoperability among independently developed systems. The limitations of these approaches against the criteria provided the motivation for subsequent development of a general model of the interoperation among systems, the Federation Interoperability Object Model (FIOM) used in the Object-Oriented Method for Interoperability (OOMI), to address these shortcomings (Young et al., 2002). View full abstract»

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  • Rapid design and analysis of communication systems using the BEE hardware emulation environment

    Page(s): 148 - 154
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    This paper describes the early analysis and estimation features currently implemented in the Berkeley Emulation Engine (BEE) system. BEE is an integrated rapid prototyping and design environment for communication and digital signal processing (DSP) systems, consisting of four multi-FPGA based processing units, each capable of emulating 10 million ASIC (application specific integrated circuits) equivalent gates at an overall system clock rate up to 60 MHz. This translates to over 600 billion 16 bit additions (operations) per second on one unit. An integrated software design flow enables the users to specify the design using a data-flow diagram, then automatically generates both the FPGA implementation for real-time rapid prototyping and a cycle-accurate, bit-true, and functionally equivalent ASIC implementation. For system-level design, the BEE hardware and software support rapid design turn-around and early performance analysis, without full synthesis or hardware mapping, from the high-level design entry. A case study detailing a turbo-decoder explains how the processing capability of the emulator can be utilized to verify a design using one billion input vectors with a speed-up factor exceeding 106 over equivalent software simulation methods. View full abstract»

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  • A versatile framework for FPGA field updates: an application of partial self-reconfiguration

    Page(s): 117 - 123
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (320 KB) |  | HTML iconHTML  

    Field programmable gate arrays (FPGAs) provide an attractive solution to developers needing custom logic for short time-to-market products. Products embedding FPGA system-on-chip solutions have the advantage in that they can be updated once deployed. New FPGA firmware may be loaded via manufacturer-supplied memory devices or remotely via a network connection. Recent FPGAs allow for self-reconfiguration, where the user-FPGA fabric can internally modify its own configuration data. Using self-reconfiguration, configuration control protocols can be implemented in user logic. This allows new FPGA programming methods to be designed. We propose a versatile partial self-reconfiguration framework for FPGA field updates that customizes to specific applications, reduces reconfiguration times, and minimizes the need for external hardware. The framework provides flexibility in media sources and design security. A prototype using this framework is demonstrated on a Xilinx Virtex-II FPGA. View full abstract»

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  • xDSL systems prototyping using a flexible emulation environment

    Page(s): 194 - 200
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    In this paper we describe the methodology and architecture of a flexible modular environment for prototyping data transmission systems and its application on xDSL systems. The development environment is based on custom and commercially available software tools and a custom hardware emulation platform for mapping the basic data-pump modules of xDSL systems into hardware/software functional modules. The road-map from a high-level xDSL system model to the actual prototype is based on the progressive substitution of high-level submodules of the initial model with their respective hardware/software counterparts, and their integration into a complete functional system. A library of custom blocks is used for data exchange and synchronization between the high-level model and the emulation platform, and for real-time visualization of the critical parameters of the emulated system as well. The application of the proposed development environment in the implementation and testing of an emulator of a bundle of DSL lines and of a centralized bit-loading algorithm for multicarrier ADSL systems is also described. View full abstract»

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  • Comparative rapid prototyping: a case study

    Page(s): 210 - 217
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    This paper presents a case study that explores the effectiveness of parallel conceptualization efforts to expose potential requirements issues in rapid prototyping. The case study consists of developing and comparing five design alternatives to model the safety-critical computer assisted resuscitation algorithm (CARA) software for a casualty intravenous fluid infusion pump using a set of computer aided Software Engineering Automated Tools (SEATools). The prototyping effort showed that users can efficiently create/modify multiple parallel models and reason about their complexity using SEATools. The study also illustrates the usefulness of comparative rapid prototyping to identifying strengths and weaknesses of alternative designs, improving the final result. The case study also exposed numerous omissions and discrepancies in the requirements document and highlighted useful future enhancements for SEATools. View full abstract»

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  • A new approach of a self-timed bit-serial synchronous pipeline architecture

    Page(s): 71 - 77
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (308 KB) |  | HTML iconHTML  

    Power consumption, area minimization as well as signal delay and reconfiguration with respect to rapid system prototyping make increasing demands on chip design. While design space can be reduced by bit-serial operators, long control lines in synchronous bit-serial architecture usually affect the performance of the circuit. This paper presents a new synchronous, fully reconfigurable self-timed bit-serial and fully interlocked pipeline architecture. Through a one-hot implementation of the central control engine, we realize the local control of the operators. Furthermore, we developed a specialized routing component that allows the reconfiguration of the implementation w.r.t. rapid system prototyping. This realization of the developed architectures provides the freedom of a rapid system prototyping of a given problem. To our knowledge, this is the second paper detailing the implementation of a fully interlocked synchronous architecture after the one by Jacobson et al. (2002) and the first which does not rely on gated clocks to realize the local control of the operators. We prove the usefulness of our architecture by an example implementation of a given problem on a Xilinx FPGA. The architecture is optimized for the use in embedded systems to control mechatronic systems, but can also be employed in other fields of application. View full abstract»

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  • Design and prototyping a Fast Hadamard Transformer for WCDMA

    Page(s): 134 - 140
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    In this paper, the design and implementation of a Fast Hadamard Transformer (FHT) on a field programmable gate array (FPGA) is described. Two possible schemes which use 256 and 16 chip input sequences are compared on a Xilinx Virtex-E XCV1000E FPGA. The results indicate that the 16 chip sequence achieves 90% reduction in hardware resources and more than double the maximum frequency of operation as compared to 256 chip sequences. An application of the proposed FHT design used to perform cell search for Wideband Code Division Multiple Access (WCDMA) system is also presented. View full abstract»

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  • Prototype-based tests for hybrid reactive systems

    Page(s): 78 - 84
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    Model-based testing relies on the use of behavior models to automatically generate sequences of inputs and expected outputs. These sequences can be used as test cases to the end of both validating the model and also verifying an actual system. In the automotive domain, many systems are reactive and exhibit continuous as well as discrete dynamics. This leads to an explosion of the model state space, which makes automated test case generation difficult, and because of imprecisions in the continuous parts, requires an adequate treatment of fuzziness both in the dimensions of time and values. We report on experiments with model-based testing in the automotive domain. Roughly, the idea is to use two separate models, a discrete model as an abstract description of relevant scenarios, and a discrete-continuous model to produce reference outputs for the actual system. As an application example we use a fictitious autonomous cruise control system (ACC). We argue that rapid prototyping approaches fit well with the use of models that serve as specifications, as a basis for test case generation, or as a basis for production code generation. View full abstract»

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  • i-CAD: a rapid prototyping CAD tool for intranet design

    Page(s): 16 - 23
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    This paper presents i-CAD, a novel computer-aided design tool for intranets that support data-intensive multimedia applications. We have formulated the intranet design problem as a combined optimization problem, consisting of a network architecture design problem, server placement problem and file allocation problem. Concurrently, i-CAD determines the network strategy, interconnection hardware required, number and locations of file servers, and the static file allocation. While many optimization approaches described in the literature involve abstract networks, i-CAD is technology-relative, designing a complete network architecture along with selected components, using a database of current network technologies along with their costs and performances. An evolutionary approach is used to search the design space for good solutions. The experimental results for several large (65 to 150 nodes) intranet architecture problems show the effectiveness of i-CAD in finding good designs in few minutes. View full abstract»

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  • A new specification methodology for embedded systems based on the π-calculus process algebra

    Page(s): 26 - 32
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (461 KB) |  | HTML iconHTML  

    This paper presents a formal specification methodology for embedded systems which is founded upon the π-calculus process algebra. The domain model underlying this newly developed methodology identifies eight categories of system building blocks each of which describes a particular system facet. Based on these building blocks complex embedded systems can be specified, refined, and formally verified. The theories underlying both system specification and refinement are explained and exemplified by applications from the field of aeronautics. View full abstract»

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  • Rapid exploration of pipelined processors through automatic generation of synthesizable RTL models

    Page(s): 226 - 232
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    As embedded systems continue to face increasingly higher performance requirements, deeply pipelined processor architectures are being employed to meet desired system performance. System architects critically need modeling techniques to rapidly explore and evaluate candidate architectures based on area, power, and performance constraints. We present an exploration framework for pipelined processors. We use the EXPRESSION Architecture Description Language (ADL) to capture a wide spectrum of processor architectures. The ADL has been used to enable performance driven exploration by generating a software toolkit from the ADL specification. In this paper, we present a functional abstraction technique to automatically generate synthesizable RTL from the ADL specification. Automatic generation of RTL enables rapid exploration of candidate architectures under given design constraints such as area, clock frequency, power, and performance. Our exploration results demonstrate the power of reuse in composing heterogeneous architectures using functional abstraction primitives allowing for a reduction in the time for specification and exploration by at least an order of magnitude. View full abstract»

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  • Hardware evaluation of low power communication mechanisms for transport-triggered architectures

    Page(s): 141 - 147
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    The requirement for flexibility in IP-based designs increases the attractiveness of transport-triggered architectures as a suitable alternative to classic operation-triggered processors. Since the performance of these architectures strongly depends on the communication mechanism, the optimization of the bus structure represents a major design concern. In this work, a rapid prototyping methodology is employed in order to compare the power consumption and hardware requirements of several competing communication alternatives. Therefore, a generic test processor has been prototyped onto an FPGA. By monitoring the switching activity and bus statistics under realistic operation conditions, a fast and accurate evaluation of different bus coding schemes has been achieved. View full abstract»

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  • Efficient analysis of mixed-signal ASICs for smart sensors

    Page(s): 40 - 46
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    Smart sensor systems usually contain highly integrated mixed-signal ASICs (application specific integrated circuits). The design of such a circuit typically falls into two distinct tasks: the development of a customized analog part and the design of an often custom-specific digital processor core. While the latter is likely to yield first time right silicon, the former usually requires more design iterations. To speed up the design process, independent optimization of both parts is desirable, but hardly possible in conventional designs. This paper proposes several measures to improve the prototyping and evaluation phase of a class of mixed-signal ASICs typical for smart sensors. Specifically, we suggest using a JTAG-like interface to disentangle analog and digital part and enable external data processing by means of an FPGA (field programmable gate arrays). Furthermore, we propose to replace the RAM/ROM blocks of a user-specific controller with a dual-ported RAM to achieve full programmability while at the same time preserving the overall architecture. Both approaches have successfully been used for the design of a smart sensor system for automotive applications. View full abstract»

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  • Cache configuration exploration on prototyping platforms

    Page(s): 164 - 170
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    We describe cache architecture, intended for prototype-oriented IC platforms, that automatically finds the best cache configuration for a particular application. The cache itself can be configured with respect to the total size, associativity, line size, and way prediction. The cache architecture includes an explorer component that efficiently searches the large space of possible configurations for the set of points representing meaningful tradeoffs between performance and energy - the Pareto-optimal set. We provide results of experiments showing that the architecture effectively finds a good set of Pareto points for numerous Powerstone and MediaBench embedded system benchmarks. Our architecture eliminates the need for time-consuming simulations to determine the best cache configuration, and imposes little power overhead and reasonable size overhead. View full abstract»

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  • Marked regulatory graphs: a formal framework to simulate biological regulatory networks with simple automata

    Page(s): 93 - 99
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    In the field of biological regulation, models obtained from experimental biology are usually complex networks of induction and repression between genes. Due to the development of high throughput genomic, it is now necessary to treat large scale networks. The challenge is to automatically analyze their behavior. We propose a formal framework to define these biological regulatory networks. Our model is derived from R. Thomas representation, where a biological regulatory network can be seen as a discrete model. We propose a formal definition of such a representation. We separate the static part (description of the systems) from the dynamic part (we develop two semantics, synchronous or asynchronous, to illustrate our method). A software environment to support this framework is also described. This software, developed to be used by biologists, can be used to rapidly obtain a prototype describing the behavior of the system, for product simulations and to automize proofs of properties. View full abstract»

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  • Rapid prototyping of real-time communication. A case study: interacting robots

    Page(s): 186 - 192
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    The implementation of real-time communication within the design of embedded systems is becoming the real system bottleneck. For this reason the evaluation of the communication characteristics is very essential in an early design stage. In this paper we present an evaluation method for real-time communication based on rapid prototyping. Key points are the ISO/OSI layer conform implementation, exchangeable hardware and software modules and the adaptation of a wide range of real-time protocols. These aspects are implemented and illustrated in our case study: two interacting robots with five degrees of freedom each. View full abstract»

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  • Synthesizing approach for perspective-based architecture design

    Page(s): 218 - 225
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    Architecture is recognized as a critical aspect in the successful development and evolution of software-intensive systems. Explicitly architecting such systems inevitably involves establishing consensus among different stakeholders' concerns. Unfortunately, there are few established approaches for rapidly prototyping architecture to identify key architectural components during the early stakeholder requirements resolution phases of software design. This paper presents an approach for developing a perspective-based architectural design (PBAD) using rapid prototyping. The approach relies on explicit architecting and system composition to provide a set of rules governing the system composition from coarser-grained components. The approach establishes mappings between perspective designs of recurring architectural facilities that implement compositional patterns. Finally, it provides a rationale for treating dependability as a set of semantic constraints localized on compositional patterns. View full abstract»

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  • Embedded application prototyping on a communication-restricted reconfigurable platform

    Page(s): 33 - 39
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    As the complexity of SoC is increasing, prototyping becomes more and more suitable than simulation to validate the design. Reconfigurable platform is the solution to attain this prototyping in realistic cost and time. Unfortunately, most of the reconfigurable platforms have fixed communication network. This property becomes a restriction to implement the nowadays applications which have very complex and sophisticated communication network. In this paper, we present a novel approach for embedded application prototyping using reconfigurable platform under communication restriction. The effectiveness of our approach is illustrated through an application example using an ARM Integrator platform. View full abstract»

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  • An efficient methodology and semi-automated flow for design and validation of complex digital signal processing ASICS macro-cells

    Page(s): 56 - 63
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    We present a methodology and design flow for signal processing application specific integrated circuit macro-cells. The key features of the methodology are the mastering the complexity of design, the increasing of reuse factor and the early error detection. It takes advantages of a derivative designs, a signal processing modularity, generic modeling and combines both levels of abstraction, in order to produce an efficient architecture. The flow includes a fast verification platform that drives both algorithm and architecture validation in an efficient way. We illustrate the effectiveness of the proposed methodology by a significant industrial application. Experimental design results indicate strong advantages of the proposed schemes. View full abstract»

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  • Rapid prototyping and incremental evolution using SLAM

    Page(s): 201 - 208
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    The paper shows the outlines of the SLAM system that allows for an effective use of Formal Methods (FM) in Rapid Application Development (RAD) and other prototyping processes. The SLAM system, includes an expressive object oriented specification language and a development environment that, among other features, is able to generate efficient and readable code in a high level object oriented language (Java, C++, ...). SLAM is able to generate prototypes that can be used to validate the requirements with the user. The additional advantage is that the prototype is not throw-away because most part of the generated code can be directly used and the other part can be optimised with the additional help of assertions automatically included. View full abstract»

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