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Multiple-Valued Logic, 2003. Proceedings. 33rd International Symposium on

Date 16-19 May 2003

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Displaying Results 1 - 25 of 59
  • Iterative symmetry indices decomposition for ternary logic synthesis in three-dimensional space

    Page(s): 139 - 145
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (362 KB) |  | HTML iconHTML  

    This paper introduces the implementation of the Iterative Symmetry Indices Decomposition (ISID) for the synthesis of ternary three-dimensional logic circuits. The synthesis of regular two-dimensional circuits using ISID has been introduced previously, and the synthesis of area-specific circuits using ISID has been demonstrated The new method is useful for the synthesis of functions using three-dimensional regular logic circuits whenever volume-specific layout constraints have to be satisfied. View full abstract»

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  • Bidirectional data transfer based asynchronous VLSI system using multiple-valued current mode logic

    Page(s): 99 - 104
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (645 KB) |  | HTML iconHTML  

    A new asynchronous data transfer scheme using multiple-valued 2-color 1-phase coding, called a bidirectional data transfer scheme, is proposed for a high-performance and low-power VLSI system. Valid data signals of "0" or "1" are represented by binary dual-rail complementary codes, (0,1) and (1,0), and "ODD" and "EVEN" colors are represented by binary dual-rail codes, (0,0) and (1,1), respectively. Control signals from both a transmitter and a receiver are represented by dual-rail multiple-valued coding with superposition of data and color signals. The use of dual-rail coding makes it easy to detect EVEN and ODD information by calculating the sum of dual-rail codes, even when data and color information are mixed on the same wires in asynchronous data transfer Since a linear-summation can be implemented by wiring without active devices in multiple-valued bidirectional current-mode circuitry, the proposed circuit for asynchronous control becomes simple. It is evaluated in a 0.18 μm CMOS technology that the switching speed of the proposed asynchronous data transfer scheme is about 1.6-times faster than that of the corresponding binary CMOS implementation under the normalized power dissipation. View full abstract»

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  • Spectral transforms of mixed-radix MVL functions

    Page(s): 329 - 333
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (525 KB)  

    Mixed-radix "Multiple Valued Logic" (MVL) functions are assumed to be finite and discrete-valued and depend on a finite-valued variable support set {xi,...,xj} such that xi is qi-valued and xj is qj-valued with qi ≠ qj. The spectra of such MVL functions is of interest to circuit designers and automated design tool researchers and developers. Spectral transforms are described that are applicable to such functions over the elementary additive (mod(p)) Abelian groups. Three formulation of such transforms are described here; a linear transformation matrix derived front a group character table, a Kronecker-based expansion allowing for a 'fast' transform algorithm, and a Cayley graph spectrum computation. It is shown that a particular spectral transformation of a discrete mixed-radix function over Z6 is equivalent to that over Z2 × Z3 within a permutation. Also, it is shown that a Cayley graph may be formed over Z6 with a generator corresponding to the discrete function of interest. View full abstract»

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  • An extension of ternary majority function and its application to evolvable system

    Page(s): 17 - 23
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (498 KB) |  | HTML iconHTML  

    Multiple-valued majority functions were defined in 1980 as a group which differ from; threshold functions, but the majority functions only consist of a subset of Kleenean functions. This paper defines an extension of the ternary majority function using cyclic operation to I/O values of the function. The extended ternary majority functions are functionally complete on a ternary logic system. We apply this function to synsthesize evolvable logic system. The goal of the discussion in the latter half is to devise a method of representing any ternary logic function using the extended ternary majority functions. GA is used as a tool, and an advanced method applicable to many variable case is proposed together with some experiments. View full abstract»

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  • Multi-output Galois Field Sum of Products synthesis with new quantum cascades

    Page(s): 146 - 153
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (361 KB) |  | HTML iconHTML  

    Galois Field Sum of Products (GFSOP) leads to efficient multi-valued reversible circuit synthesis using quantum gates. In this paper, we propose a new generalization of ternary Toffoli gate and another new generalized reversible ternary gale with discussion of their quantum realizations. Algorithms for synthesizing ternary GFSOP using quantum cascades of these gates are proposed In both the synthesis methods, 5 ternary shift operators and ternary swap gate are used We also propose quantum realizations of 5 ternary shift operators and ternary swap gate. In the cascades of the new ternary gates, local mirrors, variable ordering, and product ordering techniques are used to reduce the circuit cost. Experimental results show that the cascade of the new ternary gates is more efficient than the cascade of ternary Toffoli gates. View full abstract»

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  • Generation of the Post Lattice by irreducible clones

    Page(s): 309 - 314
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (358 KB) |  | HTML iconHTML  

    Clones of logic functions form an algebraic lattice, which in the case of Boolean functions was completely described by E.L.Post in 1941. This lattice, often referred to as the Post Lattice, has been well studied from various angles, particularly, the generation of the Post Lattice by its subsets. This paper discusses the results about clones that are irreducible by means of meet- and/or join-operations of the lattice. We show that the join-irreducible clones generate the Post Lattice, and dually, the meet-irreducible clones generate the Post Lattice. We present a complete description of such generation in both cases. We observe that any clone can be presented as a join or meet of at most two irreducible clones. In the former case each clone is the join of at most four join-irreducible clones and in the latter case each clone is the meet of at most three meet-irreducible ones. View full abstract»

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  • CTL model-checking over logics with non-classical negations

    Page(s): 293 - 300
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (478 KB) |  | HTML iconHTML  

    In earlier work [9], we defined CTL model-checking over finite-valued logics with De Morgan negation. In this paper, we extend this work to logics with intuitionistic, Galois and minimal negations, calling the resulting language χCTL. We define χCTL operators and show that they can be computed using fixpoints. We further discuss how to extend our existing multi-valued model-checker χChek [8] to reasoning over these logics. View full abstract»

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  • Fast algorithm for computing spectral transforms of Boolean and multiple-valued functions on circuit representation

    Page(s): 334 - 339
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (439 KB) |  | HTML iconHTML  

    In this paper we present a fast algorithm for computing the value of a spectral transform of Boolean or multiple-valued functions for a given assignment of input variables. Our current implementation is for arithmetic transform, because our work is primarily aimed at optimizing the performance of probabilistic verification methods. However, the presented technique is equally applicable for other discrete transforms, e.g. Walsh or Reed-Muller transforms. Previous methods for computing spectral transforms used truth tables, sum-of-product expressions, or various derivatives of decision diagrams. They were fundamentally limited by the excessive memory requirements of these data structures. We present a new algorithm that partitions the computation of the spectral transform based on the dominator relations of the circuit graph representing the function to be transformed. As a result, the presented algorithm can handle larger functions than previously possible. View full abstract»

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  • Compact representations of logic functions using heterogeneous MDDs

    Page(s): 247 - 252
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (323 KB) |  | HTML iconHTML  

    In this paper we propose a compact representation of logic functions using Multi-valued Decision Diagrams (MDDs) called heterogeneous MDDs. In a heterogeneous MDD, each variable may take a different domain. By partitioning binary input variables and representing each partition as a single multi-valued variable, we can produce a heterogeneous MDD with 16% smaller memory size than a Reduced Ordered Binary Decision Diagram (ROBDD), and with as small memory size as the Free Binary Decision Diagrams (FBDDs). We minimized a large number of benchmark functions to show the compactness of heterogeneous MDDs. View full abstract»

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  • Multiple-valued dynamic source-coupled logic

    Page(s): 207 - 212
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (332 KB) |  | HTML iconHTML  

    A new multiple-valued current-mode (MVCM) integrated circuit based on dynamic source-coupled logic (SCL) is proposed for low-power VLSI applications. The use of a precharge-evaluate logic style makes steady current flow cut off, thereby greatly saving the power dissipation. A combination of SCL and dynamic logic styles makes it possible to reduce the power dissipation while maintaining a highspeed switching capability due to small input-voltage swing with SCL. As a typical example of a high-performance arithmetic circuit, a radix-2 signed-digit adder based on the proposed dynamic SCL is implemented in a 0.18-μm CMOS technology. Its power dissipation is reduced to about 33 percent in comparison with that of the corresponding binary CMOS implementation under the normalized switching delay. View full abstract»

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  • New information on the effectiveness of different reed-muller algebras on the representation of quaternary functions

    Page(s): 33 - 39
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (249 KB) |  | HTML iconHTML  

    Efforts to get reliable data about the efficiency of a set of basis functions in representing a Reed-Muller canonical form with the minimum number of coefficients are frustrated by the long computation times necessary for calculation. Using an integrated suite of utility programs employing fast transforms, we provide statistics on the performance of six different algebras for two, three, four and five variables. Based on experimental results we suggest that the choice of basis functions has only a marginal effect for random samples from the entire function space. In addition we provide evidence which suggests that providing additional polarities has a more and more marginal effect upon efficiency. View full abstract»

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  • A technique for logic design of voltage-mode pass transistor based multi-valued multiple-output logic circuits

    Page(s): 111 - 116
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (334 KB) |  | HTML iconHTML  

    An approach for designing multi-valued logic circuits is proposed in this paper. We also describe a systematic method for implementing a set of binary logic functions, as multi-valued logic functions, and the heuristic algorithms for different stages of the design process are provided along with it. Experimental results are included for a number of benchmark functions and the proposed method has been found to be quite efficient, in terms of number of transistors, in the implementation of some of these functions. The proposed circuits are essentially voltage-mode circuits with multi-valued outputs and in the case of implementing multiple-output binary logic functions this approach produces circuits with reduced number of output pins. The circuits described here are also suitable to be implemented in VLSI technology since they are composed of simple enhancement/depletion mode MOS transistors and pass transistors. View full abstract»

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  • Automated finding of the Willis ring in MR angiography images using fuzzy knowledge base

    Page(s): 83 - 88
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (942 KB) |  | HTML iconHTML  

    This paper proposes an automated method for finding the Willis ring from the human brain MR angiography (MRA) images, which can depict cerebral arteries with high contrast. It strongly helps screening of unruptured cerebral aneurysm in MRA images. The proposed method consists of (1) segmenting cerebral arteries from MRA images, (2) skeletonization of artery trees, and detection of furcations, and (3) finding furcations in the Willis ring using genetic algorithm (GA) based on fuzzy knowledge base (fuzzy KB). Fuzzy KB gives knowledge about the Willis ring that consists of arteries and furcations. GA finds a set of furcations by optimizing an objective function. The objective function used by GA estimates fitness of a set of furcations using fuzzy KB. Our method was first applied to a 3-D phantom data generated by computer simulation. The result demonstrated that our method detected all suitable furcations correctly. Next, it was applied to MRA volume data of two normal healthy volunteers. In any cases, the proposed method detected desired all furcations in the Willis ring. View full abstract»

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  • On intervals of partial clones of Boolean partial functions

    Page(s): 315 - 320
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    We describe the interval of all partial clones that contain all monotonic idempotent Boolean partial functions as well as the interval of all partial clones that contain all idempotent self-dual Boolean partial functions. View full abstract»

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  • Cascade realizations of two-valued input multiple-valued output functions using decomposition of group functions

    Page(s): 125 - 132
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (409 KB) |  | HTML iconHTML  

    This paper considers a method to realize a two-valued input three-valued output function f:{0, 1}n→{0, 1, 2} by using a cascade of four-input cells. Decomposition of a group function is used to find a canonical form. We show that the Walsh spectrum specifies the canonical form, and the number of non-zero coefficients in the spectrum is proportional to the number of cells in the cascade. Finally, we show a design algorithm for a p-valued function f:{0, 1}n→{0, 1, ..., p-1}. The designed cascades are reversible and conservative. View full abstract»

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  • Proposal of four-valued MRAM based on MTJ/RTD structure

    Page(s): 273 - 278
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (332 KB) |  | HTML iconHTML  

    We proposed a novel four-valued magnetic random access memory (MRAM), that uses a double barrier magneto tunnel junction (MTJ) and a resonant tunneling diode (RTD) connected in series. The double barrier MTJ in the form FM1/I/FM2/I/FM1, where FM1 and FM2 represent ferromagnetic materials with different coercive forces and I represents an insulator, respectively, can take four distinct resistance values, depending on the direction of magnetization of each ferromagnetic layer The RTD can increase the tunneling magneto-resistance (TMR) ratio of the MTJ without area penalty due to the nonlinear nature of the NDR characteristics and compactness. The SPICE simulation showed that the RTD with its peak-to-valley current ratio of 12 could increase the effective TMR ratio from 15% to more than 100%. The cell area per bit is 2F2/bit, which is suitable for an ultra-high density memory. View full abstract»

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  • Towards fuzzy type theory

    Page(s): 65 - 70
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (311 KB) |  | HTML iconHTML  

    In the paper, the formal type theory is generalized to fuzzy one. The structure of truth values is assumed to be the IMTL-algebra (on [0, 1], the algebra of left continuous t-norms with involutive negation) since the formulation of FTT based on it preserves the elegancy of classical formulation. Some properties of theories of fuzzy type theory are demonstrated and the completeness saying that each consistent theory has a model is proved. We will follow the way of the development of the classical type theory as elaborated especially by A. Church and L. Henkin. View full abstract»

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  • Recursive evaluation of the generalized Reed-Muller coefficients

    Page(s): 117 - 121
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (349 KB) |  | HTML iconHTML  

    :In this paper, we propose the computation method of GRM (Generalized Reed-Muller) coefficients over GF(2) using triangle cell recursively. GRM expansions of each polarity contain different numbers of product terms. Hence, the minimum form may be selected from them. Many authors have presented various algorithms of calculating the coefficients of GRM expansions under mixed polarities. The method proposed by W. Besslich requires 2n-1×(2n-1) modulo - sums (i.e. Ex-OR)[1], but the method proposed in this paper requires only 2×(the number of modulo-sums for n-1 variable)+3n-1 ones. From this proposed method we can get easily GRM coefficients. View full abstract»

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  • Counter Tree Diagrams for design and analysis of fast addition algorithms

    Page(s): 91 - 98
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    This paper presents a unified representation of fast addition algorithms based on Counter Tree Diagrams (CTDs). By using CTDs, we can describe and analyze various adder architectures in a systematic way without using specific knowledge about underlying arithmetic algorithms. Examples of adder architectures that can be handled by CTDs include Redundant-Binary (R-B) adders, Signed-Digit (SD) adders, Positive-Digit (PD) or carry-save adders, parallel counters (e.g., 3-2 counters and 4-2 counters) and networks of such basic adders/counters. This paper also discusses the CTD-based design and analysis of carry-propagation-free adders using redundant number representation. View full abstract»

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  • New logical and complexity results for Signed-SAT

    Page(s): 181 - 187
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (352 KB) |  | HTML iconHTML  

    We define Mv-formulas as the union of the subclasses of signed CNF formulas known as regular and monosigned CNF formulas, and then define resolution calculi that are refutation complete for Mv-formulas and give new complexity results for the Horn-SAT and 2-SAT problems. Our goal is to use Mv-formulas as a constraint programming language between CSP and SAT, and solve computationally difficult combinatorial problems with efficient satisfiability solvers for Mv-formulas. The results presented in this paper provide evidence that Mv-formulas are a problem modeling language that offers a good compromise between complexity and expressive power. View full abstract»

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  • Fuzzy logic as a basis for a theory of hierarchical definability (THD)

    Page(s): 3 - 4
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    Attempts to formulate mathematically precise definitions of basic concepts such as causality, randomness and probability have a long history. The concept of hierarchical definability that is outlined in the following suggests that such definitions may not exist. Furthermore, it suggests that existing definitions of many basic concepts, among them those of linearity stability, statistical independence and Pareto-optimality, may be in need of reformulation. View full abstract»

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  • Family of fast transforms over GF(3) logic

    Page(s): 323 - 328
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (373 KB) |  | HTML iconHTML  

    New classes of recursive transforms over GF(3) have been introduced here. They are based on simple recursive equations what allows to obtain corresponding fast forward and inverse transforms and very regular butterfly diagrams. The classification is further extended into various transforms with horizontal and vertical permutations. The relations between various classes of introduced ternary transforms are also discussed. View full abstract»

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  • Relationship between UCHT and FFT

    Page(s): 154 - 159
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (293 KB) |  | HTML iconHTML  

    This paper presents relationships among unified complex Hadamard transform (UCHT) whose transformation matrix contains elements ±1 and ±i, Walsh-Hadamard transform (WHT) whose transformation matrix contains elements ±1, and Fast Fourier Transform (FFT). They are all related to each other by a key matrix, and FFT can be computed by using UCHT WHT and some twiddle factor matrices. View full abstract»

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  • Using games for benchmarking and representing the complete solution space using symbolic techniques

    Page(s): 361 - 366
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (302 KB) |  | HTML iconHTML  

    Games often are inherently multi-valued problems and their wide variety offers different graduations of complexity. Moreover a lot of games have a parameter, like board-size that allows to generate differently sized instances of the same problem. All this makes them perfectly suitable for benchmarking in the multi-valued domain. So far the lack of benchmarks in this area often was compensated by transferring problems from binary to multi-valued, but for several application domains this is not adequate. This paper focuses on three games, that we consider suitable for benchmarking. We show the differences in complexity of the games and compare two coding schemes for one of them. All three problems are modeled by symbolic techniques, namely decision diagrams, leading to a complete representation of the solution space. This representation finds several applications, e.g. in objectively analyzing the efficiency of different heuristics on a solution space or to speed up learning algorithms. View full abstract»

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  • Hyperoperations on {0, 1, 2} based on Min, Max, and Universal Literal operations

    Page(s): 11 - 16
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (297 KB) |  | HTML iconHTML  

    This paper will discuss functions with hyperstructure based on Min, Max, and Universal Literal operations on {0, 1, 2}. These three types of operations will be expanded into operations on the set P3 of non-empty subsets of {0, 1, 2}. Then, the paper will define a special type of compositions, called formulas, and will show a necessary and sufficient condition for a function on P3 to be expressed by a formula. View full abstract»

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