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VLSI Test Symposium, 2003. Proceedings. 21st

Date 1-1 May 2003

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  • Proceedings 21st IEEE VLSI Test Symposium

    Publication Year: 2003
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    Freely Available from IEEE
  • VTS'02 Best Panel Award

    Publication Year: 2003, Page(s): 5
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  • VTS'02 Best Paper Award

    Publication Year: 2003, Page(s): 6
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  • Author index

    Publication Year: 2003, Page(s):431 - 432
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    Freely Available from IEEE
  • Energy-efficient logic BIST based on state correlation analysis

    Publication Year: 2003, Page(s):267 - 272
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (315 KB) | HTML iconHTML

    We present a new low-power BIST (built-in-self-test) for sequential circuits. State correlation analysis is first performed on the flip-flop values in the relaxed, compacted sequence for the undetected faults to extract spatial correlations among the flip-flops. The extracted spatial correlation matrix not only provides additional metrics through which the scan order may be altered, but also allow... View full abstract»

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  • BIST reseeding with very few seeds

    Publication Year: 2003, Page(s):69 - 74
    Cited by:  Papers (21)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (736 KB) | HTML iconHTML

    Reseeding is used to improve the fault coverage of pseudo-random testing. The seed corresponds to the initial state of the LFSR before filling the scan chain. The number of deterministic seeds required is directly proportional to the tester storage or hardware overhead requirement. In this paper, we present an algorithm for seed ordering to minimize the number of seeds required to cover a set of d... View full abstract»

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  • Generating complete and optimal march tests for linked faults in memories

    Publication Year: 2003, Page(s):254 - 261
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (323 KB) | HTML iconHTML

    We show that no published march test detects all march-test detectable instances of linked faults in memories. We present necessary and sufficient conditions for detection of single cell linked faults. We identify the set of faults that are undetectable by march tests. We also present sets of faults that dominate all march-test detectable instances of linked multiple cell faults along with the nec... View full abstract»

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  • Built-in reseeding for serial BIST

    Publication Year: 2003, Page(s):63 - 68
    Cited by:  Papers (25)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (794 KB) | HTML iconHTML

    Reseeding is used to improve fault coverage in BIST pseudo-random testing. Most of the work done on reseeding is based on storing the seeds in an external tester. Besides its high cost, testing using automatic test equipment (ATE) makes it hard to test the circuit while in the system. In this paper, we present a technique for built-in reseeding. Our technique requires no storage for the seeds. The... View full abstract»

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  • Test and diagnosis of word-oriented multiport memories

    Publication Year: 2003, Page(s):248 - 253
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (335 KB) | HTML iconHTML

    Conventionally, the test of multiport memories is considered difficult because of the complex behavior of the faulty memories and the large number of inter-port faults. This paper presents an efficient approach for testing and diagnosing multiport RAMs. Our approach takes advantage of the higher access bandwidth due to the increased number of read/write ports, which also provides higher observabil... View full abstract»

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  • Design for self-checking and self-timed datapath

    Publication Year: 2003, Page(s):417 - 422
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (602 KB) | HTML iconHTML

    This work examines the inherent self-checking property of a latch-free dynamic asynchronous datapath (LFDAD) using differential cascode voltage switch logic (DCVSL). Consequently, a highly efficient self-checking (SC) dynamic asynchronous datapath architecture is presented. In this architecture, no hardware needs to be added to the datapath to achieve self-checking. The presented implementation is... View full abstract»

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  • High speed ring generators and compactors of test data [logic IC test]

    Publication Year: 2003, Page(s):57 - 62
    Cited by:  Papers (11)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (341 KB) | HTML iconHTML

    This paper presents a new highly modular architecture of generators and compactors of test patterns. This structure has fewer levels of logic, smaller fan-out, reduced area, and operates at faster speed than external feedback LFSRs, internal feedback LFSRs, and cellular automata, all implementing the same characteristic polynomial. View full abstract»

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  • Application of Saluja-Karpovsky compactors to test responses with many unknowns

    Publication Year: 2003, Page(s):107 - 112
    Cited by:  Papers (65)  |  Patents (33)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (290 KB) | HTML iconHTML

    This paper addresses the problem of compacting test responses in the presence of unknowns at the input of the compactor by exploiting the capabilities of well-known error detection and correction codes. The technique, called i-Compact, uses Saluja-Karpovsky Space Compactors, but permits detection and location of errors in the presence of unknown logic (X) values with help from the ATE. The advanta... View full abstract»

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  • Detecting intra-word faults in word-oriented memories

    Publication Year: 2003, Page(s):241 - 247
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (454 KB) | HTML iconHTML

    This paper improves upon the state of the art in testing word oriented memories. It first presents a complete set of fault models for intra-word coupling faults. Then, it establishes the data background sequence (DBS) for each intra-word coupling fault. These DBSs will be compiled into a (1 + 28 * [log2B]) * n/B test with complete fault coverage of the target faults, where n is the size... View full abstract»

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  • Testing SoC interconnects for signal integrity using boundary scan

    Publication Year: 2003, Page(s):158 - 163
    Cited by:  Papers (20)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (300 KB) | HTML iconHTML

    As the technology is shrinking toward 50 nm and the working frequency is going into the multi Gigahertz range, the effect of interconnects on functionality and performance of system-on-chips is becoming dominant. More specifically, distortion (integrity loss) of signals traveling on high-speed interconnects can no longer be ignored. In this paper, we extend the conventional boundary scan architect... View full abstract»

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  • Fault testing for reversible circuits

    Publication Year: 2003, Page(s):410 - 416
    Cited by:  Papers (21)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (364 KB) | HTML iconHTML

    Irreversible computation necessarily results in energy dissipation due to information loss. While small in comparison to the power consumption of today's VLSI circuits, if current trends continue this will be a critical issue in the near future. Reversible circuits offer an alternative that, in principle, allows computation with arbitrarily small energy dissipation. Furthermore, reversible circuit... View full abstract»

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  • Analyzing crosstalk in the presence of weak bridge defects

    Publication Year: 2003, Page(s):385 - 392
    Cited by:  Papers (11)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (449 KB) | HTML iconHTML

    An extensive simulation study of various combinations of resistive bridges and crosstalk has been performed and several notable properties that have significant implications for test development have been discovered. Scenarios have been identified where a combination of a bridge at one site and a crosstalk at a separate site in its transitive fanout (or vice versa) can cause slowdown/speed-up whos... View full abstract»

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  • Effectiveness of I-V testing in comparison to IDDq tests [IC testing]

    Publication Year: 2003, Page(s):47 - 52
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3195 KB) | HTML iconHTML

    This paper contrasts the novel I-V test criteria with traditional and recent IDDq test methods and compares their test effectiveness. It shows how I-V tests and IDDq tests fare in discriminating between "good" and "bad" dies and how test limits can be set empirically, especially for I-V testing. All results are based on data from an (internal) IBM experiment that was based on a large ASIC manufact... View full abstract»

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  • Analysis and design of optimal combinational compactors [logic test]

    Publication Year: 2003, Page(s):101 - 106
    Cited by:  Papers (20)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (698 KB) | HTML iconHTML

    Scan and logic built-in self-test (BIST) are increasingly used to reduce test cost. In these test architectures, many internal signals are observed through a small number of output pins or into a small signature analyzer, requiring a combinational space compactor. This paper analyzes the basic requirements of compactors to support efficient test and diagnosis, focusing on practical compactors wher... View full abstract»

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  • Efficient seed utilization for reseeding based compression [logic testing]

    Publication Year: 2003, Page(s):232 - 237
    Cited by:  Papers (31)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (280 KB) | HTML iconHTML

    The conventional LFSR reseeding technique for test data compression generates one test pattern from each LFSR seed. The seed size is determined by the maximum number of specified bits in a test pattern belonging to a given test set. However, for most practical designs the majority of test patterns have significantly fewer specified bits compared to the maximum. This limits the amount of compressio... View full abstract»

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  • SOC test scheduling using simulated annealing

    Publication Year: 2003, Page(s):325 - 330
    Cited by:  Papers (39)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (730 KB) | HTML iconHTML

    We propose an SOC test scheduling method based on simulated annealing. In our method, the test scheduling is formulated as a two-dimensional bin packing problem (rectangle packing) and a data structure called a sequence pair is used to represent the placement of the rectangles. Simulated annealing is used to find the optimal test schedule by altering an initial sequence pair and changing the width... View full abstract»

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  • Test generation for maximizing ground bounce considering circuit delay

    Publication Year: 2003, Page(s):151 - 157
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (317 KB) | HTML iconHTML

    In this paper, we focus on the aspect of ground bounce due to the combination of current produced by gates (signals) switching and the flow of this current through pin electronics. We present a branch-and-bound test generation procedure to obtain high quality 2-vector tests that produce a large amount of ground bounce. We present a framework that accurately captures the relationship between a test... View full abstract»

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  • Built-in TPG with designed phaseshifts

    Publication Year: 2003, Page(s):365 - 370
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (307 KB) | HTML iconHTML

    In this paper, we present built-in test pattern generation (TPG) mechanisms that can enforce a prescribed exact set of phaseshifts, or channel separations, on the bit sequences produced by their successive stages, while still requiring low hardware overhead. Such mechanisms are used in controlling the amount of correlations and/or linear dependencies that are problematic for pseudorandom and pseud... View full abstract»

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  • An efficient test relaxation technique for synchronous sequential circuits

    Publication Year: 2003, Page(s):179 - 185
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (296 KB) | HTML iconHTML

    Testing systems-on-a-chip (SOC) involves applying huge amounts of test data, which is stored in the tester memory and then transferred to the circuit under test (CUT) during test application. Therefore, practical techniques, such as test compression and compaction, are required to reduce the amount of test data in order to reduce both the total testing time and the memory requirements for the test... View full abstract»

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  • Testable design and testing of micro-electro-fluidic arrays

    Publication Year: 2003, Page(s):403 - 409
    Cited by:  Papers (22)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (373 KB) | HTML iconHTML

    The testable design and testing of a fully software-controllable lab-on-a-chip, including a fluidic array of FlowFETs, control and interface electronics is presented. Test hardware is included for detecting faults in the DMOS electro-fluidic interface and the digital parts. Multidomain fault modeling and simulation shows the effects of faults in the (combined) fluidic and electrical parts. The fau... View full abstract»

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  • A circuit level fault model for resistive opens and bridges

    Publication Year: 2003, Page(s):379 - 384
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (300 KB) | HTML iconHTML

    Delay faults are an increasingly important test challenge. Traditional open and bridge fault models are incomplete because only the functional fault or a subset of delay fault are modeled. In this paper, we propose a circuit level model for resistive open and bridge faults. All possible fault behaviors are illustrated and a general resistive bridge delay calculation method is proposed. The new mod... View full abstract»

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